2. The Beginning 1947 : Point Contact Transistor BELL LABS : Bardenn, Brattain & Shockley * William Shockley : 1956 Nobel Prize in Physics
3. Integrated Circuit from 1960 to 2010 1961 First planer IC "flip-flop" 2010 IBM POWER7 transistors: 1.2 B Invented by Robert Noyce , Fairchild *integrated circuit Invented by Jack Kilby , Texas Instruments *cmos 45 , 5 GHz, cache, D ual DDR3 memory controllers Level 1 & 2 caches remain SRAM ,32MB eDRAM on-chip Level 3
4. Processor Evolution 1979 MOTOROLA 68000 the Most Powerful µp16-Bit 40k transistors 1971 Intel 4004 The First µp 4-Bit 2,25k transistors,24mm2 1976 Zilog Z80 the Most Popular µp 8-bit 4,5k transistors 1993 Intel Pentium 32 bit 3.1M transistors 2003 AMD Opteron 64 bit 233M transistors 2008 AMD Barcelona Quad-Core 128 bit 463M transistors ,283 mm2
5. Moore's Law : 1960 -Number of transistors on integrated circuit : Doubling every two years. -RAM storage capacity & Power consumption : Doubling every 18 months. *Gordon Moore
8. Human Brain In 2010, the semiconductor industry Manufactured roughly 1 billion transistors for every human on the planet;
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10. NMOS Transistor Basics 1. Cut-off Region: no channel exists (iD = 0) for all values of VD. (VGS < Vt) 2. Triode Region: The NMOS transistor is active and not “pinched off.” This means the value of VDS affects the value of iD (VGS > Vt and VDS ≤ VGS – Vt). 3. Saturation Region: The channel is “pinched off” because increases in VD have no affect on iD (VGS > Vt and VDS > VGS – Vt)
11. Saturation Region Technology fixed parameters : μ eff : is the charge-carrier effective mobility, Cox : is the gate oxide capacitance per unit area m : is the Body effect Vt : is the threshold voltage Fixed by designer : W : is the gate width L : is the gate length (L min fixed by the Technology ) V gs ( = Vdd)
12. NMOS & PMOS Transistor complementary and symmetrical pairs of p-type and n-type MOSFETs transistor
19. Stepper Costing several hundred to several thousand million yen ASML, Ultratech, Nikon, Canon - Early days of lithography used 456 nm wavelength light. - Lithography today is using 193 nm wavelength light.
22. Defect on ASIC Defect increase as cmos technology shrinks Defect on metal 1 wire malfunction of wire bonding machine Number of defect Transistor shrink Burnt part During test.
25. Power Dissipation Thermal dissipation Traditional Power saving : -Lower the clock frequency (F clk ) -Lower the load capacity (C l ) -Lower the rail voltage (V dd ) Dynamic Power : C l V dd 2 P trans F clk Static Power : leakage gate thickness New Power saving technique : -Power gating, Clock gating -Voltage & frequency scaling -Multi-voltage, Multi-threshold logic
27. Application Specific Integrated Circuit ASIC Semi- specific specific Programmable FPGA Sea of gate Standard cell Full Custom SOC Image sensor MEMS
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31. Image Sensors (example) - 352 x 288 image array - 60 frames per second image capture - Advanced algorithms to : cancel Fixed Pattern Noise (FPN), Eliminate smearing, reduce blooming. - Programmable I2C : control, gamma, gain, white balance, color matrix, windowing, and image output in either 4-, 8- or 16 bit digital formats
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34. Advantages : => mixed system possible ( analog/digital) => internal flexibility => high density Disadvantages : => middle cost => technology transistors / standard cell imposed and fixed => complex to master the technology Sea of Gate or masked gate array (MGA)
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36. Advantages : => complete control of time parameters and electrical => mixed system possible ( analog/digital/memes ) => flexibility => very high density => Low Power, high speed techniques Disadvantages : => High cost ( $20M and up for chips designed at 90nm) => hard and complex to master the technology => few companies (low competition) => High volume Product ASIC Standard Cell
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38. Advantages: => Technology easy to master => Reduced development time => Reprogrammable for some (ideal for prototyping) => Low cost Disadvantages: => Non-optimized performance => Internal architecture completely frozen => Only digital (with some exceptions) FPGA Field Programmable Gate Array
40. FPGA Vs ASIC high moderate/high moderate /high All interconnection Weeks /months Weeks /months Standard Cell Very high moderate low cost high moderate moderate speed high low Very low Density All interconnection none Masks manufactories All interconnection none Masks designs Weeks /months minutes/hours minutes/hours Modification time months /years Weeks /months days/weeks Development time Full Custom Sea of gate FPGA
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42. Examples of fixed costs: training cost for a new electronic design automation ( EDA ) system hardware and software cost • productivity • production test and design for test • programming costs for an FPGA • nonrecurring-engineering ( NRE ) • test vectors and test-program development cost • pass ( turn or spin ) • profit model represents the profit flow during the product lifetime • product velocity • second source
43. FPGA Vs ASIC A break-even analysis for an FPGA, a masked gate array (MGA) and a custom cell-based ASIC (CBIC). Cost parts Number of parts or volume $1.000.000 $100.000 $10.000 10 100 1000 10.000 100.000 break-even FPGA / CBIC break-even FPGA / MGA break-even MGA / CBIC CBIC MGA FPGA
44. FPGA Vs ASIC ASICs comprise three separate regions, each with its own complexity, performance and cost characteristics.
48. Market Forecast 15% FPGA provide the customizability of an ASIC without theneed to design and fab new devices for each platform. Xilinx has more software engineers than hardware engineers; at Altera, the mix is roughly 50-50.
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50. FPGA interconnect Logic Block Switch Block Wire Segment Programmable Switch a c b e d f a=0 b=0 c=1 d=0 e=1 f=0 0 0 1 0 1 0 Programmable FPGA Memory RAM/ROM c e
58. Spartan-3 : Dedicated Multipliers -Embedded multipliers that accept two 18-bit words as inputs to produce a 36-bit product. - The input buses to the multiplier accept data in two’s-complement form (either 18-bit signed or 17-bit unsigned).
