5. always @(posedge clk) begin
a <= b;
b <= a;
end
process(clk)
begin
if rising_edge(clk) then
a <= b;
b <= a;
end if;
end process;
!!
… { pragma }
VHDL/VerilogHDL
C/C++
22. for _, decl := range file.Decls {
switch td := decl.(type) {
case *ast.GenDecl:
switch td.Tok {
case token.IMPORT:
case token.TYPE:
case token.CONST:
case token.VAR:
for _, sp := range td.Specs {
s := sp.(*ast.ValueSpec)
case *ast.FuncDecl:
b := target.AddBoard(&Board{Name: td.Name.Name, Module: target})
if td.Recv != nil {
fmt.Println(td.Recv.List[0].Type)
}
if td.Type.Params != nil && td.Type.Params.NumFields() > 0 {
for _, p := range td.Type.Params.List {
for _, n := range p.Names {
t := convTypeFromExpr(p.Type)
b.AddVariable(&Variable{Name: n.Name, MethodParam: true,
OriginalName: n.Name, MethodName: td.Name.Name, Type: t})
}
}
}
if td.Type.Results != nil && td.Type.Results.NumFields() > 0 {
Go
!!