1. General N-Tap Data Permutation Engine Magdi Mohamed Motorola Labs, PRR CoE 2006-08-29 An Indirect Sorting Hardware Architecture Using Threshold Decomposition Techniques

2. Typical Use N=5 Tap Q-Filter Computations h 5 <h 2 < h 1 <h 3 < h 4 h 4 x 1 x 2 x 3 x 4 x 5 f 1 f 2 f 3 f 4 f 5 Window Slots Signal Value h 1 h 2 h 3 h 5 Density Generators i  h 5 h 2 h 1 h 3 h 4 Threshold Kernel Parameter  h(x i ) q(A  ) q({x 4 }) q({x 4 , x 3 }) q({x 4 , x 3 , x 1 }) q({x 4 , x 3 , x 1 , x 2 }) q({x 4 , x 3 , x 1 , x 2 , x 5 })=1.0 Case Adaptive Weight  A  q(  )=0.0 Total area is the Q-Filter output value

4. Innovation An Indirect Sorting Hardware Architecture Using Threshold Decomposition Techniques 14 00 21 31 02 09 24 18 03 1 2 3 4 5 6 7 8 9 2 5 9 6 1 8 3 7 4 1 2 3 4 5 6 7 8 9

5. Simulation of Invention N=9 Tap Sorting of Random Real-Valued Digital Input Cases

7. Analyzing the Complexity Bitonic Sorting Network (BSN) Versus Data Permutation Engine (DPE) n 2 n 2 n 2 n log 4 n worst seq cost efficiency, e(n) = c(n) n 2 1 n 2 log 2 n worst seq time speedup, s(n) = t(n) n 2 n log 4 n overall cost, c(n) = t(n) p(n) n 2 n log 2 n number of processors, p(n) 1 log 2 n running time, t(n) DPE (Novel Art) BSN (Prior Art) Architecture Complexity

8. How Big is the Saving in Cost? BSN DPE