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Digital logic circuits important question and answers for 5 units
1 Digital Logic Circuits 2 marks1) Given the two binary numbers X = 1010100 and Y = 1000011, perform the subtraction (a)X -Y and (b) Y - X using 2’s complements. a) X = 1010100 2’s complement of Y = + 0111101 -------------- Sum = 10010001 Discard end carry Answer: X - Y = 0010001 b) Y = 1000011 2’s complement of X = + 0101100 --------------- Sum = 1101111 There is no end carry, Therefore the answer is Y-X = -(2’s complement of 1101111) = -00100012). Given the two binary numbers X = 1010100 and Y = 1000011, perform the subtraction (a)X -Y and (b) Y - X using 1’s complements. a). X - Y = 1010100 – 1000011 X = 1010100 1’s complement of Y = + 0111100 -------------- Sum = 10010000 End -around carry = + 1 -------------- Answer: X - Y = 0010001 b). Y - X = 1000011 – 1010100 Y = 1000011 1’s complement of X = + 0101011 ----------- Sum = + 1101110 There is no end carry. Therefore the answer is Y - X = -(1’s complement of 1101110) = -00100013). what is meant by parity bit? A parity bit is an extra bit included with a message to make the total number of 1’s eithereven or odd. Consider the following two characters and their even and odd parity: With even paritywith odd parity ASCII A = 1000001 01000001 11000001, ASCII T = 1010100 1101010001010100. In each case we add an extra bit in the left most position of the code to produce an evennumber of1’s in the character for even parity or an odd number of 1’s in the character for oddparity. The parity bit is helpful in detecting errors during the transmission of information from onelocation to another.4).What are registers? Register is a group of binary cells. A register with n cells can store any discrete quantity ofinformation that contains n bits. The state of a register is an n-tuple number of 1’s and 0’s, witheach bit designating the state of one cell in the register.5). What is meant by register transfer? A register transfer operation is a basic operation in digital systems. It consists of transfer ofbinary information from one set of registers into another set of registers. The transfer may be directfrom one register to another, or may pass through data processing circuits to perform an operation.6). Define binary logic?
2 Binary logic consists of binary variables and logical operations. The variables are designatedby the alphabets such as A, B, C, x, y, z, etc., with each variable having only two distinct values: 1and 0. There are three basic logic operations: AND, OR, and NOT.7). Define logic gates? Logic gates are electronic circuits that operate on one or more input signals to produce anoutput signal. Electrical signals such as voltages or currents exist throughout a digital system ineither of two recognizable values. Voltage- operated circuits respond to two separate voltage levelsthat represent a binary variable equal to logic 1 or logic 0.8).Define duality property. Duality property states that every algebraic expression deducible from the postulates ofBoolean algebra remains valid if the operators and identity elements are interchanged. If the dual ofan algebraic expression is desired, we simply interchange OR and AND operators and replace 1’sby 0’s and 0’s by 1’s.9).Find the complement of the functions F1= x’yz’ + x’y’z and F2= x(y’z’ + yz) by applying DeMorgan’s theorem as many times as necessary. F1’ = (x’yz’ + x’y’z)’ = (x’yz’)’(x’y’z)’ = (x + y’ + z)(x + y +z’) F2’ = [x(y’z’ + yz)]’ = x’ + (y’z’ + yz)’ = x’ + (y’z’)’(yz)’ = x’ + (y + z)(y’ + z’)10).Find the complements of the functions F1 = x’yz’ + x’y’z and F2 = x(y’z’ + yz) by takingtheir duals and complementing each literal. F1= x’yz’ + x’y’z. The dual of F1 is (x’ + y + z’)(x’ + y’ + z). Complementing each literal: (x + y’ + z)(x + y + z’) F2= x(y’z’ + yz). The dual of F2 is x + (y’ + z’)(y + z). Complement of each literal: x’ + (y + z)(y’ + z’)11).State De Morgan’s theorem. De Morgan suggested two theorems that form important part of Boolean algebra. They are,1) The complement of a product is equal to the sum of the complements. (AB)’ = A’ + B’ 2) Thecomplement of a sum term is equal to the product of the complements. (A + B)’ = A’B’12).Reduce A.A’C A.A’C = 0.c [A.A’ = 1] = 013). Reduce A(A + B) A(A + B) = AA + AB = A(1 + B) [1 + B = 1] = A.14. Reduce A’B’C’ + A’BC’ + A’BC A’B’C’ + A’BC’ + A’BC = A’C’(B’ + B) + A’B’C = A’C’ + A’BC [A + A’ = 1] = A’(C’ + BC) = A’(C’ + B) [A + A’B = A + B]15.) Reduce AB + (AC)’ + AB’C(AB + C) AB + (AC)’ + AB’C(AB + C) = AB + (AC)’ + AAB’BC + AB’CC = AB + (AC)’ + AB’CC [A.A’ = 0] = AB + (AC)’ + AB’C [A.A = 1] = AB + A’ + C’ =AB’C [(AB)’ = A’ + B’] = A’ + B + C’ + AB’C [A + AB’ = A + B] = A’ + B’C + B + C’ [A + A’B = A + B] = A’ + B + C’ + B’C =A’ + B + C’ + B’ =A’ + C’ + 1 = 1 [A + 1 =1]
316. Simplify the following expression Y = (A + B)(A + C’ )(B’ + C’ ) Y = (A + B)(A + C’ )(B’ + C’ ) = (AA’ + AC +A’B +BC )(B’ + C’) [A.A’ = 0] = (AC + A’B + BC)(B’ + C’ ) = AB’C + ACC’ + A’BB’ + A’BC’ + BB’C + BCC’ = AB’C + A’BC’17).Simplify the following using De Morgan’s theorem [((AB)’C)’’ D]’ [((AB)’C)’’ D]’ = ((AB)’C)’’ + D’ [(AB)’ = A’ + B’] = (AB)’ C + D’ = (A’ + B’ )C + D’18.Show that (X + Y’ + XY)( X + Y’)(X’Y) = 0 (X + Y’ + XY)( X + Y’)(X’Y) = (X + Y’ + X)(X + Y’ )(X’ + Y) [A + A’B = A + B] = (X + Y’ )(X + Y’ )(X’Y) [A + A = 1] = (X + Y’ )(X’Y) [A.A = 1] = X.X’ + Y’.X’.Y = 0 [A.A’ = 0]19).Prove that ABC + ABC’ + AB’C + A’BC = AB + AC + BC ABC + ABC’ + AB’C + A’BC =AB(C + C’) + AB’C + A’BC =AB + AB’C + A’BC =A(B + B’C) + A’BC =A(B + C) + A’BC =AB + AC + A’BC =B(A + C) + AC =AB + BC + AC =AB + AC +BC ...Proved20).Convert the given expression in canonical SOP form Y = AC + AB + BC Y = AC + AB + BC =AC(B + B’ ) + AB(C + C’ ) + (A + A’)BC =ABC + ABC’ + AB’C + AB’C’ + ABC + ABC’ + ABC =ABC + ABC’ +AB’C + AB’C’ [A + A =1]21).Convert the given expression in canonical POS form Y = ( A + B)(B + C)(A + C) Y = ( A + B)(B + C)(A + C) = (A + B + C.C’ )(B + C + A.A’ )(A + B.B’ + C) = (A + B + C)(A + B + C’ )(A + B +C)(A’ + B +C)(A + B + C)(A + B’ + C) [A + BC = (A + B)(A + C) Distributive law] = (A + B + C)(A + B + C’)(A’ + B + C)(A’ + B + C)(A + B’ + C)22). Find the minterms of the logical expression Y = A’B’C’ + A’B’C + A’BC + ABC’ Y = A’B’C’ + A’B’C + A’BC + ABC’ =m0 + m1 +m3 +m6 =ôP____________23).Write the maxterms corresponding to the logical expression Y = (A + B + C’ )(A + B’ +C’)(A’ + B’ + C) Y = (A + B + C’ )(A + B’ + C’)(A’ + B’ + C) =M1.M3.M6 =ö0_______24).Convert (4021.2)5to its equivalent decimal. (4021.2)5= 4 x 53+ 0 x 52+ 2 x 51+ 1 x 50+ 2 x 5-1 = (511.4)10
425) Using 10’s complement subtract 72532 – 3250 M = 72532 10’s complement of N = + 96750 ----------- Sum = 169282 Discard end carry Answer = 6928226) What are called don’t care conditions? In some logic circuits certain input conditions never occur, therefore the correspondingoutput never appears. In such cases the output level is not defined, it can be either high or low.These output levels are indicated by ‘X’ or‘d’ in the truth tables and are called don’t care conditionsor incompletely specified functions.27) Write down the steps in implementing a Boolean function with levels of NAND Gates? Simplify the function and express it in sum of products. Draw a NAND gate for eachproduct term of the expression that has at least two literals. The inputs to each NAND gate are theliterals of the term. This constitutes a group of first level gates. Draw a single gate using the AND-invert or the invert-OR graphic symbol in the second level, with inputs coming from outputs of firstlevel gates. A term with a single literal requires an inverter in the first level. How ever if the singleliteral is complemented, it can be connected directly to an input of the second level NAND gate.28) Give the general procedure for converting a Boolean expression in to multilevel NANDdiagram? Draw the AND-OR diagram of the Boolean expression. Convert all AND gates to NANDgates with AND-invert graphic symbols. Convert all OR gates to NAND gates with invert-ORgraphic symbols. Check all the bubbles in the same diagram. For every bubble that is notcompensated by another circle along the same line, insert an inverter or complement the inputliteral.29) What are combinational circuits? A combinational circuit consists of logic gates whose outputs at any time are determinedfrom the present combination of inputs. A combinational circuit performs an operation that can bespecified logically by a set of Boolean functions. It consists of input variables, logic gates, andoutput variables.30) Give the design procedures for the designing of a combinational circuit. The procedure involves the following steps, From the specification of the circuit, determinethe required number of inputs and outputs and assign a symbol to each. Derive the truth table thatdefines the required relationships between inputs and outputs. Obtain the simplified Booleanfunctions for each output as a function of the input variables. Draw the logic diagram and verify thecorrectness of the design.31) Define half adder. A combinational circuit that performs the addition of two bits is called a half adder. A halfadder needs two binary inputs and two binary outputs. The input variables designate the augend andaddend bits; the output variables produce the sum and carry32) Define full adder? A combinational circuit that performs the adtion of three bits is a full adder.It consists ofthree inputs and two outputs.33) Define binary adder. A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. Itcan be constructed with full adders constructed in cascade, with the output carry from each fulladder connected to the input carry of the next full adder in the chain.
534) What is overflow? Over flow is a problem in digital computers because the number of bits that hold the numberis finite and a result that contains n + 1 bits cannot be accommodated. For this reason manycomputers detect the occurrence of an overflow, and when it occurs a corresponding flip flop is setthat can be checked by the user. An overflow condition can be detected by observing the carry intosign bit position and the carry out of the sign bit position. If these two carries are not equal, anoverflow has occurred.35) Define magnitude comparator? A magnitude comparator is a combinational circuit that compares two numbers, A and B,and determines their relative magnitudes. The outcome of the comparison is specified by threebinary variables that indicate whether a>b, A = b, or A < B.36) What are decoders? A decoder is a combinational circuit that converts binary information from n input lines to amaximum of 2n unique output lines. If the n bit coded information has unused combinations, hedecoder may have fewer than 2n outputs.37) What are encoders? An encoder is a digital circuit that performs the inverse operation of a decoder. An encoderhas 2n and n output lines. The output lines generate the binary code corresponding to the inputvalue.38) Define priority encoder? A priority encoder is an encoder circuit that includes the priority function. The operation ofpriority encoder is such that if two or more inputs are equal to 1 at the same time, the input havingthe highest priority will take precedence.39) Define multiplexer? A multiplexer is combinational circuit that selects binary information from one of manyinput lines and directs it to a single output line. The selection of a particular input line is controlledby a set of selection lines. Normally there are 2n input lines and n selection lines whose bitcombinations determine which input is selected.40) Define binary decoder? A decoder which has an n- bit binary input code and a one activated output out-of -2n outputcode is called binary decoder. A binary decoder is used when it is necessary to activate exactly oneof 2n outputs based on an n-bit input value.41. Represent binary number 1101 - 101 in power of 2 and find its decimal equivalent N = 1 x 2 3 + 1 x 2 2 + 0 x 2 1 + 1 x 2 0 + 1 x 2 -1 + 0 x 2 -2 + 1 x 2 -3 = 13.625 1042. Convert (634) 8 to binary 634 110 011 100 Ans = 110 011 100 43. Convert (9 B 2 - 1A) H to its decimal equivalent. N = 9 x 16 2 + B x 16 1 + 2 x 16 0 + 1 x 16 -1 + A (10) x 16 -2 = 2304 + 176 + 2 + 0.0625 + 0.039 = 2482.1 10 44. What are the different classifications of binary codes? 1. Weighted codes 2. Non - weighted codes 3. Reflective codes 4. Sequential codes 5.Alphanumeric codes 6. Error Detecting and correcting codes
645. Convert 0.640625 decimal number to its octal equivalent. 0.640625 x 8 = 5.125 0.125 x 8 = 1.0 Ans. = 0.640 625 10 = 0.5146. Convert 0.1289062 decimal number to its hex equivalent 0.1289062 x 16 = 2.0625 0.0625 x 16 = 1.0 Ans. = 0.21 16 47. Convert decimal number 22.64 to hexadecimal number. 16 22 -6 16 1 -1 0 0.64 x 16 = 10.24 0.24 x 16 = 3.84 0.84 x 16 = 13.44 .44 x 16 = 7.04 Ans. = (16 . A 3 D 7) 16.348. What are the two steps in Gray to binary conversion? The MSB of the binary number is the same as the MSB of the gray code number. So write itdown.To obtain the next binary digit, perform an exclusive OR operation b/n the bit just writtendown and the next gray code bit. Write down the result. 49. Convert gray code 101011 into its binary equivalent. Gray Code : 1 0 1 0 1 1 Binary Code 1 1 0 0 1 0 50. Convert 10111011 is binary into its equivalent gray code. Binary Code: 1 0 1 1 1 0 1 0 1 1 Gray code : 1 1 1 0 0 1 1 0 1010 0011 110152. Substract (0 1 0 1) 2 from (1 0 1 1) 2 101001010110 53. Find 2’S complement of (1 0 1 0 0 0 1 1) 2 0 1 0 1 1 1 0 0 1 1’s Complement +00000001 0 1 0 1 1 1 0 1 0 2’s complement. 54. Substract 1 1 1 0 0 1 2 from 1 0 1 0 1 1 2 using 2’s complement method 101011 + 0 0 0 1 1 1 2’s comp. of 1 1 1 0 0 1 1 1 0 0 1 0 Ans. in 2’s complement form - 0 0 1 1 1 0 Answer in true form.55. What are the advantages of 1’s complement subtraction? 1) The 1’s complement subtraction can be accomplished with an binary adder. Therefore,this method is useful in arithmetic logic circuits. 2) The is complement of a number is easilyobtained by inverting each bit in the number
756. Find the excess -3 code and 9’s complement of the number 403 10 403 010000000011 001100110011+ 0 1 1 1 0 0 1 1 0 1 1 0 excess 3 code 9’s complement 1 0 0 0 1 1 0 0 1 0 0 157. Write the names of basic logical operators. 1. NOT / INVERT 2. AND 3. OR58. Simplify the following expression y = (A + B) (A = C) (B + C) = (A A + A C + A B + B C) (B + C) = (A C + A B + B C) (B + C) =ABC+ACC+ABB+ABC+BBC+BCC =ABC=ABC59. Show that the NAND connection is not associative The NAND connection is not associative says that A . B . C A . B. C A.B+CA+BC AB + C A + BC 60. What is a Logic gate? Logic gates are the basic elements that make up a digital system. The electronic gate is acircuit that is able to operate on a number of binary inputs in order to perform a particular logicalfunction.61. Write the names of Universal gates. 1. NAND gate 2. NOR gate62. Why are NAND and NOR gates known as universal gates? The NAND and NOR gates are known as universal gates, since any logic function can beimplemented using NAND or NOR gates.63. Define combinational logic When logic gates are connected together to produce a specified output for certain specifiedcombinations of input variables, with no storage involved, the resulting circuit is calledcombinational logic.64. Explain the design procedure for combinational circuits ¢ The problem definition ¢ The determination of number of available input variables &required O/P variables. ¢ Assigning letter symbols to I/O variables ¢ Obtain simplified booleanexpression for each O/P. ¢ Obtain the logic diagram.65. Define half adder and full adder The logic circuit which performs the addition of two bits is a half adder. The circuit whichperforms the addition of three bits is a full adder. 66. Define Decoder? A decoder is a multiple - input multiple output logic circuit which converts coded inputs intocoded outputs where the input and output codes are different.67. What is binary decoder? A decoder which has an n-bit binary i/p code and a one activated output out of 2l. outputcode is called binary decoder. It is used when it is necessary to activate exactly one of 2 n out putsbased on an n - bit input value.
868. Define Encoder? An encoder has 2n input lines and n output lines. In encoder the output lines gener- ate thebinary code corresponding to the input value.69. What is priority Encoder? A priority encoder is an encoder circuit that includes the priority function. In priorityencoder, if 2 or more inputs are equal to 1 at the same time, the input having the highest prioritywill take precedence.70. Define multiplexer? Multiplexer is a digital switch. If allows digital information from several sources to berouted onto a single output line.71. What do you mean by comparator A comparator is a special combinational circuit designed primarily to compare the relativemagnitude of two binary numbers.72. List basic types of programmable logic devices. 1. Programmable Read only memory (PROM) 2. Programmable logic Arrays (PLA) 3. Programmable Array Logic (PAL) 4. Field Programmable Gate Array (FPGA) 5. Complex Programmable Logic Devices (CPLD)73. Define ROM A read only memory is a device that includes both the decoder and the OR gates within asingle IC package.74. Define address and word: In a ROM, each bit combination of the input variable is called on address. Each bitcombination that comes out of the output lines is called a word.75. What are the types of ROM 1. Masked ROM. 2. Programmable Read only Memory 3. Erasable Programmable Read only memory. 4. Electrically Erasable Programmable Read only Memory.76. What is programmable logic array? How it differs from ROM? In some cases the number of don™t care conditions is excessive,it is more economical to use a second type of LSI component called a PLA A PLA is similar to aROM in concept; however it does not provide full decoding of the variables and does not generatesall the minterms as in the ROM..77. What is mask - programmable? With a mask programmable PLA, the user must submit a PLA program table to themanufacturer.78. What is field programmable logic array? The second type of PLA is called a field programmable logic array. The EPLA can beprogrammed by the user by means of certain recommended procedures.79. Give the comparison between prom and PLA. PROM 1. AND array is fixed and OR array is programmable 2. Cheaper and simple to use. PLA 1. Both AND and OR arrays are Programmable 2. Costliest and complex thanPROMS.
980. Define even parity In even parity the added parity bit will make the total number of 1s an even amount.81. Define sequential circuit? In sequential circuits the output variables dependent not only on the present input variablesbut they also depend up on the past history of these input variables.82. Give the comparison between combinational circuits and sequential circuits. Memory unit is not required Memory unity is required Parallel adder is a combinationalcircuit Serial adder is a sequential circuit83. What do you mean by present state? The information stored in the memory elements at any given time define™s the present stateof the sequential circuit.84. What do you mean by next state? The present state and the external inputs determine the outputs and the next state of thesequential circuit.85. What are the types of sequential circuits? 1. Synchronous sequential circuits 2. Asynchronous sequential circuits86. Define synchronous sequential circuit In synchronous sequential circuits, signals can affect the memory elements only at discreteinstant of time.87. Define Asynchronous sequential circuit? In asynchronous sequential circuits change in input signals can affect memory element atany instant of time88. Define flip-flop Flip - flop is a sequential device that normally. samples its inputs and changes its outputsonly at times determined by clocking signal.89. List various types of flip-flop 1] S.R. latch 2] D latch 3] Clocked J.K. flip-flop 4] T flip-flop90. What is race around condition? In the JK latch, the output is feedback to the input, and therefore change in the output resultschange in the input. Due to this in the positive half of the clock pulse if J and K are both high thenoutput toggles continuously. This condition is known as race around condition.91. Define rise time and fall time? The time required to change the voltage level from 10% to 90% is known as rise time, andthe time required to change the voltage level from 90% to 10% is known as fall time.92. Define propagation Delay? A propagation delay is the time required to change the output after application of the input.93. Define shift Registers The binary information in a register can be moved from stage to stage within the register orinto or out of the register upon application of clock pulses. This type of bit movement or shifting isessential for certain arithmetic and logic operations used in microprocessors. This gives rise to agroup of registers called shift registers.94. What are the types of shift register? 1. Serial in serial out shift register? 2. Serial in parallel out shift register 3. Parallel in serialout shift register 4. Parallel in parallel out shift register 5. Bidirectional shift register shift register.95. What are the types of counter? 1. Synchronous counter 2. Asynchronous Counter
1096. What are the two models in synchronous sequential circuits. 1. Moore circuit 2. Mealy circuit97. What is moore circuit? When the output of the sequential circuit depends only on the present state of the flip-flop,the sequential circuit is referred to as moore circuit.98. What is Mealy circuit? When the output of the sequential circuit depends on both the present state of flip- flop andon the input, the sequential circuit is referred to as mealy circuit.99. Define successor In a state diagram, if an input sequence, x takes a machine from state si to state sj, then sj issaid to be the x - successor of si.100. Define strongly connected machine? In a sequential machine many times certain subsets of states may not be reachable fromother subsets of states, even if the machine does not contain any terminal state. However, if forevery pair of states si, sj of a sequential machine, there eights an input sequence which takes Mfrom Si to Sj then sequential machine M is said to be strongly connected.101. State and prove consensus theorem in Boolean algebra? In simplification of Boolean expression, the redundant term in an expression can beeliminated to form the equivalent expression. The theorem used for this simplification is calledconsensus theorem. For ex in expression of the AB+A’C+BC, the term BC is redundant and can beeliminated using Consensus theorem.102. What do you mean by Literal? In Boolean function, the total numbers of variables in complemented or uncomplementedform are called literals.103. Give Applications of MUX?Applications: 1. MUX can be used to realize a Boolean function 2. It can be used in communication systems e.g. time division multiplexing104. Define Latch? It is a sequential device that checks all of its inputs continuously and changes its outputsaccordingly at any time, independent of a clocking signal.105. What is Lock out? In a counter, if the next state of some unused state is again some unused state, it may happenthat the counter remains in unused state never to arrive at a used state. Such a condition is calledLock out condition.106. How to avoid Lock out Condition? 1. The counter should be provided with an additional circuit. This will force the counter from an unused state to the next state as initial state. 2. It is not always necessary to force all unused states into an initial state. Because from unused states which are not forced, the circuit may eventually arrive at a forced unused state. This frees the circuit from the Lock out condition.107. State the advantages and disadvantages of Totem pole output?Advantages: 1. External pull up resistor is not required 2. Operating speed is high
11Disadvantages: Output of two gates cannot be tied together.108. Explain the wired And connection? When the open collector outputs of two or more gates can be connected together, theconnection is called a wired AND. It is represented as: 1. In wired AND connection, the output is high only when all the switches are open 2. Hence, the output is equivalent to the logical AND operation of the logic function performed by the gates.109. State the advantages and disadvantages of wired AND connection. Advantage is, Outputs of two gates can be tied together using wired-AND technique. Disadvantage is, Operating Speed is Low.110. What is open collector output. When the collector terminal of the transistor is kept open without any pull up transistor the arrangement is called open collector output. 16 marks UNIT I1. Determine the prime-implicants of the Boolean function by using the tabulation method(w, x, y, z)=Σ(1,4,6,7,8,9,10,11,15) (Refer pg: 1.62 – 1.64 in Godse)2. Simplify the following Boolean expression using Quine McCluskey method: F=∑m(0,9,15,24,29,30)+d(8,11,31). (Refer pg : 1.66 – 1.68 in Godse)3. Design a combinational logic diagram for BCD to Excess-3 code converter. (Refer pg: 3.36,3.37 in Godse)4. Find a minimum sum of products expression for the following function using Quine- McClusky method. F (A,B,C,D,E) = ∑(0,2,3,5,7,9,11,13,14,16,18,24,26,28,30) (Refer pg: 1.62 -1.64 in Godse)5. Determine the minimum sum of products and minimum product of sums for f = b’c’d’+bcd+acd’+ab’bc’d. (Refer pg: 1.42 & 1.54 in Godse)6. Find the minterm expansion of f (a, b, c, d) = a’ (b’+d) +acd’ (Refer notes)7. Explain with necessary diagram a BCD to 7 segment display decoder. (Refer pg: 3.55 – 3.59 in Godse)9. With a suitable block diagram explain the operation of BCD adder (Refer pg: 3.20 – 3.22 in Godse)10. Draw and explain the working of a carry-look ahead adder. (Refer pg: 3.15 – 3.18 in Godse) UNIT II 1. Design a MOD – 10 synchronous counter using JK flip-flops. Write the excitation table and state table. (Refer pg: 5.37, 5.38 in Godse) 2. Design a sequential circuit with four flip-flops ABCD. The next states of B, C, and D are equal to the present states of A, B, C respectively. The next state of A is equal to the EX- OR of present states of C and D. (Refer pg: 5.86 in Godse) 3. Design a mod- 7 counter using JK flip-flops. (Refer pg: 5.49 - 5.51 in Godse) 4. Design a BCD Up / Down counter using S R flip-flops. (Refer pg: 5.98 – 5.102 in Godse) 5. Design a synchronous decade counter using D flip-flops. (Refer pg: 5.92, 5.93 in Godse)
12 6. Explain the working of JK flip- flop. What is race around condition? How is it overcome? Explain these concepts with relevant timing diagrams. (Refer pg: 4.13 -4.16 in Godse) 7. Design a 3 – bit up / down counter using JK flip – flops and Explain its working with timing diagrams. (Refer pg: 5.42, 5.43 in Godse) 8. Using SR flip-flops design a parallel counter, which counts in the sequence 101,110,001,010,000,111,101…(Refer pg: 5.81, 5.82 in Godse) 9. Design a synchronous sequential counter using JK flip-flop and avoid lock out condition, for 4→6→7→3→1→4… (Refer pg: 5.28, 5.29 in Godse) 10. Expalin the operation of Master Slave JK flip-flop with suitable diagrams. (Refer 4.17 – 4.19 in Godse) UNIT III1. Design an asynchronous sequential circuit that has two inputs X1 and X1 and one output Z. When X1=0, the output Z is 0. The first change in X2 that occurs while X1 is 1 will cause output Z to be 1. The output Z will remain 1 until X1 returns to 0. (Refer pg: 6.18-6.21 in Godse)2. Design a pulse mode circuit having two input lines X1 and X2 and one output line Z. The circuit should produce an output pulse to coincide with the last input pulse in the sequenceX1, X2, X2. No other input sequence should produce an output pulse. (Refer pg: 6.34 – 6.35 in Godse)3. Draw the state diagram and obtain the primitive flow table for a circuit with two inputs x1 and x2 and two outputs z1 and z2 that satisfies the following conditions. 1. When x1x2=00, output z1z2=00. 2. When x1=1 and x2 changes from 0 to 1, the output z1z2=01. 3. When x2=1 and x1 changes from 0 to 1, output z1z2=10. 4. Otherwise output does not change. ( Refer pg: 6.26, 6.27 in Godse)5. Define the following: i) asynchronous sequential circuits, ii) Cycles, iii) critical race, iv) non- critical race v) race vi) flow table vii) primitive flow table viii) stable state ( Refer notes)7. An asynchronous sequential circuit has two internal states and one output. The excitation and output function describing the circuit are as follows. Y1=x1x2+x1y2+x2y1 Y2=x2+x1y1y2+x1y1 Z=x2+y1 (refer 6.24 – 6.26 in Godse) UNIT IV1. Design a combinatorial circuit using ROM and PLA. The circuit accepts 3-bit number and generates an output binary number equal to square of input number. (Refer pg: S.6, S7 in Godse)2. Write a descriptive note on memories. (Refer pg: 71, 72 in Godse)3. Discuss on the concept and applications of ROM, PROM and EPROM (Refer pg: 7.2 – 7.6 in Godse)4. Discuss on the working of FPGA, PLA, PAL, PROM ( Refer section 8.2,3,4,5 in Godse)5. Give the comparison between PROM, PLA, and PAL (Refer pg: 8-31 in Godse)6. Implement the following Boolean function using PAL (Refer pg: 8.19-8.21 in Godse) W(A,B,C,D) = ∑m(0,2,6,7,8,9,12,13) x(A,B,C,D) = ∑m(0,2,6,7,8,9,12,13,14) y(A,B,C,D) = ∑m(2,3,8,9,10,12,13) z(A,B,C,D) = ∑m(1,3,4,6,9,12,14)7. Realize the functions given using a PLA with 6 inputs, 4 outputs and 10 AND gates
13 f1(A,B,C,D,E,F) = ∑m(0,1,7,8,9,10,11,15,19,23,27,31,32,33,35,39,40,41,47,63) f2(A,B,C,D,E,F) = ∑m(8,9,10,11,12,14,21,25,27,40,41,42,43,44,46,57,59) (Refer pg: 8.42 – 8.44 in Godse)8. Draw the circuit of a CMOS two input NAND gate and NOR gate and explain its operation. (Refer pg: 9.38 – 9.41 in Godse)9. Expalin about basic circuit and NOR gate of ECL with its characteristics. (Refer pg: 9.48 – 9.50 in Godse)10. Explain about TTL, its wired logic and about the totem pole output, three state output TTL with its characteristics. (Refer pg: 9.13 – 9.36 in Godse) UNIT V1. Expalin the block diagram of a typical processor unit with control signals and Arithmetic unit ( Refer pg: 10.38 – 10.40 and 10.26 – 10.29 in Godse)2. Design ALU, Shift register and Shifter with its logic Diagram. (Refer pg: 10.30 -10.38 in Godse)3. Design Simple Computer with its Block diagram. (Refer pg: 10.21 -1010.25 in Godse)4. Write an HDL program for full adder and 4-bit Comparator (Refer pg: 11.62, 11.67-11.68 in Godse)5. Write an HDL behavioural description of JK flip-flop using if-else statement based on the value of the present state. (Refer pg: S.8 in Godse)6. Write a VHDL code for a serial adder (Refer Notes)7. Write a VHDL code for a T flip-flop (Refer Notes)8. Write a VHDL code for FSM. (Refer Notes)