2017年2月のクラウドネットワークロボット研究会で発表したスライドです

1. PEAR-LAB Utsunomiya Univ.
FPGA
2017/2/18 @ 1

2. PEAR-LAB Utsunomiya Univ.
1.
2. ROS FPGA
3. cReComp (creator Reconfigurable Component)
4. cReComp
5.
6. T
2017/2/18 @ 2

3. PEAR-LAB Utsunomiya Univ.
FPGA
•
• SLAM HW
• SLAM Simultaneous Localization and Mapping
•
•
FPGA
• FPGA (Field Programmable Gate Array)
• i LSI
• c
http://www.pirobot.org/blog/0015/
2017/2/18 @ 3

4. PEAR-LAB Utsunomiya Univ.
FPGA
• FPGA
• Intel Altera [1]
• FPGA [2]
• CNN FPGA [3]
• FPGA →
• × FPGA
•
• ROS Open-RTM aist, OROCOS…
•
• FPGA
[1] Intel Completes Acquisition of Altera : https://newsroom.intel.com/news-releases/intel-completes-acquisition-of-altera/
[2] . "FPGA ." Fundamentals Review 10.2
(2016), 104-112, 2016.
[3] , , , `` FPGA ’’,
, vol. 116, no. 417, RECONF2016-69, pp. 127-132, 2017 1 .
2017/2/18 @ 4

5. PEAR-LAB Utsunomiya Univ.
•
FPGA
• FPGA
2017/2/18 @ 5

6. PEAR-LAB Utsunomiya Univ.
1.
2. ROS FPGA
3. cReComp (creator Reconfigurable Component)
4. cReComp
5.
6. T
2017/2/18 @ 6

7. PEAR-LAB Utsunomiya Univ.
• ROS RobotOperating System
• p
c
• p
• Publish/Subscribe o i
Node
Publication Subscription
Subscriber
Publisher Topic
Massage (data) :
Node Node Node
2017/2/18 @ 7

8. PEAR-LAB Utsunomiya Univ.
ROS FPGA [4]
• FPGA
HW/SW
• FPGA
• ROS FPGA p
• SoC ARM FPGA
• On chip p p HW-SW
• Linux OpenCV c
ARM( ) FPGA ( )
ROS
Node_0
Topic
ROS
Node_2
ROS
Node_1
Topic
FPGA
ROS
SoC
ROS FPGA
[4] Kazushi Yamashina,Takeshi Ohkawa,Kanemitsu Ootsu andTakashi Yokota :“Proposal of ROS-compliant FPGA Component for Low- Power Robotic Systems -
case study on image processingapplication -”, Proceedings of 2nd International Workshopon FPGAs for Software Programmers,FSP2015,pp. 62-67, 2015.
2017/2/18 @ 8

9. PEAR-LAB Utsunomiya Univ.
ROS FPGA
•
• CPU-FPGA p p
•
• c
• I/O cp c
i
HWóSW
o
HWóSW
o
i
FPGA
ROS
i
ROS node
i
HWóSW
o
HWóSW
o
i
FPGA
ROS
i
ROS node
2017/2/18 @ 9

10. PEAR-LAB Utsunomiya Univ.
1.
2. ROS FPGA
3. cReComp (creator Reconfigurable Component)
4. cReComp
5.
6. T
2017/2/18 @ 10

11. PEAR-LAB Utsunomiya Univ.
cReComp creator for Reconfigurable Component
• FPGA ROS FPGA
• FPGA
• FPGA
c cp
• FPGA p
• HW-SW
2017/2/18 @ 11

12. PEAR-LAB Utsunomiya Univ.
cReComp
•
1.
2.
•
1.
• c cp
• FPGA CPU
2. FPGA
• c
2017/2/18 @ 12

13. PEAR-LAB Utsunomiya Univ.
cReComp ×
• o
• RTL
•
• c cp
•
• c cp
• c cp p c
•
•
•
2017/2/18 @ 13

14. PEAR-LAB Utsunomiya Univ.
CPU-FPGA
• Xillybus XillybusIP Core
• Linux cp c FPGA
• CPU o c i
• o I/F
For
input
FIFO
For
output
FIFO
Xillybus
IP coreCPU
full
wr_en
data
empty
rd_en
data
empty
rd_en
data
full
wr_en
data
User
Logic
AXI
bus
2017/2/18 @ 14

15. PEAR-LAB Utsunomiya Univ.
FPGA HW SW
• publish/subscribe message o
p
• message
• I/F message
• I/F o p
16
16
32
data_in_0 [15:0]
data_in_1 [15:0]
data_out [31:0]
o
int16 input_data_in_0
int16 input_data_in_1
int32 output_data_out
msg
device
file
32bit
device
file
I/F
xillybus_ip
write
read
publish/subscribe
o i
I/F
2017/2/18 @ 15

16. PEAR-LAB Utsunomiya Univ.
FPGA HW SW
• publish/subscribe message o
p
• message
• I/F message
• I/F o p
16
16
32
data_in_0 [15:0]
data_in_1 [15:0]
data_out [31:0]
o
int16 input_data_in_0
int16 input_data_in_1
int32 output_data_out
msg
device
file
32bit
device
file
I/F
xillybus_ip
write
read
publish/subscribe
o i
I/F
2017/2/18 @ 16

17. PEAR-LAB Utsunomiya Univ.
FPGA HW SW
• publish/subscribe message o
p
• message
• I/F message
• I/F
16
16
32
data_in_0 [15:0]
data_in_1 [15:0]
data_out [31:0]
o
int16 input_data_in_0
int16 input_data_in_1
int32 output_data_out
msg
device
file
32bit
device
file
I/F
xillybus_ip
write
read
publish/subscribe
o i
I/F
2017/2/18 @ 17

18. PEAR-LAB Utsunomiya Univ.
cReComp I/F
FIFO CtrlROS APP
Verilog-HDL
FIFO
FIFO
c
cReComp
o
Output
ROS-compliant FPGA component
Python
C++
HardwareSoftware
Input
• c 2 1
• Python or scrp (specification for cReComp)
• HW-SW
• c
o HDL
c
I/F
I/F
Xillybus
FIFO Xillybus_ip
2017/2/18 @ 18

19. PEAR-LAB Utsunomiya Univ.
cReComp I/F
FIFO CtrlROS APP
Verilog-HDL
FIFO
FIFO
c
o
ROS-compliant FPGA component
Python
C++
HardwareSoftware
Input
• I/F 2 I/F
• I/F o CPU
• I/F publish/subscribe o i DF p
• Python C++
• ROS o p
o HDL
c
I/F
I/F
Xillybus
FIFO Xillybus_ip
I/FI/F
cReComp
Output
2017/2/18 @ 19

20. PEAR-LAB Utsunomiya Univ.
1.
2. ROS FPGA
3. cReComp (creator Reconfigurable Component)
4. cReComp
5.
6. T
2017/2/18 @ 20

21. PEAR-LAB Utsunomiya Univ.
cReComp
ROS FPGA
• ROS FPGA
•
i
HWóSW
o
HWóSW
o
i
FPGA
ROS
i
ROS node
ROS
2017/2/18 @ 21

22. PEAR-LAB Utsunomiya Univ.
Python
adder.vC++ Python
2017/2/18 @ 22

23. PEAR-LAB Utsunomiya Univ.
1.
2. ROS FPGA
3. cReComp (creator Reconfigurable Component)
4. cReComp
5.
6. T
2017/2/18 @ 23

24. PEAR-LAB Utsunomiya Univ.
•
• 10
• cReComp PWM
p
• cReComp
•
• FPGA 1 2
• Python 1
• ROS 3
• Linux 1 3
•
•
• 5 5 1
•
o
pwm_ctl.v
2017/2/18 @ 24

25. PEAR-LAB Utsunomiya Univ.
a) cReComp
b) ROS FPGA HW
c) ROS
d) ROS FPGA
e)
f)
a I/F
cReComp
ROS FPGA
cReComp
ROS FPGA
2017/2/18 @ 25

26. PEAR-LAB Utsunomiya Univ.
• 11
• I/F e + f 36
•
• cReComp
a) cReComp
b) ROS FPGA HW
c) ROS p
d) ROS FPGA
e)
f)
Zedboard Avnet
Programmable SoC Zynq-7020 Xilinx
OS Ubuntu14.04
ROS Indigo
0 5 10 15 20 25 30 35 40
a
b
c
d
e
f
2 26
2017/2/18 @ 26

27. PEAR-LAB Utsunomiya Univ.
• a 16 6
•
• c 55 22
• d 23 66
0 10 20 30 40 50 60 70
a
c
d
exp1 exp2 exp3 exp4 exp5 exp6 exp7 exp8 exp9 exp10
a) cReComp
c) ROS
d) ROS FPGA
→ Python ROS
2017/2/18 @ 27

28. PEAR-LAB Utsunomiya Univ.
•
• a) HW SW
d) c cp
• a dT 5 4
• FPGA
a) cReComp 4.5
b) ROS FPGA HW 4.2
c) ROS 4.1
d) ROS FPGA 4.2
e) 1.9
f) 3.2
2017/2/18 @ 28

29. PEAR-LAB Utsunomiya Univ.
1.
2. ROS FPGA
3. cReComp (creator Reconfigurable Component)
4. cReComp
5.
6.
2017/2/18 @ 29

30. PEAR-LAB Utsunomiya Univ.
•
•
FPGA FPGA
cReComp
• cReComp FPGA
ROS p
•
• Xillybus FIFO
• c cp
2017/2/18 @ 30

31. PEAR-LAB Utsunomiya Univ.
• SCOPE 152103014
cReComp is available !
https://github.com/kazuyamashi/cReComp
COCORE
https://github.com/kazuyamashi/cocore
FPGA Linux
2017/2/18 @ 31