3. COMPUTER ARCHITECTURE
Central Processing Unit (CPU)
Arithmetic Logic Unit (ALU)
Registers
General-purpose
Special-purpose
Control Unit
Input/output (I/O) Unit
2-3
6. Data Bus
Address Bus
Control Bus
1
2
3
0 4
5
6
7
9
A
B
8
E
F
C
D
CONSTITUENT COMPONENTS OF A CPU
I/O Unit
Control Unit
Program Counter (PC)
Instruction Register (IR)
Other Other
Other Other
Other Other
Registers
ALU
2-6
8. COMPUTER BUSES
Collection of wires that connect the components of
a computer to one another
Address
Data
Control
Power (usually ignored)
2-8
10. ADDING TWO VALUES STORED IN SYSTEM MEMORY
IS A FIVE-STEP PROCESS
Step 1 Get the first value to be added from memory and store
it in a register.
Step 2 Get the second value to be added from memory and
store it in another register.
Step 3 Activate the circuitry in the ALU responsible for
addition. Add the values from Steps 1 & 2 and store
the sum in a third register.
Step 4 Write the contents of register holding the result back to
some address in memory.
Step 5 Halt.
2-10
11. STORED PROGRAMS
Programs can be encoded as a sequence of bits
and stored in system memory
Obvious today
Not always so
Early computers were hard-wired
Difficult to re-program
von Neumann architecture
Memory is an array of individually-addressable cells that
store both instructions and data
Control unit interprets and executes instructions
2-11
16. MACHINE LANGUAGE
Machine instruction: a command recognized by the
CPU and encoded as a bit pattern
Machine language: the set of machine instructions
a particular CPU recognizes
Flavors:
Reduced Instruction Set Computer (RISC)
Complex Instruction Set Computer (CISC)
Instruction categories:
Data transfer
Arithmetic/logic
Control 2-16
17. EXAMPLE: DIVIDING VALUES STORED IN MEMORY
Step 1 LOAD a register with value from memory.
Step 2 LOAD another register with another value from
memory.
Step 3 If this second value equals zero, JUMP to Step 6.
Step 4 Divide the contents of the first register by the contents
of the second register putting the quotient in a third
register.
Step 5 Store the contents of the third register in memory.
Step 6 HALT.
2-17
18. AN ILLUSTRATIVE MACHINE LANGUAGE
We will be using the hypothetical machine
described in Appendix C of the book:
16 one-byte, general-purpose registers
256 one-byte memory cells
Two-byte instructions
2-18
19. ARCHITECTURE OF THE MACHINE IN
APPENDIX C
Registers
ALU
Control Unit
PC
IR
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
2-19
21. EXAMPLE: ADDING VALUES STORED IN MEMORY
Encoded
Instruction
Translation
156C LOAD register 5 with the bit pattern found at address
6C.
166D LOAD register 6 with the bit pattern found at address
6D.
5056 ADD contents of registers 5 and 6 and put the sum in
register 0.
306E STORE the contents of register 0 in address 6E.
C000 HALT.
2-21
23. THE MACHINE CYCLE
Fetch
• [PC] → IR
• Increment PC
Decode
• Interpret IR
• Fetch operand(s)
Execute
• Carry out
instruction
2-23
24. PROGRAMS VS DATA
Everything in memory is encoded in strings of 1’s
and 0’s
There is no differentiation between data and code
The control unit interprets the contents of certain
cells as instructions and other cells as data
Programs can even modify themselves during execution
2-24
28. BIT MAPS
A bit map is a way of using a value in the computer
by assigning each bit in the value some meaning
We could store the day of the week in a byte
7 6 5 4 3 2 1 0
NotUsed
Saturday
Friday
Thursday
Wednesday
Tuesday
Monday
Sunday
2-28
29. MASKS
Using a mask we can extract the status of any
given bit(s) in a string of bits
The following example tests to see if it’s Friday yet:
Bit Map 0 0 0 0 0 0 1 0
Mask (AND) 0 0 1 0 0 0 0 0
Result 0 0 0 0 0 0 0 0
2-29
30. BIT SHIFTING
Circular Shifts
Also called rotations
Logical Shifts
Left or right
Also called arithmetic shifts
2-30
35. MEMORY-MAPPED I/O
In many computers I/O devices are read from and
written just as memory is
A certain amount of address space is set aside for
communicating with memory-mapped devices
These addresses reside at the top of the addressable
memory range
232 = 4,294,967,296 or 4,096 MB
264 = 18,446,744,073,709,551,616
18 quintillion bytes
18 petabytes PB
17,592,186,044,416 MB
2-35
37. DIRECT MEMORY ACCESS (DMA)
Allows certain hardware subsystems to access
system memory independently of the CPU
Historically the CPU would have been responsible
for every bit transferred in the computer
DMA allows peripherals to transfer blocks of data to
and form memory without CPU intervention
2-37
38. HANDSHAKING
Two-way communication between the processor
and a peripheral device
Status word: a bit map used to communicate
between the system and the external device
One bit may indicate an out-of-paper error
Another signals the printer is ready for more data
The controller monitors the status and passes
important messages along to the CPU
2-38
39. PARALLEL VS SERIAL COMMUNICATION
1-bit at a time
Simple to implement
Lower bandwidth than
parallel
Able to transmit over
longer distances than
parallel
Multiple bits at a time
Higher bandwidth than
serial
Trickier to implement
Limited distance
Propagation delay
“Noisy”
Mutual inductance
Capacitance
Serial Parallel
39
41. PIPELINING
Technique for speeding up execution of a program
Each stage of the machine cycle can run in parallel
on different instructions
Bubbles
Stalls
Bad prediction
2-42
42. PIPELINING
t0 t1 t2 t3 t4 t5 t6 t7 t8
Fetch
Decode
Execute
Write
Completed
Fetch
Decode
Execute
Write
Completed
Without
Pipelining
With
Pipelining
2-43
43. PARALLEL PROCESSING AND
MULTIPROCESSOR MACHINES
Parallel processing means to execute multiple
threads or processes simultaneously
Pipelining is a step in this direction
True parallel processing require more than one
CPU
Several strategies
Multiple, independent processors sharing memory while
executing separate processes
Multiple cores operating on the same data at the same
time executing the same set of instructions
A single core operating on multiple data sets at the
same time 2-44
