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TMS320C6x ARCHITECTURE
• The TMS320C6711 is a floating-point processor
based on the
• VLIW architecture .
• Internal memory...
• On-chip peripherals include two multichannel buffered serial ports
(McBSPs),two timers, a 16-bit host port interface (HP...
3-Access level of Memory Map
1. L1 Memory
-Cache-based Architecture
-Program Cache & Data Cache
-Size : PC(4Kbyte), DC(4Kb...
Internal Memory
• Independent memory banks on the C6x allow for two
memory accesses within one instruction cycle.
• Two independent memory...
• C6x has a byte-addressable memory space.
• Internal memory is organized as separate
program and data memory spaces, with...
• With six of the eight functional units capable
of handling floating-point operations, it is
possible to perform 900 milli...
FUNCTIONAL UNITS
• The CPU consists of eight independent functional
units divided into two data paths
• Each path has a un...
Tms320C6X Architecture
Tms320C6X Architecture
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Tms320C6X Architecture

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TMS320C6X architecture - processor, peripherals, 3 level memory, various internal buses
32 bit program address bus
256 bit program data bus
2, 32 bit data address bus
2, 64bit load data bus
2,64 bit store data bus

Publicada em: Educação, Tecnologia, Negócios
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Tms320C6X Architecture

  1. 1. TMS320C6x ARCHITECTURE • The TMS320C6711 is a floating-point processor based on the • VLIW architecture . • Internal memory includes a two-level cache architecture with 4kB of level 1 program cache (L1P), 4kB of level 1 data cache (L1D), and 64kB of RAM or level 2 cache for data/program allocation (L2). • It has a direct interface to both synchronous memories and asynchronous memories •
  2. 2. • On-chip peripherals include two multichannel buffered serial ports (McBSPs),two timers, a 16-bit host port interface (HPI), and a 32-bit external memory interface (EMIF). • It requires 3.3V for I/O and 1.8V for the core (internal). • Internal buses – 32-bit program address bus – 256-bit program data bus (eight 32-bit instructions), – two 32-bit data address buses, – two 64-bit data buses – two 64-bit store data buses. • With a 32-bit address bus, the total memory space is 2^32 • = 4GB, including four external memory spaces: CE0, CE1, CE2, and CE3.
  3. 3. 3-Access level of Memory Map 1. L1 Memory -Cache-based Architecture -Program Cache & Data Cache -Size : PC(4Kbyte), DC(4Kbyte) 2. L2 Memory - Size : 64Kbyte - Program & Data 3. L3 Memory External Memory
  4. 4. Internal Memory
  5. 5. • Independent memory banks on the C6x allow for two memory accesses within one instruction cycle. • Two independent memory banks can be accessed using two independent buses. • Two loads or two stores instructions can be performed in parallel. • No conflict results if the data accessed are in different memory banks. • Separate buses for program, data, and direct memory access (DMA) allow the C6x to perform concurrent program fetches, data read and write, and DMA operations.
  6. 6. • C6x has a byte-addressable memory space. • Internal memory is organized as separate program and data memory spaces, with two 32- bit internal ports (two 64-bit ports with the C64x) to access internal memory. • With a clock of 150MHz onboard the DSK, one can ideally achieve two multiplies and accumulates per cycle, for a total of 300 million multiplies and accumulates (MACs) per second.
  7. 7. • With six of the eight functional units capable of handling floating-point operations, it is possible to perform 900 million floating-point operations per second (MFLOPS). • 1200 million instructions per second (MIPS)
  8. 8. FUNCTIONAL UNITS • The CPU consists of eight independent functional units divided into two data paths • Each path has a unit for – multiply operations (.M), – logical and arithmetic operations (.L), – branch, bit manipulation, and arithmetic operations (.S), – loading/storing and arithmetic operations (.D). • The .S and .L units are for arithmetic, logical, and branch instructions. • All data transfers make use of the .D units.

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