11th International Conference on Software Engineering & Trends (SE 2023)

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11th International Conference on Software Engineering & Trends (SE 2023) will provide an excellent international forum for sharing knowledge and results in theory, methodology and applications of Software Engineering. The goal of this conference is to bring together researchers and practitioners from academia and industry to focus on understanding Modern software engineering concepts and establishing new collaborations in these areas. Authors are solicited to contribute to the conference by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the areas of software engineering & applications. Topics of interest include, but are not limited to, the following.

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Embedded systems in the range of from a tiny microcontroller-based sensor device to mobile smart phones have vast variety of applications. However, in the literature there is no up to date system-level design of embedded hardware and software, instead academic publications are mainly focused on the improvement of specific features of embedded software/hardware and the embedded system designs for specific applications. Moreover, commercially available embedded systems are not disclosed for the view of researchers in the literature. Therefore, in this paper we first present how to design a state of art embedded system including emerged hardware and software technologies. Bedside Patient monitor devices used in intensive cares units of hospitals are also classified as embedded systems and run sophisticated software and algorithms for better diagnosis of diseases. We reveal the architecture of our, commercially available, bedside patient monitor to provide a design example of embedded systemsrelating to emerged technologies.

DESIGN OF AN EMBEDDED SYSTEM: BEDSIDE PATIENT MONITOR

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Pip-MPU is a minimalist separation kernel for constrained devices (scarce memory and power resources). In this work, we demonstrate high-assurance of Pip-MPU’s isolation property through formal verification. Pip-MPU offers user-defined on-demand multiple isolation levels guarded by the Memory Protection Unit (MPU). Pip-MPU derives from the Pip protokernel, with a full code refactoring to adapt to the constrained environment and targets equivalent security properties. The proofs verify that the memory blocks loaded in the MPU adhere to the global partition tree model. We provide the basis of the MPU formalisation and the demonstration of the formal verification strategy on two representative kernel services. The publicly released proofs have been implemented and checked using the Coq Proof Assistant for three kernel services, representing around 10000 lines of proof. To our knowledge, this is the first formal verification of an MPU based separation kernel. The verification process helped discover a critical isolation-related bug.

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15th International Conference on Wireless & Mobile Network (WiMo 2023) is dedicated to addressing the challenges in the areas of wireless & mobile networks. The Conference looks for significant contributions to the Wireless and Mobile computing in theoretical and practical aspects. The Wireless and Mobile computing domain emerges from the integration among personal computing, networks, communication technologies, cellular technology, and the Internet Technology. The modern applications are emerging in the area of mobile ad hoc networks and sensor networks. This Conference is intended to cover contributions in both the design and analysis in the context of mobile, wireless, ad-hoc, and sensor networks. The goal of this Conference is to bring together researchers and practitioners from academia and industry to focus on advanced wireless and Mobile computing concepts and establishing new collaborations in these areas. Authors are solicited to contribute to the conference by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the following areas, but are not limited to.

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ijesajournal

Scope & Topics International Conference on NLP & Signal (NLPSIG 2023) will provide an excellent international forum for sharing knowledge and results in theory, methodology and applications of Signal and Natural Language Processing (NLP). Authors are solicited to contribute to the conference by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the following areas, but are not limited to: Topics of interest include, but are not limited to, the following Chunking/Shallow Parsing Dialogue and Interactive Systems Deep learning and NLP Discourseand Pragmatics Information Extraction, Retrieval, Text Mining Interpretability and Analysis of Models for NLP Language Grounding to Vision, Robotics and Beyond Lexical Semantics Linguistic Resources Machine Learning for NLP Machine Translation NLP and Signal Processing NLP Applications Ontology Paraphrasing/Entailment/Generation Parsing/Grammatical Formalisms Phonology, Morphology POS tagging Question Answering Resources and Evaluation Semantic Processing Sentiment Analysis, Stylistic Analysis, and Argument Mining Speech and Multimodality Speech Recognition and Synthesis Spoken Language Processing Statistical and Knowledge based methods Summarization Theory and Formalism in NLP Signal Processing & NLP Computer Vision, Image Processing& NLP NLP, AI & Signal Paper Submission Authors are invited to submit papers through the conference Submission System by May 06, 2023. Submissions must be original and should not have been published previously or be under consideration for publication while being evaluated for this conference. The proceedings of the conference will be published by International Journal on Cybernetics & Informatics (IJCI) (Confirmed). Selected papers from NLPSIG 2023, after further revisions, will be published in the special issue of the following journals. International Journal on Natural Language Computing (IJNLC) International Journal of Ubiquitous Computing (IJU) International Journal of Data Mining & Knowledge Management Process (IJDKP) Signal & Image Processing : An International Journal (SIPIJ) International Journal of Ambient Systems and Applications (IJASA) International Journal of Grid Computing & Applications (IJGCA) Important Dates Submission Deadline : May 06, 2023 Authors Notification : May 25, 2023 Final Manuscript Due : June 08, 2023

Call for Papers -International Conference on NLP & Signal (NLPSIG 2023)

ijesajournal

International Conference on NLP & Signal (NLPSIG 2023) will provide an excellent international forum for sharing knowledge and results in theory, methodology and applications of Signal and Natural Language Processing (NLP). Authors are solicited to contribute to the conference by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the following areas, but are not limited to:

International Conference on NLP & Signal (NLPSIG 2023)

ijesajournal

This article is based on preliminary work on the OSI model management layers to optimized industrial wired data transfer on low data rate wireless technology. Our previous contribution deal with the development of a demonstrator providing CAN bus transfer frames (1Mbps) on a low rate wireless channel provided by Zigbee technology. In order to be compatible with all the other industrial protocols, we describe in this paper our contribution to design an innovative Wireless Device (WD) and a software tool, which will aim to determine the best architecture (hardware/software) and wireless technology to be used taking in account of the wired protocol requirements. To validate the proper functioning of this WD, we will develop an experimental platform to test different strategies provided by our software tool. We can consequently prove which is the best configuration (hardware/software) compared to the others by the inclusion (inputs) of the required parameters of the wired protocol (load, binary rate, acknowledge timeout) and the analysis of the WD architecture characteristics proposed (outputs) as the delay introduced by system, buffer size needed, CPU speed, power consumption, meeting the input requirement. It will be important to know whether gain comes from a hardware strategy with hardware accelerator e.g or a software strategy with a more perf

PERFORMING AN EXPERIMENTAL PLATFORM TO OPTIMIZE DATA MULTIPLEXING

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Today, a significant number of embedded systems focus on multimedia applications with almost insatiable demand for low-cost, high performance, and low power hardware cosumption. In this paper, we present a re-configurable and generic hardware platform for image and video processing. The proposed platform uses the benefits offered by the Field Programmable Gate Array (FPGA) to attain this goal. In this context, a prototype system is developed based on the Xilinx Virtex-5 FPGA with the integration of embedded processors, embedded memory, DDR, interface technologies, Digital Clock Managers (DCM) and MPMC. The MPMC is an essential component for design performance tuning and real time video processing. We demonstrate the importance role of this interface in multi video applications. In fact, to successful the deployment of DRAM it is mandatory to use a flexible and scalable interface. Our system introduces diverse modules, such as cut video detection, video zoom-in and out. This provides the utility of using this architecture as a universal video processing platform according to different application requirements. This platform facilitates the development of video and image processing applications.

GENERIC SOPC PLATFORM FOR VIDEO INTERACTIVE SYSTEM WITH MPMC CONTROLLER

ijesajournal

This paper presents an inverting buck-boost DCDC converter design. A negative supply voltage is needed in a variety of applications, but only a few DCDC converters are available on the market. OLED, a new display type especially suited for small digital camera or mobile phone displays. Design challenges that came up when negative voltages have to be handled on chip will be discussed, such as continuous/discontinuous mode transition problems, negative voltage feedback and negative over-voltage protection. Both devices operate in a fixed frequency PWM mode or alternatively in PFM mode. The single inductor topology is called inverting buck-boost converter or simply inverter. The proposed converter has been implemented with a TSMC 0.13-um 2P4M CMOS process, and the chip area is 325 x 300 um2.

INVERTING BUCK-BOOST DCDC CONVERTER DESIGN CHALLENGES

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High Speed computing meets ever increasing real-time computational demands through the leveraging of flexibility and parallelism. The flexibility is achieved when computing platform designed with heterogeneous resources to support multifarious tasks of an application where as task scheduling brings parallel processing. The efficient task scheduling is critical to obtain optimized performance in heterogeneous computing Systems (HCS). In this paper, we brought a review of various application scheduling models which provide parallelism for homogeneous and heterogeneous computing systems. In this paper, we made a review of various scheduling methodologies targeted to high speed computing systems and also prepared summary chart. The comparative study of scheduling methodologies for high speed computing systems has been carried out based on the attributes of platform & application as well. The attributes are execution time, nature of task, task handling capability, type of host & computing platform. Finally a summary chart has been prepared and it demonstrates that the need of developing scheduling methodologies for Heterogeneous Reconfigurable Computing Systems (HRCS) which is an emerging high speed computing platform for real time applications.

A Case Study: Task Scheduling Methodologies for High Speed Computing Systems

ijesajournal

Modern embedded systems are being modeled as Heterogeneous Reconfigurable Computing Systems (HRCS) where Reconfigurable Hardware i.e. Field Programmable Gate Array (FPGA) and soft core processors acts as computing elements. So, an efficient task distribution methodology is essential for obtaining high performance in modern embedded systems. In this paper, we present a novel methodology for task distribution called Minimum Laxity First (MLF) algorithm that takes the advantage of runtime reconfiguration of FPGA in order to effectively utilize the available resources. The MLF algorithm is a list based dynamic scheduling algorithm that uses attributes of tasks as well computing resources as cost function to distribute the tasks of an application to HRCS. In this paper, an on chip HRCS computing platform is configured on Virtex 5 FPGA using Xilinx EDK. The real time applications JPEG, OFDM transmitters are represented as task graph and then the task are distributed, statically as well dynamically, to the platform HRCS in order to evaluate the performance of the designed task distribution model. Finally, the performance of MLF algorithm is compared with existing static scheduling algorithms. The comparison shows that the MLF algorithm outperforms in terms of efficient utilization of resources on chip and also speedup an application execution.

A NOVEL METHODOLOGY FOR TASK DISTRIBUTION IN HETEROGENEOUS RECONFIGURABLE COM...

ijesajournal

Payment industry is largely aligned in their desire to create embedded payment systems ready for the modern digital age. The trend to embed payments into a software platform is often regarded as first step towards a broader trend of embedded finance based on digital representation of fiat currencies. Since it became clear to our research team that there are no technologies and protocols that are protected against attacks of quantum computing, and that enable automatic embedded payments, online or offline with no fear of counterfeit, P2P or device-to-device to be made in real time without intermediaries, in any denomination, even continuous payments per time or service, while preserving the privacy of all parties, without enabling illicit activities, we decided to utilize the Generic Innovation Engine [1] that is based on the Artificial Intelligence Assistance Innovation acceleration methodologies and tools in order to boost the progress of innovation of the necessary solutions. These methodologies accelerate innovation across the board. It proposes a framework for natural and artificial intelligence collaboration in pursuit of an innovative (R&D) objective The outcome of deploying these Artificial Innovation Assistant (AIA) methodologies was tens of patents that yield solutions, that a few of them are described in this paper. We argue that a promising avenue for automated embedded payment systems to fulfil people’s desire for privacy when conducting payments, and national security agencies demand for quantum-safe security, could be based on DeFi and digital currencies platforms that does not suffer from flaws of DLT-based solutions, while introducing real advantages, in all aspects, including being quantum-resilient, enabling users to decide with whom, if at all, to share information, identity, transactions details, etc., all without trade-offs, complying with AML measures, and accommodating the potential for high transaction volumes. It is not legacy bank accounts, and it is not peer-dependent, nor a self-organizing network.

AUTOMATED EMBEDDED PAYMENT SYSTEMS

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A NOVEL METHODOLOGY FOR TASK DISTRIBUTION IN HETEROGENEOUS RECONFIGURABLE COM...

ijesajournal

2 nd International Conference on Computing and Information Technology Trends (CCITT 2023) will provide an excellent international forum for sharing knowledge and results in theory, methodology and applications of Computing and Information Technology Trends. The Conference looks for significant contributions to all major fields of the Computer Science, Compute Engineering, Information Technology and Trends in theoretical and practical aspects.

2 nd International Conference on Computing and Information Technology

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A NOVEL METHODOLOGY FOR TASK DISTRIBUTION IN HETEROGENEOUS RECONFIGURABLE COM...

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This paper presents the research work on multicore microcontrollers using parallel, and time critical programming for the embedded systems. Due to the high complexity and limitations, it is very hard to work on the application development phase on such architectures. The experimental results mentioned in the paper are based on xCORE multicore microcontroller form XMOS® . The paper also imitates multi-tasking and parallel programming for the same platform. The tasks assigned to multiple cores are executed simultaneously, which saves the time and energy. The relative study for multicore processor and multicore controller concludes that micro architecture based controller having multiple cores illustrates better performance in time critical multi-tasking environment. The research work mentioned here not only illustrates the functionality of multicore microcontroller, but also express the novel technique of programming, profiling and optimization on such platforms in real time environments.

TIME CRITICAL MULTITASKING FOR MULTICORE MICROCONTROLLER USING XMOS® KIT

ijesajournal

4 th International Conference on Signal Processing and Machine Learning (SIGML 2023) will provide an excellent international forum for sharing knowledge and results in theory, methodology and applications of on Signal Processing and Machine Learning. The aim of the conference is to provide a platform to the researchers and practitioners from both academia as well as industry to meet and share cutting-edge development in the field.

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11th International Conference on Software Engineering & Trends (SE 2023)

1. 11th International Conference on Software Engineering & Trends (SE 2023) May 27 ~ 28, 2023, Vancouver, Canada https://acsit2023.org/se/index Scope 11th International Conference on Software Engineering & Trends (SE 2023) will provide an excellent international forum for sharing knowledge and results in theory, methodology and applications of Software Engineering. The goal of this conference is to bring together researchers and practitioners from academia and industry to focus on understanding Modern software engineering concepts and establishing new collaborations in these areas. Authors are solicited to contribute to the conference by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the areas of software engineering & applications. Topics of interest include, but are not limited to, the following. Topics of interest include, but are not limited to, the following  The Software Process  Software Engineering Practice  Web Engineering  Quality Management  Managing Software Projects  Advanced Topics in Software Engineering  Multimedia and Visual Software Engineering  Software Maintenance and Testing  Languages and Formal Methods  Web-based Education Systems and Learning Applications  Software Engineering Decision Making  Knowledge-based Systems and Formal Methods  Search Engines and Information Retrieval Paper Submission Authors are invited to submit papers through the conference Submission System by April 01, 2023. Submissions must be original and should not have been published previously or be under consideration for publication while being evaluated for this conference. The proceedings of the conference will be published by Computer Science Conference Proceedings in Computer Science & Information Technology (CS & IT) series (Confirmed). Selected papers from SE 2023, after further revisions, will be published in the special issue of the following journals.

2.  The International Journal of Software Engineering & Applications (IJSEA) -ERA indexed  International Journal of Computer Science, Engineering and Applications (IJCSEA) Important Dates  Submission Deadline : April 01, 2023  Authors Notification : April 29, 2023  Final Manuscript Due : May 06, 2023 Contact Us Here's where you can reach us : se@acsit2023.org (or) wseconf@yahoo.com

11th International Conference on Software Engineering & Trends (SE 2023)

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