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S5L2010
DPF PROCESSOR

S5L2010D S5L2010X01-X080
S5L2010A S5L2010X01-X081
S5L2010L S5L2010X02-X080
DPF PROCESSOR

USER'S MANUAL
Revision 1.0

Email:Tech@fosvos.com
HotTel:+86-21-58998693
S5L2010D S5L2010X01-X080
S5L2010A S5L2010X01-X081
S5L2010L S5L2010X02-X080
S5L2010

PRODUCT OVERVIEW

PRODUCT OVERVIEW
INTRODUCTION
The S5L2010 DPF SOC is designed to provide a cost-effective, low power and high performance Digital Photo
Frame. To reduce total system cost, the S5L2010 integrates the following functions: an advanced Audio/Video
decoder, a control CPU with 4KB/4KB instruction/data separated caches. Also S5L2010 supports various I/F’s,
USB2.0 OTG, TCON, ATA, IIC, IIS, IR, SIO, SPDIF OUT, general purpose I/O Ports, RTC, Jog-shuttle, 2-channel
UART with handshake, DVB-T I/F, 10-bit ADC for Touch-screen, 3-channel 10-bits Video DAC, 5-channel Timer
with PWM, 2-channel audio PWM out and 3-PLLs for clock generation.
The S5L2010 is fabricated in a standard 65nm CMOS technology. Its low power and static design is suitable for
power-sensitive applications.
The S5L2010 is built around the ARM9 CPU core: The ARM9 cached processor provides a complete optimal
performance CPU subsystem, including ARM946E-S RISC integer CPU, 4KB instruction/data separated caches,
with an AMBA bus interface. The ARM946E-S core executes both the 32-bit ARM and 16-bit Thumb instruction
sets, allowing the user to trade off between high performance and high code density. It is binary compatible with
ARM9TDMI, ARM10TDMI, and StrongARM processors, and is supported by a wide range of tools, operating
systems, and application software.

S5L2010D (For Digital TFT, 128pin) S5L2010X01-X080
S5L2010A (For Analogur panel, 128pin)

S5L2010X01-X081

S5L2010L (For digital TFT, 128pin, Photo only) S5L2010X02-X080

DPF PROCESSOR
Email:Tech@fosvos.com

S5L2010F (For both Digital and analogue panel, 160pin)

HotTel:+86-21-58998693

Email:Tech@fosvos.com
HotTel:+86-21-58998693

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S5L2010L S5L2010X02-X080
PRODUCT OVERVIEW

S5L2010

ARCHITECTURE
•

176MHz ARM9 (ARM946E-S, 4KB/4KB separated cache)

•

MPEG Video stream decoder : MPEG1, MPEG2(MP@ML ), MPEG4-ASP

•

Audio stream decoder (Audio DSP: CalmMAC24)

•

Format conversion, Scaling, NTSC/PAL encoder

•

Graphic processor (Multiple windows, BitBLT)

•

16-bit Unified Memory Architecture for SDR

•

On-chip clock generator with PLL

•

Core peripherals (UART, I2S, I2C, SPDIF, IR, SPI, GPIO, USB2.0 OTG etc.)

•

Memory card interfaces (MstickPro, SDC, MMC, NAND, xD, CF) 
VIDEO
Decoding Standard

MPEG-1 (ISO/IEC 11172-2), MPEG-2 (ISO/IEC 13818-2), MPEG4-ASP, M-JPEG

Source Resolutions

Decoding : Up to 960x600, Display : Up to 1024x768

Video File Format

MPEG1, MPEG4 and AVI

Graphic Processor

Multi Windows / colour modes, mixing, cursor, scaling, BitBLT

Video Post Processing

Contrast, Brightness, Hue, Sharpness Enhancement

AUDIO
Decoding Standard

MPEG-1 and MPEG-2, Layer1, 2, 3(MP3), WMA, AAC, and OGG

Input/Output Channel

2-ch PWM Audio output, SPDIF output, 3-channel I2S Output, 1-ch I2S Input

JPEG
Decoding Standard

Decoded ITU-T.81 (ISO/IEC 10918-1) compliant process

Deciding size

65536x65536 ( tested 16384x16384 )

Decoding speed

Max 57Mpixel/sec

Image decoding : others

BMP, GIF, TIFF, PNG

LCD I/F
LCD I/F

Analog/Digital LCD I/F, CPU I/F

TCON I/F

Analog/Digital DDI I/F

SYSTEM
Peripheral Interface
Memory Card Interface

UART, IR, I2C, I2S, SPI, SPDIF, USB2.0OTG, DVB-T Channel I/F
10-bit ADC(for Touch Screen), RTC
MstickPro, SDC, MMC, NAND, xD, CF, MicroDrive

Memory Interface

SDRAM I/F(16-bit Data Bus), Serial Flash I/F(1bit/2bit), EDO DRAM I/F(4bit/8bit)

PHYSICAL
Operating Voltage

3.3V I/O, 1.2V core

Clock Frequencies

Input Frequency = 24MHz, ARM : up to 176MHz, SDRAM : up to 132MHz

Packaging

160-LQFP-2424, 128-eTQFP-1414

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S5L2010

PRODUCT OVERVIEW

BLOCK DIAGRAM
SDRAM

UMA SDRAM Controller
CCIR656
Interface

USB2.0
OTG

SD/MMC

Boot ROM

BUS Interface

Memory
Stick

32-bit bus

CF/ATAPI

ARM946E-S

4KB
I-cache

SDOUT
( TV )

Mixer

(processor core)
4KB

Video
Processor
( Scaling )

32-bit bus

BUS Interface

2D Graphic
Engine(GA)

D-cache

LCDOUT

Video
3-DAC

LCD
I/F

H/W JPEG
CalmADM
( Audio DSP )
8KB
I-cache

MPEG
Video
Decoder

12KB

Audio
Interface

D-cache

IIS x 3

NAND I/F

IIS In

32-bit

NAND
Bus
Bridge
RTC

SPDIF O
2-ch
Audio

PWM

TS Interface
Channel chip

GPIO
User I/F

LED Backlight

UART
RS-232C

16 bit Timer

IR
Remocon

WDT

IIC

Ext M I/F
Flash ROM

EEPROM

PLLs
OSC

SPI

JTAG
Debugger

32-bit

Figure 1-1. S5L2010 Block Diagram

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PRODUCT OVERVIEW

S5L2010

COMPARISON TABLE
Feature

S5L2010F

S5L2010D

S5L2010A

S5L5025(DVD)

Process

65n

65n

65n

65n

Core

ARM9

ARM9

ARM9

ARM7

Core Speed

176MHz

176MHz

176MHz

132MHz

OS

iRTOS

iRTOS

iRTOS

iRTOS

Video Codec

MPEG1/2/4

MPEG1/2/4

MPEG1/2/4

MPEG1/2/4

LCD Interface

Analog/Digital

Digital(RGB 18-bit)

Analog

X

TCON Include

O

O

O

X

Decoding width (JPEG)

65536 x 65536

65536 x 65536

65536 x 65536

4096 x 4096

Decoding Speed (JPEG)

57Mpixel/sec

57Mpixel/sec

57Mpixel/sec

1.5Mpixel/sec

Display Performance

1024 x 768

1024 x 768

1024 x 768

800 x 576

Display Effect

Various

Various

Various

Simple

NAND Booting

SLC/MLC

SLC/MLC

SLC/MLC

X

SD Card Booting

O

O

O

X

Memory Card I/F

CF/SD/MMC/MS/xD

CF/SD/MMC/MS/xD

CF/SD/MMC/MS/xD

SD, MMC, MS

Video DAC( TV Output)

3

0

3

4

Audio Channel ( PWM)

2

2

2

2

IIS Output Channel

6

6

6

X

IIS Input Channel

2

2

2

X

TS Interface

O

O

O

X

RTC

O

O

O

X

ADC

12-bit 7-ch

12-bit 4-ch

12-bit 4-ch

14-bit 1-ch

USB

USB2.0 OTG

USB2.0 OTG

USB2.0 OTG

USB1.1 Host

LVD RESET

O

O

O

O

Flash memory I/F

Serial

Serial

Serial

Serial

PAD Power

3.3V

3.3V

3.3V

3.3V

Core Power

1.2V

1.2V

1.2V

1.2V

Internal BUS Clock
(ARM, ADM, Bus)

132MHz

132MHz

132MHz

132MHz

SDRAM Clock (Max)

132MHz

132MHz

132MHz

132MHz

Minimum SDRAM

16Mbit

16Mbit

16Mbit

16Mbit

Package

160-LQFP

128-eTQFP

128-eTQFP

128-QFP

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S5L2010

PRODUCT OVERVIEW

FEATURES
RISC Processor Architecture

MPEG Video Decoder

•

ARM946E-S based core processor

•

•

Fully 16/32-bit RISC architecture.

•

4KB/4KB Instruction and Data separated cache

•

Up to 176 MHz operating frequency

•
•

Cache Memory
•

64 way set-associative cache with I-cache(4KB)
and D-cache(4KB)

•

8-word per line with one valid bit and two dirty bits
per line

•

Pseudo random or round robin replacement
algorithm

•

Write through or write back cache operation to
update the main memory

•

•
•

The write buffer can hold 8 words of data and four
address

Decodes MPEG1, MPEG2 (MP@ML) and MPEG4
ASP video stream
Error detection and autonomous error
concealment
Provides a programmable core for robust
decoding of various MPEG4 stream
Decodes images having max. width of 960
Decodes MPEG1, MPEG2 video stream
(MP@ML)

Audio Stream Decoder
•
•

Decodes MPEG1, MPEG2, OGG, AAC and WMA.
Supports down mix

•

CalmMAC24 for audio signal processing
– 24-bit high performance fixed-point DSP
co-processor, 24x24 MAC operation in 1 cycle
– 2 multiplier accumulator registers,
4 general accumulator registers,
and 8 pointer registers

Memory Controller
•

Supports 1/2-bit serial flash interface.

LCD I/F

•

Supports 4/8-bit EDO-DRAM interface

•

•

Supports 16-bit data bus width for SDR interface

Horizontal max. size : 1024 ,
Vertical max. size : 768

•

SDRAM usage.
– 16Mbit SDRAM x1 ( 2-bank).
– 16Mbit SDRAM x2 ( 4-bank).
– 64/128Mbit SDRAM x1 (4-bank)

•

•

Fully Programmable access cycles for all memory
banks.

Supported MCU Interface
- 6800 MCU Interface with 18/16/8 bit parallel
interface.
- 8080 MCU Interface with 18/16/8 bit parallel
interface.
Supported LCD Interface
- Analog LCD Interface.
- Digital LCD Interface with RGB 18-bit.
- Digital LCD Interface with 8bit RGB.
Supported DDI Interface
- Analog Source DDI + Gate DDI
- Digital Source DDI (Only TTL) + Gate DDI

•

•

JPEG Decoder
•

Decoded ITU-T.81 (ISO/IEC 10918-1) compliant
baseline process.

•

Decode up to maximum 65535x65535 pixel size

•

Operation Clock Frequency : 132 MHz

•

Support variable JPEG image chroma format

•

Fine zoom operation with small memory (under
1MB)

12-bit ADC & Touch Screen I/F
•

Resolution: 12-bit

•

Maximum conversion rate: 1MSPS

•

Power supply: 3.3V (Typ.), 1.2V (Typ.)

•

Touch screen function (4-wire resistive touch).

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PRODUCT OVERVIEW

S5L2010

FEATURES (CONTINUED)
Video Processor (VP)

Watchdog Timer

•
•
•

•

•

•

Source resolution: Max 1024x768
Output Resolution: Max 1024x768
Aspect ratio conversion
Letterbox / Pan & Scan
De-interlacing
– Weave: For film source
–IPC: For interlaced video
Slide show : wipe diagonal +, wipe diagonal –,
wipe horizontal, wipe vertical
fade in/out, dissolve
Zoom In/Out: 16x – 1/4 Display format

•

•
•
•

3 graphic layers & 2 video layers : YCbCr format
Graphic Layer1 : 1/2/4/8-bpp (sub OSD )
Graphic Layer2 : 4/8/16/32-bpp ( main OSD )
Graphic Layer3 : 4-bpp ( sub-picture , cursor )
Video Layer1-2 : supports image effects
Supports Layer Blending
– Arbitrary priority control of graphic and video
layer
– 256 level alpha blending (graphic to video
layer, pixel to video layer)
Supports display maximum size 1024x768
Support two 256x32bit palette for graphic layer
and one 16x16bit palette for cursor layer
Supports image effects
– sliding, corner sliding, translation, rollup, rolling,
bars, snail, stairs, square, grid, fading, cross
comb, shutter

•

•

16-bit Timer 1, 2
– Interval, free run, one shot and capture mode
– Programmable duty cycle,frequency and
polarity.

•

16-bit Timer 3, 4
– lnterval mode and free run mode
– Supports external clock source.
High speed PWM1, PWM2 and PWM3
– Interval, free run, one shot and capture mode
– PWM function for LED backlight.

•

32-bit Timer : free run mode

Interrupt Controller
•

•
•
•

Various Interrupt sources
(Watch dog timer, 7 Timers, UART, 8 External
interrupts, I2C, I2S, SPI, IR, SPDIFOUT, Mstick,
SDCI etc.)
Edge detect mode on external interrupt source.
Programmable polarity of rising and falling.
Supports FIQ (Fast Interrupt request) for very
urgent interrupt request.

SPDIF Interface
Integrated IEC60958 encoder (SPDIF output)
2x8 bits Shift register for transmit.

•

3CH 10-bit Video DACs(Analog output)
– YPbPr, RGB, CVBS, YC output.
CCIR-656 compatible digital output

•
•

NTSC/PAL Encoder & Video Output
•

• Interrupt request or system reset at time-out.
.
Timers and PWM

•

•
•
•
Graphic Accelerator (GA) & Mixer
•

16-bit Watchdog Timer.

DMA-based or interrupt-based operation.

I2S Audio In/Out (3ch output, 1ch input)
•

3-channel I2S-bus for audio interface with DMAbased operation (6 digital channel)

RTC (Real Time Clock)

•

1-channel I2S input for Mic input

•

Full clock features: msec, sec, min, hour, day,
week, month, year

•

Serial, 8/16/24bit per channel data transfers

•

•

Up to 24-bit sample size, up to 192KHz sample

32.768 KHz operation

•

Alarm interrupt ( no wake function )

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S5L2010

PRODUCT OVERVIEW

FEATURES (Continued)
IR Input

USB2.0 OTG

•

Supports consumer electronic IR protocol

•

Transmit and receive the 8 bit data in the simple
manner

Channel I/F

USB 2.0 OTG supporting high speed (480Mbps,
on-chip transceiver).

SPI
•
•

SPI protocol (ver 2.11) compatible

• Support TS interface in DVB-H/DVB-T/ISDB-T/
T-DMB/DAB mode
•

I2C Interface
•

1-channel Multi-Master I2C-Bus.

•

Serial, 8-bit oriented and bi-directional data
transfers can be made at up to 100 Kbit/s
(standard mode) or up to 400 Kbit/s (fast mode)

I/F Signal (TS_CLK, TS_DATA, TS_VALID,
TS_SYNC, TS_ERROR )

Clock & Power Manager

•

UART with DMA-based or interrupt-based
operation

•

Supports H/W handshaking during
transmit/receive

•

Programmable baud rate

•

Loop back mode for testing

•

Internal 16-byte Tx FIFO and 16-byte Rx FIFO

•

On-chip PLLs
Clock can be fed selectively to each function block
under software control

•

Power mode : Normal, Stop mode.
Normal mode: Normal operating mode.
Stop mode : All clocks are stopped.

Supports 5-, 6-, 7-, or 8-bit serial data
transmit/receive

•

Low power consumption

•

UART

•

Oscillator
•

Single 24MHz crystal clock input.

•

Oscillation Sources & PLL

Operating Voltage
•

Memory Card Interface (All-in-1)

Core: 1.2V

•

I/O: 3.3V

•

Memory Stick (Standard ver1.4, Pro ver1.0)

•

SD ver2.0 / MMC ver 4.1

•

CF ver4.1

Operating Temperature

•

xD ver1.2 / Smart Media ver2003

•

0°C – 70 °C

NAND Flash Interface

Operating Frequency

•

NAND Flash Interface with x8 data bus

•

•

Supports SLC/MMC NAND (up to 8-bit ECC )

Up to 176 MHz

Package
•

NAND Flash Boot Loader
•
•

System can be booted from NAND when system
initialization begins
Supports both SLC and MLC NAND Flash
memory

S5L2010F : 160-LQFP-2424
S5L2010A : 128-eTQFP-1414
S5L2010D : 128-eTQFP-1414

.
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PRODUCT OVERVIEW

S5L2010

S5L2010 BASED DPF SYSTEM DIAGRAM

◆ S5L2010F(160-LQFP)
◆ S5L2010D
(128-eTQFP)

◆ S5L2010A
(128-eTQFP)

USB Slave

SD/MMC, MS,
CF, xD/SM

Memory
Controller

USB 2.0 OTG

USB Host

IR

ARM946E-S
ARM946E176MHz

Remote Con

Audio DSP
NAND Flash

UART

2D Graphic Engine
MIU/Arbiter

SDRAM/EDO

OSD/Video Mixer
OSD/Video

SDIO

Video Processor
32.768KHz

RTC

Audio PWM

H/W JPEG
MPEG Video
Decoder

IIC I/F
System Power

PMIC
Main Charger

5V
DC

USB Charger

5V
USB

Digital or Analog
LCD

CPU I/F, LCD I/F,
DDI I/F

PWM

DVB-T

Back Light
Channel
LCD

Li-Ion

Figure 1-2. System Diagram

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Keypad

12 bit ADC

TV out

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Audio
AMP

Touch Screen
S5L2010D S5L2010X01-X080
S5L2010A S5L2010X01-X081
S5L2010L S5L2010X02-X080
S5L2010

PRODUCT OVERVIEW

MEMORY ADDRESS MAP

0x3800_0000

Memorymapped
Register

0x3800_0000

Memorymapped
Register

0x3800_0000

Memorymapped
Register

0x3800_0000

0x3000_0000

0x3000_0000

0x3000_0000

0x3000_0000

0x2800_0000

0x2800_0000

0x2800_0000

Memorymapped
Register

0x2800_0000

SFLASH
0x2000_0000

SFLASH
0x2000_0000

ROM
0x1800_0000

SFLASH
0x2000_0000

ROM
0x1800_0000

SDRAM

SFLASH
0x2000_0000

ROM
0x1800_0000

SDRAM

ROM
0x1800_0000

SDRAM

SDRAM

0x1000_0000

0x1000_0000

0x1000_0000

0x1000_0000

0x0800_0000

0x0800_0000

0x0800_0000

0x0800_0000

SFLASH
0x0000_0000

SDRAM
0x0000_0000

remap = 0

ROM
0x0000_0000

remap = 1

Boot Mode[0] = 0

SDRAM
0x0000_0000

remap = 0

remap = 1

Boot Mode[0] = 1

Figure 1-3. Available Address Space of S5L2010
2010 has a memory configuration shown in figure. SDRAM, Flash, Boot ROM memory and internal registers are
mapped in the address space of 0x0000_0000 ~ 0x3FFF_FFFF.

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PRODUCT OVERVIEW

S5L2010

#

IP

Base Address

#

IP

Base Address

1

MIU

0x3820_0000

22

RTC

0x3C00_0000

2

IODMA

0x3840_0000

23

PWM

0x3C10_0000

3

BAT

0x3860_0000

24

SDCI

0x3C20_0000

4

LCD_VP

0x3880_0000

25

APU_ADM

0x3C30_0000

5

MIXER

0x38A0_0000

26

IR

0x3C40_0000

6

CSCR

0x38C0_0000

27

CLKGEN

0x3C50_0000

7

LCD_OUT

0x38E0_0000

28

MSTICK

0x3C60_0000

8

ADM

0x3900_0000

29

TIMER

0x3C70_0000

9

CF_IF

0x3920_0000

30

WDT

0x3C80_0000

10

MPVD

0x3940_0000

31

I2C

0x3C90_0000

11

TSI

0x3960_0000

32

I2S

0x3CA0_0000

12

GA

0x3980_0000

33

SPDIFOUT

0x3CB0_0000

13

SDOUT

0x39A0_0000

34

UART1

0x3CC0_0000

14

ICU

0x39C0_0000

35

SPI

0x3CD0_0000

15

ECC

0x39E0_0000

36

TIME_STAMP

0x3CE0_0000

16

CSDMA

0x3A00_0000

37

GPIO

0x3CF0_0000

17

JPEG

0x3A20_0000

38

UART2

0x3D00_0000

18

FCSCALER

0x3A40_0000

39

Reversed

0x3D10_0000

19

Reserved

0x3A60_0000

40

Reserved

0x3D20_0000

20

USB2.0(OTG)

0x3A80_0000

41

ADC_CON

0x3D30_0000

21

NAND_FLASH

0x3AA0_0000

42

Reversed

0x3D40_0000

43

APU_MPVD3

0x3D50_0000

44

APU_MPVD4

0x3D60_0000

45

JOG

0x3D70_0000

46

PG

0x3D80_0000

47

SPDIFIN

0x3D90_0000

48

USB2.0(OTG)

0x3DA0_0000

Figure 1-4. Base Address of memory mapped IP
.

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S5L2010

PRODUCT OVERVIEW

BOOT MODE
The S5L2010 DPF SOC can be booted from NAND or Flash memory when system initialization begins.
Configuration mode is selected Boot1, Boot0 pin status.
Boot 1

Boot 0

Available JTAG

0

0

Case1 : Port 3

Serial Flash Booting
Internal ROM Booting
(NAND Flash or SD Card)

0

1

Case2 : Port 0

1

0

-

1

1

Configuration Mode

-

Test

Debugging environment ( JTAG )
The S5L2010 DPF SoC has 2 JTAG ports. The ARM core processor can be controlled through its JTAG port.

PC

JTAG : nTRST

Debugger
User select
Case 1 :
JTAG or Memory I/F

Case2 :
JTAG or Serial Flash

JTAG

TDI
TDO
TMS
TCK
RTCK

JTAG

Port 3

Port 0

ARM9

Boot 0
Boot 1

Figure 1-5. JTAG Interface

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PRODUCT OVERVIEW

S5L2010

121 P0.4/SF_D1

122 P0.6/SF_CLK

123 VDDP6

124 P0.3/RXD1

125 P0.2/TXD1

126 P0.1/NRTS1

127 P0.0/NCTS1

128 P1.7/IRIN

129 P2.0/CF_DATA0

130 P2.1/CF_DATA1

131 P2.2/CF_DATA2

132 P2.3/CF_DATA3

133 P2.4/CF_DATA4

134 P2.5/CF_DATA5

135 P2.6/CF_DATA6

136 P2.7/CF_DATA7

137 P4.0/CF_RESET/SDCLK

138 VSS2

139 VDDC2

140 P3.6/CF_IOWR

141 P3.7/CF_IORD

142 P3.5/CF_IORDY

143 P4.1/NAND_CE

144 P4.2/xD_CE/SDCLK

145 P3.0/CF_A0

146 P3.1/CF_A1

147 P3.2/CF_A2

148 P3.3/CF_CE0

149 P3.4/CF_CE1

150 P4.3/NAND_R/B

151 VDDP7

152 P1.3/TS_VALID

153 P1.2/TS_DATA

154 P1.1/TS_SYNC

155 P1.0/TS_CLK

156 P1.4/TS_ERROR

157 P1.6/PWM2/MDA7

158 P1.5/PWM1/MDA6

159 P5.7/I2CCLK/MDA5

PACKAGE

160 P5.6/I2CDAT/MDA4

PIN ASSIGNMENT

MDA4

1

MDA3

2

MDA5

3

MDA2

4

MDA6

5

MDA1

6

MDA7

7

MDA0

8

MDA8

9

MDA10

10

VDDP0

11

110 AVDD331

MDA9

12

109 AVDD330

MDA11

13

108 AVSS0

BA1_NDCS1

14

BA0

15

NDCS0

16

NRAS

17

104 AVSS1

VSS0

18

103 VDD12_USB

VDDC0

19

DCLK

20

NCAS

21

NDWE

22

DQM

23

MDB8

24

MDB7

25

MDB9

26

MDB6

27

MDB10

28

MDB5

29

MDB11

30

MDB4

31

MDB12

32

MDB3

33

VDDP1

34

MDB13

35

86 VDDP4

MDB2

36

85 P10.2/INT6/A_mute

MDB14

37

84 P5.3/Audio_R

MDB1

38

MDB15

39

MDB0

40

DVB-T I/F

UART

Memory Card Interface

120 P0.7/SF_CS

Serial
Flash

119 P0.5/SF_D0
118 VDD33A_ADC

Touch
ADC

116 ADCAIN6(XM)
115 ADCAIN5(YP)
114 ADCAIN4(YM)
113 ADCAIN3
112 ADCAIN2

SDRAM I/F

111 ADCAIN1

107 DP_USB20

USB2.0
OTG

106 TXRTUNE
105 DM_USB20

S5L2010F 160LQFP-2424
Analog/Digital DDI/LCD I/F

102 VSS_USB
101 AVSSC
100 XO
99 XI
98 VDDP5
97 PLL2VDD12

PLL

96 PLL1VDD12
95 PLL0VDD12
94 RTCXTAL1

RTC

93 RTCEXTAL1
92 VDDRTC

SDRAM I/F

91 VSSRTC
90 BOOT1
89 BOOT0

Audio
2-ch

88 NRESET
87 P10.3/PWM2

83 P5.2/Audio_L

Video DAC

DDI/LCD I/F

82 P5.1/PWM2

DDI/LCD I/F

81 P5.0/PWM1

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

P4.5/I2CCLK/SPDIFO/MDB15

P4.4/I2CDAT/PCLK/MDB14

R0

R1/PWM1/NCTS1

R2/PWM2/NRTS1

R3

R4/Sample_Hold

R5

G0

G1/UP_DOWN

G2

VDDP2

G3/STVD/TxD1

G4/STHR/RxD1

G5

B0

B1/LEFT_RIGHT

DACVDD33D

DAC3_B

DAC2_G

DAC1_R

DACVDD33A1

DACIREF

DACVREF

DACCOMP

B2

B3

B4

B5

VSS1

VDDC1

P6.3/STH_L

P6.4/PCLK

P6.5/LATCH

P6.6/POL

VDDP3

P6.1/TCON_OE

P6.0/CPV

P6.2/STV_U

P6.7/VCOM

Figure 1-6. S5L2010F Pin Assignments (160-LQFP-2424)
Email:Tech@fosvos.com
1-12

117 ADCAIN7(XP)

HotTel:+86-21-58998693
S5L2010D S5L2010X01-X080
S5L2010A S5L2010X01-X081
S5L2010L S5L2010X02-X080

111 P4.0/CF_RESET/SDCLK
110 P2.7/CF_DATA7
109 P2.6/CF_DATA6
108 P2.5/CF_DATA5
107 P2.4/CF_DATA4
106 P2.3/CF_DATA3
105 P2.2/CF_DATA2
104 P2.1/CF_DATA1
103 P2.0/CF_DATA0
102 P1.7/IRIN
101 P0.2/TXD1
100 P0.3/RXD1
99 VDDP6
98 P0.6/SF_CLK
97 P0.4/SF_D1

113 P3.6/CF_IOWR
112 VDDC2

114 P3.7/CF_IORD

116 P4.1/NAND_CE
115 P3.5/CF_IORDY

118 P3.0/CF_A0
117 P4.2/xD_CE/SDCLK

120 P3.2/CF_A2
119 P3.1/CF_A1

122 P3.4/CF_CE1
121 P3.3/CF_CE0

128 MDA4/P5.6
127 MDA5/P5.7
126 MDA6/P1.5
125 MDA7/P1.6

124 VDDP7
123 P4.3/NAND_R/B

PRODUCT OVERVIEW

PACKAGE

S5L2010

MDA3

1

MDA2

2

MDA1

3

MDA0

4

MDA8

5

MDA10

6

VDDP0

7

MDA9

8

MDA11

9

BA1_NDCS1

10

BA0

11

NDCS0

12

NRAS

13

VDDC0

14

DCLK

15

NCAS

16

NDWE

17

DQM

18

MDB8

19

MDB7

20

MDB9

21

MDB6

22

75 BOOT1

MDB10

23

74 BOOT0

Memory Card Interface

UART

Serial
Flash
Touch
ADC

SDRAM I/F

96 P0.5/SF_D0
95 P0.7/SF_CS
94 VDD33A_ADC
93 ADCAIN7(XP)
92 ADCAIN6(XM)
91 ADCAIN5(YP)
90 ADCAIN4(YM)
89 AVDD331

USB2.0
OTG

S5L2010D 128-eTQFP
Digital LCD/DDI I/F

88 DP_USB20
87 TXRTUNE
86 DM_USB20
85 VDD12_USB
84 XO
83 XI
82 VDDP5

PLL
RTC

81 PLL2VDD12
80 PLL1VDD12
79 PLL0VDD12
78 RTCXTAL1
77 RTCEXTAL1
76 VDDRTC

MDB5

24

MDB11

25

MDB4

26

MDB12

27

MDB3

28

VDDP1

29

68 P5.3/Audio_R

MDB2

30

67 P5.2/Audio_L

MDB1

31

MDB0

32

Audio
2-ch

SDRAM I/F

73 NRESET
72 P10.4/PWM3
71 P10.3/PWM2
70 VDDP4
69 P10.2/INT6/A_mute

DDI/LCD Interface

66 P5.1/PWM2
65 P5.0/PWM1

B0

P6.7/VCOM
P6.2/STV_U
P6.0/CPV
P6.1/TCON_OE
VDDP3
P6.6/POL
P6.5/LATCH
P6.4/PCLK
P6.3/STH_L
VDDC1
B5
B4
B3
B2

B1

64
63
62
61
60
59
58
57
56
55
54
53
52
51

G5

50

49

G4

G3

48

G2

47

46

G1

VDDP2

44

G0

45

43

R4

R5

R2

42

40

R1

41

38

R3

37

R0
MDB13/P4.6
MDB15/P4.5
MDB14/P4.4

39

36
35
34
33

Figure 1-7. S5L2010D Pin Assignments (128-eTQFP-1414)

Email:Tech@fosvos.com
HotTel:+86-21-58998693

1-13
S5L2010D S5L2010X01-X080
S5L2010A S5L2010X01-X081
S5L2010L S5L2010X02-X080

111 P4.0/CF_RESET/SDCLK
110 P2.7/CF_DATA7
109 P2.6/CF_DATA6
108 P2.5/CF_DATA5
107 P2.4/CF_DATA4
106 P2.3/CF_DATA3
105 P2.2/CF_DATA2
104 P2.1/CF_DATA1
103 P2.0/CF_DATA0
102 P1.7/IRIN
101 P0.2/TXD1
100 P0.3/RXD1
99 VDDP6
98 P0.6/SF_CLK
97 P0.4/SF_D1

113 P3.6/CF_IOWR
112 VDDC2

114 P3.7/CF_IORD

116 P4.1/NAND_CE
115 P3.5/CF_IORDY

118 P3.0/CF_A0
117 P4.2/xD_CE/SDCLK

120 P3.2/CF_A2
119 P3.1/CF_A1

122 P3.4/CF_CE1
121 P3.3/CF_CE0

124 VDDP7
123 P4.3/NAND_R/B

S5L2010

128 MDA4/P5.6
127 MDA5/P5.7
126 MDA6/P1.5
125 MDA7/P1.6

PACKAGE

PRODUCT OVERVIEW

MDA3

1

MDA2

2

MDA1

3

MDA0

4

MDA8

5

MDA10

6

VDDP0

7

MDA9

8

89 AVDD331

MDA11

9

88 DP_USB20

BA1_NDCS1

10

BA0

11

NDCS0

12

NRAS

13

VDDC0

14

DCLK

15

NCAS

16

NDWE

17

DQM

18

MDB8

19

MDB7

20

MDB9

21

MDB6

22

MDB10

23

74 BOOT0

Serial
Flash

UART

Memory Card Interface

Touch
ADC
SDRAM I/F

96 P0.5/SF_D0
95 P0.7/SF_CS
94 VDD33A_ADC
93 ADCAIN7(XP)
92 ADCAIN6(XM)
91 ADCAIN5(YP)
90 ADCAIN4(YM)

87 TXRTUNE

USB2.0
OTG

S5L2010A 128-eTQFP
Analog LCD/DDI I/F

86 DM_USB20
85 VDD12_USB
84 XO
83 XI
82 VDDP5
81 PLL2VDD12
80 PLL1VDD12

PLL

79 PLL0VDD12
78 RTCXTAL1
77 RTCEXTAL1

RTC

76 VDDRTC
75 BOOT1

MDB5

24

73 NRESET

MDB11

25

72 P10.4/PWM3

MDB4

26

MDB12

27

MDB3

28

VDDP1

29

MDB2

30

MDB1

31

MDB0

32

71 P10.3/PWM2

SDRAM I/F

Audio
2-ch

Video DAC

DDI/LCD I/F

DACIREF

P10.1/PWM2
P10.0/PWM1
P6.7/VCOM
P6.2/STV_U
P6.0/CPV
P6.1/TCON_OE
VDDP3
P6.6/POL
P6.5/LATCH
P6.4/PCLK
P6.3/STH_L
VDDC1
P10.5
DACCOMP

DACVREF

64
63
62
61
60
59
58
57
56
55
54
53
52
51

DACVDD33A1

50

49

DAC1_R

DAC2_G

48

47

DACVDD33D

DAC3_B

P9.1/LEFT_RIGHT

46

44

P8.4/STHR/RxD1

45

43

VDDP2

P8.3/STVD/TxD1

P7.4/Sample_Hold

42

40

P7.2/PWM2/NRTS1

41

38

P8.1/UP_DOWN

37

P7.1/PWM1/NCTS1
MDB13/P4.6
MDB15/P4.5
MDB14/P4.4

39

36
35
34
33

Figure 1-8. S5L2010A Pin Assignments (128-eTQFP-1414)

Email:Tech@fosvos.com
1-14

HotTel:+86-21-58998693

70 VDDP4
69 P10.2/INT6/A_mute
68 P5.3/Audio_R
67 P5.2/Audio_L
66 P5.1/PWM2
65 P5.0/PWM1
S5L2010D S5L2010X01-X080
S5L2010A S5L2010X01-X081
S5L2010L S5L2010X02-X080
S5L2010

PRODUCT OVERVIEW

GPIO TABLE
128D핀

101
100
97
96
98
95

126
125
102
103
104
105
106
107
108
109
110
118
119
120
121
122
115
113
114
111
116
117
123
33
34
35
65
66
67
68
10
9
128
127

128D핀
62
61
63
56
57
58
59
64
36
37
38
39
40
41
42
43
44
46
47
48
49
50
51
52
53
54

69
71
72

PORT
128A핀 160핀
127
126
101
125
100
124
97
121
96
119
98
122
95
120
155
154
153
152
156
126
158
125
157
102
128
103
129
104
130
105
131
106
132
107
133
108
134
109
135
110
136
118
145
119
146
120
147
121
148
122
149
115
142
113
140
114
141
111
137
116
143
117
144
123
150
42
33
41
34
35
65
81
66
82
67
83
68
84
10
14
9
13
128
160
127
159

PORT
128A핀 160핀
60
78
59
77
61
79
54
72
55
73
56
74
57
75
62
80
43
36
44
37
45
46
38
47
48
49
39
50
51
41
53
42
54
55
56
43
57
66
67
68
69
63
64
69
85
71
87
72
52

Name
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P5.6
P5.7

Name
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
P6.7
P7.0
P7.1
P7.2
P7.3
P7.4
P7.5
P8.0
P8.1
P8.2
P8.3
P8.4
P8.5
P9.0
P9.1
P9.2
P9.3
P9.4
P9.5
P10.0
P10.1
P10.2
P10.3
P10.4
P10.5

Func0 Func1
Func2
Func3
Name Name
Name
I/O
Name
INT0 output
NCTS1
I
TxD2
input output
NRTS1
O
RxD2
input output
TXD1
O
NTRST
INT7 output
RXD1
I
TDI
input output
SF_D1
B
TDO
input output
SF_D0
B
TMS
input output
SF_CLK
O
RTCK
TCK
input output
SF_CS
O
input output
PWM1
O
TxD1
input output
PWM2
O
NCTS2
input output
PWM3
O
NRTS2
INT1 output TAOUT(PWM) O
TxD2
INT2 output TBOUT(PWM) O
TACLK
input output
PWM1
O
MDA6
input output
PWM2
O
MDA7
PWM3
O
input output
IRIN
input output CF_DATA[0]
B IO[0]
input output CF_DATA[1]
B IO[1]
input output CF_DATA[2]
B IO[2]
input output CF_DATA[3]
B IO[3]
input output CF_DATA[4]
B IO[4]
input output CF_DATA[5]
B IO[5]
input output CF_DATA[6]
B IO[6]
input output CF_DATA[7]
B IO[7]
input output CF_A0
O CLE
input output CF_A1
O ALE
input output CF_A2
O RE
input output CF_CE0
O WE
input output CF_CE1
O
input output CF_IORDY
I R/B0
input output CF_IOWR
O R/B1(xD)
input output CF_IORD
O
input output CF_RESET
O
input output
CE0
input output
CE1(xD)
input output
MDA12
O R/B0
input output
I2CDAT
B
MDB14
input output
I2CCLK
B
MDB15
INT3 output
PWM1
O
MDB13
input output
PWM1
O
INT5 output
PWM2
O
input output PWM0_L_REG O
PWM0_L
input output PWM0_R_REG O
PWM0_R
input output
BA1_nDCS1
O
input output
MDA11
O
input output
MDA4
O
I2CDAT
input output
MDA5
O
I2CCLK

Func0 Func1
Name Name
input output
input output
input output
input output
input output
input output
input output
INT4 output
input output
input output
input output
input output
input output
input output
input output
input output
input output
input output
input output
input output
input output
input output
input output
input output
input output
input output
input output
input output
INT6 output
input output
input output
input output

LCD(Digital)
Func2
Name
PWM1
DE
PWM1
PWM2
PCLK
H-Sync
V-Sync
PWM2
R0
R1
R2
R3
R4
R5
G0
G1
G2
G3
G4
G5
B0
B1
B2
B3
B4
B5
PWM1
PWM2
TxD2
RxD2

I/O
O
I
I
I
O
I
O
I
O
I
O
O
I
O
O
I
B
B
B
B
B
B
B
B
O
O
O
O

Func4
Name
TAOUT(PWM)
TBOUT(PWM)
PWM1
IRIN
PWM1
PWM2
CKO

Func5
Name
EMG1
EMG2
EMG3
PWM3
NCTS1
NRTS1
TACLK

I/O
O
O
O
I
O
O
O

NCTS2
NRTS2
RxD2
TxD2

I
O
I
O

PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
DIO[0]
DIO[1]
DIO[2]
DIO[3]

I/O
O
O
O
O

Func7
Name
TACAP
TBCAP
IIS_IN
IIS_DAT0
IISLRCK
IISBCLK
IISMCLK

I/O
I
I
I
O
O
O
O

nPWM1
nPWM2
nPWM3
TxD2
RxD2

O
O
O
O
I

I
I
I
I
I

SPICLK
MOSI
MISO

B
B
B

SPDIFO
CKO

O
O

RTCOSC

O

PWM1

O

NTRSTADM
TDOADM
TDIADM
TMSADM
TCKADM
NTRST
TDI
TDO
TMS
TCK

O
O CLK0
I
B
JOG1
B
JOG2
B PCLK

B BS
O

nRST_LCD
Ext_LCD_Int
Ext_LCD_Int

O
I
I

PG0
PG1
PG2
PG3
PCLK
SPDIFO

EMG1
EMG2

I
I

I
I

TxD2
RxD2

O

O
O
O
O
O
O

O
I

CF_DATA[8]
CF_DATA[9]
CF_DATA[10]
CF_DATA[11]
CF_DATA[12]
CF_DATA[13]
CF_DATA[14]

B
B
B
B
B
B
B

CF_DATA[15]

O

I
I
O

NRTS1

B

O

O SCLK

I/O

O

O

I
I
CMD0
CLK0

Func8
Name

I
O
I
I
I
I
I
O
I
I

PWM2

TS_CLK
TS_SYNC
TS_DATA
TS_VALID
TS_ERROR

O
O
O
O
O
O
O
O
B
B
B
B

Func6
Name
STV_D
UD
STH_R
LR

RTCK

TS_CLK
TS_SYNC
TS_DATA
TS_VALID
TS_ERROR
SPICLK
MOSI
MISO
DAT[0]
DAT[1]
DAT[2]
DAT[3]
DAT[4]
DAT[5]
DAT[6]
DAT[7]

I
I
I
I
I
B
B
B
B
B
B
B
B
B
B
B

I/O
I
I
I
O
I
O
I

O
O

B
B

JOG1
JOG2

LCD(Analog)
TCON(Digital)
Func3
Func4
I/O
Name
I/O
Name
O
I CPV
TS_CLK
O
I OE
TS_SYNC
O
I STV_U
TS_DATA
O
I STH_L
TS_VALID
O
I PCLK
TS_ERROR
O
O LATCH
H-Sync
O
O POL
V-Sync
O
SPDIFO
O VCOM
O
R0
O
PWM1
O R1
O
PWM2
O R2
O
X
R3
O
SPDIFO
O R4
O
X
R5
O
G0
O
SPDIF_IN
I G1
O
X
G2
O
TxD1
O G3
O
RxD1
I G4
O
X
G5
O
JOG1
I B0
O
JOG2
I B1
O
X
B2
O
X
B3
O
X
B4
O
X
B5
O
O
O
JOG1
I
I2CDAT
I
JOG2
I
I2CCLK

I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O

TCON(Analog)
CPU IF
Func5
Func6
Name
I/O
Name
O CPU_CS
CPV
O
OE(OEV)
O CPU_RS
STV_U
O CPU_RD
STH_L
O
R_CLK
O
G_CLK
O CPU_V-Sync
B_CLK
VCOM
O WR
D1
O D2
MODE1
O D3
MODE2
X
D4
Sample&Hold
O D5
X
D6
D7
UD
O D8
X
D9
STV_D
O D10
STH_R
O D11
X
D12
D13
LR
O D14
X
D15
X
D16
X
D17
X
D18

B
B

PG1
PG0
TBCLK
SPDIFO

O
O
I
O

Auto_mute
PWM2
PWM3

I/O
O
O
O

O
O
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B

O
O
O

Func7
Name
VDAT0
VDAT1
VDAT2
VDAT3
VDAT4
VDAT5
VDAT6
VDAT7
BTCLK
NCTS1
NRTS1

Auto_mute

I
I

I/O
O
O
O
O
O
O

CF_DATA[8]
CF_DATA[9]

B
B
B

CF_DATA[11]
CF_DATA[12]
CF_DATA[13]
CF_DATA[14]

B
B
B
B

CF_INTREQ
CF_DATA[15]
CF_DMACK
CF_DMAREQ

JOG1
JOG2

Func8
Name
IISMCLK
IISBCLK
IISLRCK
IIS_DAT0
IIS_DAT1
IIS_DAT2

CF_DATA[10]

I/O
O
O
O
O
O
O
O
O
O
I
O

I
B
O
I

O

Email:Tech@fosvos.com
HotTel:+86-21-58998693

1-15
S5L2010D S5L2010X01-X080
S5L2010A S5L2010X01-X081
S5L2010L S5L2010X02-X080
PRODUCT OVERVIEW

S5L2010

PIN DESCRIPTION
Table 1-1. S5L2010F/D/A Pin Descriptions
Pin name

I/O

Description

S5L2010F
160-LQFP

S5L2010D
128-eTQPF

S5L2010A
128-eTQPF

GPIO

NRESET

B

XI

I

XO

O

BOOT1
BOOT0

I
I

System
Global reset input when LVD is disabled.
Global reset output when LVD is enabled.
(active low)
27MHz Oscillator clock input, or crystal input
Oscillator out to connected to XI, If no crystal
used, must be left NC.
Boot mode control 1
Boot mode control 0

CKO

O

PLLs Clock out for test
RTC
RTC Crystal output
RTC Crystal Input
RTC power(3.3V)
RTC ground
ARM9 Debugger
Tap controller reset (active low) for ARM
JTAG.

RTCXTAL1
RTCEXTAL1
VDDRTC
VSSRTC

O
I
P
P

NTRST

I

TDI

I

Test data input for ARM JTAG

TDO

O

Test data output for ARM JTAG

TMS

I

Tap controller Machine State control for ARM
JTAG

TCK

I

ARM JTAG Clock Input

RTCK

O

ARM debug sync clock

NTRSTADM

I

TDOADM
TDIADM

O
I

TMSADM

I

TCKADM

I

ADM Debugger
Tap controller reset (active low) for ADM
JTAG
Test data output for ADM JTAG
Test data input for ADM JTAG
Tap controller Machine State control for ADM
JTAG
ADM JTAG Clock Input

Email:Tech@fosvos.com
1-16

HotTel:+86-21-58998693

PIN

GPIO

PIN

GPIO

PIN

-

88

-

73

-

73

-

99

-

83

-

83

-

100

-

84

-

84

90
89
P0.6 122
P1.7 128
S5L2010F
94
93
92
91
S5L2010F
P0.2 125
P3.0 145
P0.3 124
P3.1 146
P0.4 121
P3.2 147
P0.5 119
P3.3 148
P0.7 120
P3.4 149
P0.6 122
P3.6 140
S5L2010F

75
74
P0.6
98
P1.7 102
S5L2010D
78
77
76
S5L2010D
P0.2 101
P3.0 118
P0.3 100
P3.1 119
P0.4
97
P3.2 120
P0.5
96
P3.3 121
P0.7
95
P3.4 122
P0.6
98
P3.6 113
S5L2010D

75
74
P0.6
98
P1.7 102
S5L2010A
78
77
76
S5L2010A
P0.2 101
P3.0 118
P0.3 100
P3.1 119
P0.4
97
P3.2 120
P0.5
96
P3.3 121
P0.7
95
P3.4 122
P0.6
98
P3.6 113
S5L2010A

P2.3

132

P2.3

106

P2.3

106

P2.4
P2.5

133
134

P2.4
P2.5

107
108

P2.4
P2.5

107
108

P2.6

135

P2.6

109

P2.6

109

P2.7

136

P2.7

110

P2.7

110

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S5L2010 datasheet

  • 1. S5L2010 DPF PROCESSOR S5L2010D S5L2010X01-X080 S5L2010A S5L2010X01-X081 S5L2010L S5L2010X02-X080 DPF PROCESSOR USER'S MANUAL Revision 1.0 Email:Tech@fosvos.com HotTel:+86-21-58998693
  • 2. S5L2010D S5L2010X01-X080 S5L2010A S5L2010X01-X081 S5L2010L S5L2010X02-X080 S5L2010 PRODUCT OVERVIEW PRODUCT OVERVIEW INTRODUCTION The S5L2010 DPF SOC is designed to provide a cost-effective, low power and high performance Digital Photo Frame. To reduce total system cost, the S5L2010 integrates the following functions: an advanced Audio/Video decoder, a control CPU with 4KB/4KB instruction/data separated caches. Also S5L2010 supports various I/F’s, USB2.0 OTG, TCON, ATA, IIC, IIS, IR, SIO, SPDIF OUT, general purpose I/O Ports, RTC, Jog-shuttle, 2-channel UART with handshake, DVB-T I/F, 10-bit ADC for Touch-screen, 3-channel 10-bits Video DAC, 5-channel Timer with PWM, 2-channel audio PWM out and 3-PLLs for clock generation. The S5L2010 is fabricated in a standard 65nm CMOS technology. Its low power and static design is suitable for power-sensitive applications. The S5L2010 is built around the ARM9 CPU core: The ARM9 cached processor provides a complete optimal performance CPU subsystem, including ARM946E-S RISC integer CPU, 4KB instruction/data separated caches, with an AMBA bus interface. The ARM946E-S core executes both the 32-bit ARM and 16-bit Thumb instruction sets, allowing the user to trade off between high performance and high code density. It is binary compatible with ARM9TDMI, ARM10TDMI, and StrongARM processors, and is supported by a wide range of tools, operating systems, and application software. S5L2010D (For Digital TFT, 128pin) S5L2010X01-X080 S5L2010A (For Analogur panel, 128pin) S5L2010X01-X081 S5L2010L (For digital TFT, 128pin, Photo only) S5L2010X02-X080 DPF PROCESSOR Email:Tech@fosvos.com S5L2010F (For both Digital and analogue panel, 160pin) HotTel:+86-21-58998693 Email:Tech@fosvos.com HotTel:+86-21-58998693 1-1
  • 3. S5L2010D S5L2010X01-X080 S5L2010A S5L2010X01-X081 S5L2010L S5L2010X02-X080 PRODUCT OVERVIEW S5L2010 ARCHITECTURE • 176MHz ARM9 (ARM946E-S, 4KB/4KB separated cache) • MPEG Video stream decoder : MPEG1, MPEG2(MP@ML ), MPEG4-ASP • Audio stream decoder (Audio DSP: CalmMAC24) • Format conversion, Scaling, NTSC/PAL encoder • Graphic processor (Multiple windows, BitBLT) • 16-bit Unified Memory Architecture for SDR • On-chip clock generator with PLL • Core peripherals (UART, I2S, I2C, SPDIF, IR, SPI, GPIO, USB2.0 OTG etc.) • Memory card interfaces (MstickPro, SDC, MMC, NAND, xD, CF)  VIDEO Decoding Standard MPEG-1 (ISO/IEC 11172-2), MPEG-2 (ISO/IEC 13818-2), MPEG4-ASP, M-JPEG Source Resolutions Decoding : Up to 960x600, Display : Up to 1024x768 Video File Format MPEG1, MPEG4 and AVI Graphic Processor Multi Windows / colour modes, mixing, cursor, scaling, BitBLT Video Post Processing Contrast, Brightness, Hue, Sharpness Enhancement AUDIO Decoding Standard MPEG-1 and MPEG-2, Layer1, 2, 3(MP3), WMA, AAC, and OGG Input/Output Channel 2-ch PWM Audio output, SPDIF output, 3-channel I2S Output, 1-ch I2S Input JPEG Decoding Standard Decoded ITU-T.81 (ISO/IEC 10918-1) compliant process Deciding size 65536x65536 ( tested 16384x16384 ) Decoding speed Max 57Mpixel/sec Image decoding : others BMP, GIF, TIFF, PNG LCD I/F LCD I/F Analog/Digital LCD I/F, CPU I/F TCON I/F Analog/Digital DDI I/F SYSTEM Peripheral Interface Memory Card Interface UART, IR, I2C, I2S, SPI, SPDIF, USB2.0OTG, DVB-T Channel I/F 10-bit ADC(for Touch Screen), RTC MstickPro, SDC, MMC, NAND, xD, CF, MicroDrive Memory Interface SDRAM I/F(16-bit Data Bus), Serial Flash I/F(1bit/2bit), EDO DRAM I/F(4bit/8bit) PHYSICAL Operating Voltage 3.3V I/O, 1.2V core Clock Frequencies Input Frequency = 24MHz, ARM : up to 176MHz, SDRAM : up to 132MHz Packaging 160-LQFP-2424, 128-eTQFP-1414 Email:Tech@fosvos.com 1-2 HotTel:+86-21-58998693
  • 4. S5L2010D S5L2010X01-X080 S5L2010A S5L2010X01-X081 S5L2010L S5L2010X02-X080 S5L2010 PRODUCT OVERVIEW BLOCK DIAGRAM SDRAM UMA SDRAM Controller CCIR656 Interface USB2.0 OTG SD/MMC Boot ROM BUS Interface Memory Stick 32-bit bus CF/ATAPI ARM946E-S 4KB I-cache SDOUT ( TV ) Mixer (processor core) 4KB Video Processor ( Scaling ) 32-bit bus BUS Interface 2D Graphic Engine(GA) D-cache LCDOUT Video 3-DAC LCD I/F H/W JPEG CalmADM ( Audio DSP ) 8KB I-cache MPEG Video Decoder 12KB Audio Interface D-cache IIS x 3 NAND I/F IIS In 32-bit NAND Bus Bridge RTC SPDIF O 2-ch Audio PWM TS Interface Channel chip GPIO User I/F LED Backlight UART RS-232C 16 bit Timer IR Remocon WDT IIC Ext M I/F Flash ROM EEPROM PLLs OSC SPI JTAG Debugger 32-bit Figure 1-1. S5L2010 Block Diagram Email:Tech@fosvos.com HotTel:+86-21-58998693 1-3
  • 5. S5L2010D S5L2010X01-X080 S5L2010A S5L2010X01-X081 S5L2010L S5L2010X02-X080 PRODUCT OVERVIEW S5L2010 COMPARISON TABLE Feature S5L2010F S5L2010D S5L2010A S5L5025(DVD) Process 65n 65n 65n 65n Core ARM9 ARM9 ARM9 ARM7 Core Speed 176MHz 176MHz 176MHz 132MHz OS iRTOS iRTOS iRTOS iRTOS Video Codec MPEG1/2/4 MPEG1/2/4 MPEG1/2/4 MPEG1/2/4 LCD Interface Analog/Digital Digital(RGB 18-bit) Analog X TCON Include O O O X Decoding width (JPEG) 65536 x 65536 65536 x 65536 65536 x 65536 4096 x 4096 Decoding Speed (JPEG) 57Mpixel/sec 57Mpixel/sec 57Mpixel/sec 1.5Mpixel/sec Display Performance 1024 x 768 1024 x 768 1024 x 768 800 x 576 Display Effect Various Various Various Simple NAND Booting SLC/MLC SLC/MLC SLC/MLC X SD Card Booting O O O X Memory Card I/F CF/SD/MMC/MS/xD CF/SD/MMC/MS/xD CF/SD/MMC/MS/xD SD, MMC, MS Video DAC( TV Output) 3 0 3 4 Audio Channel ( PWM) 2 2 2 2 IIS Output Channel 6 6 6 X IIS Input Channel 2 2 2 X TS Interface O O O X RTC O O O X ADC 12-bit 7-ch 12-bit 4-ch 12-bit 4-ch 14-bit 1-ch USB USB2.0 OTG USB2.0 OTG USB2.0 OTG USB1.1 Host LVD RESET O O O O Flash memory I/F Serial Serial Serial Serial PAD Power 3.3V 3.3V 3.3V 3.3V Core Power 1.2V 1.2V 1.2V 1.2V Internal BUS Clock (ARM, ADM, Bus) 132MHz 132MHz 132MHz 132MHz SDRAM Clock (Max) 132MHz 132MHz 132MHz 132MHz Minimum SDRAM 16Mbit 16Mbit 16Mbit 16Mbit Package 160-LQFP 128-eTQFP 128-eTQFP 128-QFP Email:Tech@fosvos.com 1-4 HotTel:+86-21-58998693
  • 6. S5L2010D S5L2010X01-X080 S5L2010A S5L2010X01-X081 S5L2010L S5L2010X02-X080 S5L2010 PRODUCT OVERVIEW FEATURES RISC Processor Architecture MPEG Video Decoder • ARM946E-S based core processor • • Fully 16/32-bit RISC architecture. • 4KB/4KB Instruction and Data separated cache • Up to 176 MHz operating frequency • • Cache Memory • 64 way set-associative cache with I-cache(4KB) and D-cache(4KB) • 8-word per line with one valid bit and two dirty bits per line • Pseudo random or round robin replacement algorithm • Write through or write back cache operation to update the main memory • • • The write buffer can hold 8 words of data and four address Decodes MPEG1, MPEG2 (MP@ML) and MPEG4 ASP video stream Error detection and autonomous error concealment Provides a programmable core for robust decoding of various MPEG4 stream Decodes images having max. width of 960 Decodes MPEG1, MPEG2 video stream (MP@ML) Audio Stream Decoder • • Decodes MPEG1, MPEG2, OGG, AAC and WMA. Supports down mix • CalmMAC24 for audio signal processing – 24-bit high performance fixed-point DSP co-processor, 24x24 MAC operation in 1 cycle – 2 multiplier accumulator registers, 4 general accumulator registers, and 8 pointer registers Memory Controller • Supports 1/2-bit serial flash interface. LCD I/F • Supports 4/8-bit EDO-DRAM interface • • Supports 16-bit data bus width for SDR interface Horizontal max. size : 1024 , Vertical max. size : 768 • SDRAM usage. – 16Mbit SDRAM x1 ( 2-bank). – 16Mbit SDRAM x2 ( 4-bank). – 64/128Mbit SDRAM x1 (4-bank) • • Fully Programmable access cycles for all memory banks. Supported MCU Interface - 6800 MCU Interface with 18/16/8 bit parallel interface. - 8080 MCU Interface with 18/16/8 bit parallel interface. Supported LCD Interface - Analog LCD Interface. - Digital LCD Interface with RGB 18-bit. - Digital LCD Interface with 8bit RGB. Supported DDI Interface - Analog Source DDI + Gate DDI - Digital Source DDI (Only TTL) + Gate DDI • • JPEG Decoder • Decoded ITU-T.81 (ISO/IEC 10918-1) compliant baseline process. • Decode up to maximum 65535x65535 pixel size • Operation Clock Frequency : 132 MHz • Support variable JPEG image chroma format • Fine zoom operation with small memory (under 1MB) 12-bit ADC & Touch Screen I/F • Resolution: 12-bit • Maximum conversion rate: 1MSPS • Power supply: 3.3V (Typ.), 1.2V (Typ.) • Touch screen function (4-wire resistive touch). Email:Tech@fosvos.com HotTel:+86-21-58998693 1-5
  • 7. S5L2010D S5L2010X01-X080 S5L2010A S5L2010X01-X081 S5L2010L S5L2010X02-X080 PRODUCT OVERVIEW S5L2010 FEATURES (CONTINUED) Video Processor (VP) Watchdog Timer • • • • • • Source resolution: Max 1024x768 Output Resolution: Max 1024x768 Aspect ratio conversion Letterbox / Pan & Scan De-interlacing – Weave: For film source –IPC: For interlaced video Slide show : wipe diagonal +, wipe diagonal –, wipe horizontal, wipe vertical fade in/out, dissolve Zoom In/Out: 16x – 1/4 Display format • • • • 3 graphic layers & 2 video layers : YCbCr format Graphic Layer1 : 1/2/4/8-bpp (sub OSD ) Graphic Layer2 : 4/8/16/32-bpp ( main OSD ) Graphic Layer3 : 4-bpp ( sub-picture , cursor ) Video Layer1-2 : supports image effects Supports Layer Blending – Arbitrary priority control of graphic and video layer – 256 level alpha blending (graphic to video layer, pixel to video layer) Supports display maximum size 1024x768 Support two 256x32bit palette for graphic layer and one 16x16bit palette for cursor layer Supports image effects – sliding, corner sliding, translation, rollup, rolling, bars, snail, stairs, square, grid, fading, cross comb, shutter • • 16-bit Timer 1, 2 – Interval, free run, one shot and capture mode – Programmable duty cycle,frequency and polarity. • 16-bit Timer 3, 4 – lnterval mode and free run mode – Supports external clock source. High speed PWM1, PWM2 and PWM3 – Interval, free run, one shot and capture mode – PWM function for LED backlight. • 32-bit Timer : free run mode Interrupt Controller • • • • Various Interrupt sources (Watch dog timer, 7 Timers, UART, 8 External interrupts, I2C, I2S, SPI, IR, SPDIFOUT, Mstick, SDCI etc.) Edge detect mode on external interrupt source. Programmable polarity of rising and falling. Supports FIQ (Fast Interrupt request) for very urgent interrupt request. SPDIF Interface Integrated IEC60958 encoder (SPDIF output) 2x8 bits Shift register for transmit. • 3CH 10-bit Video DACs(Analog output) – YPbPr, RGB, CVBS, YC output. CCIR-656 compatible digital output • • NTSC/PAL Encoder & Video Output • • Interrupt request or system reset at time-out. . Timers and PWM • • • • Graphic Accelerator (GA) & Mixer • 16-bit Watchdog Timer. DMA-based or interrupt-based operation. I2S Audio In/Out (3ch output, 1ch input) • 3-channel I2S-bus for audio interface with DMAbased operation (6 digital channel) RTC (Real Time Clock) • 1-channel I2S input for Mic input • Full clock features: msec, sec, min, hour, day, week, month, year • Serial, 8/16/24bit per channel data transfers • • Up to 24-bit sample size, up to 192KHz sample 32.768 KHz operation • Alarm interrupt ( no wake function ) Email:Tech@fosvos.com 1-6 HotTel:+86-21-58998693
  • 8. S5L2010D S5L2010X01-X080 S5L2010A S5L2010X01-X081 S5L2010L S5L2010X02-X080 S5L2010 PRODUCT OVERVIEW FEATURES (Continued) IR Input USB2.0 OTG • Supports consumer electronic IR protocol • Transmit and receive the 8 bit data in the simple manner Channel I/F USB 2.0 OTG supporting high speed (480Mbps, on-chip transceiver). SPI • • SPI protocol (ver 2.11) compatible • Support TS interface in DVB-H/DVB-T/ISDB-T/ T-DMB/DAB mode • I2C Interface • 1-channel Multi-Master I2C-Bus. • Serial, 8-bit oriented and bi-directional data transfers can be made at up to 100 Kbit/s (standard mode) or up to 400 Kbit/s (fast mode) I/F Signal (TS_CLK, TS_DATA, TS_VALID, TS_SYNC, TS_ERROR ) Clock & Power Manager • UART with DMA-based or interrupt-based operation • Supports H/W handshaking during transmit/receive • Programmable baud rate • Loop back mode for testing • Internal 16-byte Tx FIFO and 16-byte Rx FIFO • On-chip PLLs Clock can be fed selectively to each function block under software control • Power mode : Normal, Stop mode. Normal mode: Normal operating mode. Stop mode : All clocks are stopped. Supports 5-, 6-, 7-, or 8-bit serial data transmit/receive • Low power consumption • UART • Oscillator • Single 24MHz crystal clock input. • Oscillation Sources & PLL Operating Voltage • Memory Card Interface (All-in-1) Core: 1.2V • I/O: 3.3V • Memory Stick (Standard ver1.4, Pro ver1.0) • SD ver2.0 / MMC ver 4.1 • CF ver4.1 Operating Temperature • xD ver1.2 / Smart Media ver2003 • 0°C – 70 °C NAND Flash Interface Operating Frequency • NAND Flash Interface with x8 data bus • • Supports SLC/MMC NAND (up to 8-bit ECC ) Up to 176 MHz Package • NAND Flash Boot Loader • • System can be booted from NAND when system initialization begins Supports both SLC and MLC NAND Flash memory S5L2010F : 160-LQFP-2424 S5L2010A : 128-eTQFP-1414 S5L2010D : 128-eTQFP-1414 . Email:Tech@fosvos.com HotTel:+86-21-58998693 1-7
  • 9. S5L2010D S5L2010X01-X080 S5L2010A S5L2010X01-X081 S5L2010L S5L2010X02-X080 PRODUCT OVERVIEW S5L2010 S5L2010 BASED DPF SYSTEM DIAGRAM ◆ S5L2010F(160-LQFP) ◆ S5L2010D (128-eTQFP) ◆ S5L2010A (128-eTQFP) USB Slave SD/MMC, MS, CF, xD/SM Memory Controller USB 2.0 OTG USB Host IR ARM946E-S ARM946E176MHz Remote Con Audio DSP NAND Flash UART 2D Graphic Engine MIU/Arbiter SDRAM/EDO OSD/Video Mixer OSD/Video SDIO Video Processor 32.768KHz RTC Audio PWM H/W JPEG MPEG Video Decoder IIC I/F System Power PMIC Main Charger 5V DC USB Charger 5V USB Digital or Analog LCD CPU I/F, LCD I/F, DDI I/F PWM DVB-T Back Light Channel LCD Li-Ion Figure 1-2. System Diagram Email:Tech@fosvos.com 1-8 Keypad 12 bit ADC TV out HotTel:+86-21-58998693 Audio AMP Touch Screen
  • 10. S5L2010D S5L2010X01-X080 S5L2010A S5L2010X01-X081 S5L2010L S5L2010X02-X080 S5L2010 PRODUCT OVERVIEW MEMORY ADDRESS MAP 0x3800_0000 Memorymapped Register 0x3800_0000 Memorymapped Register 0x3800_0000 Memorymapped Register 0x3800_0000 0x3000_0000 0x3000_0000 0x3000_0000 0x3000_0000 0x2800_0000 0x2800_0000 0x2800_0000 Memorymapped Register 0x2800_0000 SFLASH 0x2000_0000 SFLASH 0x2000_0000 ROM 0x1800_0000 SFLASH 0x2000_0000 ROM 0x1800_0000 SDRAM SFLASH 0x2000_0000 ROM 0x1800_0000 SDRAM ROM 0x1800_0000 SDRAM SDRAM 0x1000_0000 0x1000_0000 0x1000_0000 0x1000_0000 0x0800_0000 0x0800_0000 0x0800_0000 0x0800_0000 SFLASH 0x0000_0000 SDRAM 0x0000_0000 remap = 0 ROM 0x0000_0000 remap = 1 Boot Mode[0] = 0 SDRAM 0x0000_0000 remap = 0 remap = 1 Boot Mode[0] = 1 Figure 1-3. Available Address Space of S5L2010 2010 has a memory configuration shown in figure. SDRAM, Flash, Boot ROM memory and internal registers are mapped in the address space of 0x0000_0000 ~ 0x3FFF_FFFF. Email:Tech@fosvos.com HotTel:+86-21-58998693 1-9
  • 11. S5L2010D S5L2010X01-X080 S5L2010A S5L2010X01-X081 S5L2010L S5L2010X02-X080 PRODUCT OVERVIEW S5L2010 # IP Base Address # IP Base Address 1 MIU 0x3820_0000 22 RTC 0x3C00_0000 2 IODMA 0x3840_0000 23 PWM 0x3C10_0000 3 BAT 0x3860_0000 24 SDCI 0x3C20_0000 4 LCD_VP 0x3880_0000 25 APU_ADM 0x3C30_0000 5 MIXER 0x38A0_0000 26 IR 0x3C40_0000 6 CSCR 0x38C0_0000 27 CLKGEN 0x3C50_0000 7 LCD_OUT 0x38E0_0000 28 MSTICK 0x3C60_0000 8 ADM 0x3900_0000 29 TIMER 0x3C70_0000 9 CF_IF 0x3920_0000 30 WDT 0x3C80_0000 10 MPVD 0x3940_0000 31 I2C 0x3C90_0000 11 TSI 0x3960_0000 32 I2S 0x3CA0_0000 12 GA 0x3980_0000 33 SPDIFOUT 0x3CB0_0000 13 SDOUT 0x39A0_0000 34 UART1 0x3CC0_0000 14 ICU 0x39C0_0000 35 SPI 0x3CD0_0000 15 ECC 0x39E0_0000 36 TIME_STAMP 0x3CE0_0000 16 CSDMA 0x3A00_0000 37 GPIO 0x3CF0_0000 17 JPEG 0x3A20_0000 38 UART2 0x3D00_0000 18 FCSCALER 0x3A40_0000 39 Reversed 0x3D10_0000 19 Reserved 0x3A60_0000 40 Reserved 0x3D20_0000 20 USB2.0(OTG) 0x3A80_0000 41 ADC_CON 0x3D30_0000 21 NAND_FLASH 0x3AA0_0000 42 Reversed 0x3D40_0000 43 APU_MPVD3 0x3D50_0000 44 APU_MPVD4 0x3D60_0000 45 JOG 0x3D70_0000 46 PG 0x3D80_0000 47 SPDIFIN 0x3D90_0000 48 USB2.0(OTG) 0x3DA0_0000 Figure 1-4. Base Address of memory mapped IP . Email:Tech@fosvos.com 1-10 HotTel:+86-21-58998693
  • 12. S5L2010D S5L2010X01-X080 S5L2010A S5L2010X01-X081 S5L2010L S5L2010X02-X080 S5L2010 PRODUCT OVERVIEW BOOT MODE The S5L2010 DPF SOC can be booted from NAND or Flash memory when system initialization begins. Configuration mode is selected Boot1, Boot0 pin status. Boot 1 Boot 0 Available JTAG 0 0 Case1 : Port 3 Serial Flash Booting Internal ROM Booting (NAND Flash or SD Card) 0 1 Case2 : Port 0 1 0 - 1 1 Configuration Mode - Test Debugging environment ( JTAG ) The S5L2010 DPF SoC has 2 JTAG ports. The ARM core processor can be controlled through its JTAG port. PC JTAG : nTRST Debugger User select Case 1 : JTAG or Memory I/F Case2 : JTAG or Serial Flash JTAG TDI TDO TMS TCK RTCK JTAG Port 3 Port 0 ARM9 Boot 0 Boot 1 Figure 1-5. JTAG Interface Email:Tech@fosvos.com HotTel:+86-21-58998693 1-11
  • 13. S5L2010D S5L2010X01-X080 S5L2010A S5L2010X01-X081 S5L2010L S5L2010X02-X080 PRODUCT OVERVIEW S5L2010 121 P0.4/SF_D1 122 P0.6/SF_CLK 123 VDDP6 124 P0.3/RXD1 125 P0.2/TXD1 126 P0.1/NRTS1 127 P0.0/NCTS1 128 P1.7/IRIN 129 P2.0/CF_DATA0 130 P2.1/CF_DATA1 131 P2.2/CF_DATA2 132 P2.3/CF_DATA3 133 P2.4/CF_DATA4 134 P2.5/CF_DATA5 135 P2.6/CF_DATA6 136 P2.7/CF_DATA7 137 P4.0/CF_RESET/SDCLK 138 VSS2 139 VDDC2 140 P3.6/CF_IOWR 141 P3.7/CF_IORD 142 P3.5/CF_IORDY 143 P4.1/NAND_CE 144 P4.2/xD_CE/SDCLK 145 P3.0/CF_A0 146 P3.1/CF_A1 147 P3.2/CF_A2 148 P3.3/CF_CE0 149 P3.4/CF_CE1 150 P4.3/NAND_R/B 151 VDDP7 152 P1.3/TS_VALID 153 P1.2/TS_DATA 154 P1.1/TS_SYNC 155 P1.0/TS_CLK 156 P1.4/TS_ERROR 157 P1.6/PWM2/MDA7 158 P1.5/PWM1/MDA6 159 P5.7/I2CCLK/MDA5 PACKAGE 160 P5.6/I2CDAT/MDA4 PIN ASSIGNMENT MDA4 1 MDA3 2 MDA5 3 MDA2 4 MDA6 5 MDA1 6 MDA7 7 MDA0 8 MDA8 9 MDA10 10 VDDP0 11 110 AVDD331 MDA9 12 109 AVDD330 MDA11 13 108 AVSS0 BA1_NDCS1 14 BA0 15 NDCS0 16 NRAS 17 104 AVSS1 VSS0 18 103 VDD12_USB VDDC0 19 DCLK 20 NCAS 21 NDWE 22 DQM 23 MDB8 24 MDB7 25 MDB9 26 MDB6 27 MDB10 28 MDB5 29 MDB11 30 MDB4 31 MDB12 32 MDB3 33 VDDP1 34 MDB13 35 86 VDDP4 MDB2 36 85 P10.2/INT6/A_mute MDB14 37 84 P5.3/Audio_R MDB1 38 MDB15 39 MDB0 40 DVB-T I/F UART Memory Card Interface 120 P0.7/SF_CS Serial Flash 119 P0.5/SF_D0 118 VDD33A_ADC Touch ADC 116 ADCAIN6(XM) 115 ADCAIN5(YP) 114 ADCAIN4(YM) 113 ADCAIN3 112 ADCAIN2 SDRAM I/F 111 ADCAIN1 107 DP_USB20 USB2.0 OTG 106 TXRTUNE 105 DM_USB20 S5L2010F 160LQFP-2424 Analog/Digital DDI/LCD I/F 102 VSS_USB 101 AVSSC 100 XO 99 XI 98 VDDP5 97 PLL2VDD12 PLL 96 PLL1VDD12 95 PLL0VDD12 94 RTCXTAL1 RTC 93 RTCEXTAL1 92 VDDRTC SDRAM I/F 91 VSSRTC 90 BOOT1 89 BOOT0 Audio 2-ch 88 NRESET 87 P10.3/PWM2 83 P5.2/Audio_L Video DAC DDI/LCD I/F 82 P5.1/PWM2 DDI/LCD I/F 81 P5.0/PWM1 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 P4.5/I2CCLK/SPDIFO/MDB15 P4.4/I2CDAT/PCLK/MDB14 R0 R1/PWM1/NCTS1 R2/PWM2/NRTS1 R3 R4/Sample_Hold R5 G0 G1/UP_DOWN G2 VDDP2 G3/STVD/TxD1 G4/STHR/RxD1 G5 B0 B1/LEFT_RIGHT DACVDD33D DAC3_B DAC2_G DAC1_R DACVDD33A1 DACIREF DACVREF DACCOMP B2 B3 B4 B5 VSS1 VDDC1 P6.3/STH_L P6.4/PCLK P6.5/LATCH P6.6/POL VDDP3 P6.1/TCON_OE P6.0/CPV P6.2/STV_U P6.7/VCOM Figure 1-6. S5L2010F Pin Assignments (160-LQFP-2424) Email:Tech@fosvos.com 1-12 117 ADCAIN7(XP) HotTel:+86-21-58998693
  • 14. S5L2010D S5L2010X01-X080 S5L2010A S5L2010X01-X081 S5L2010L S5L2010X02-X080 111 P4.0/CF_RESET/SDCLK 110 P2.7/CF_DATA7 109 P2.6/CF_DATA6 108 P2.5/CF_DATA5 107 P2.4/CF_DATA4 106 P2.3/CF_DATA3 105 P2.2/CF_DATA2 104 P2.1/CF_DATA1 103 P2.0/CF_DATA0 102 P1.7/IRIN 101 P0.2/TXD1 100 P0.3/RXD1 99 VDDP6 98 P0.6/SF_CLK 97 P0.4/SF_D1 113 P3.6/CF_IOWR 112 VDDC2 114 P3.7/CF_IORD 116 P4.1/NAND_CE 115 P3.5/CF_IORDY 118 P3.0/CF_A0 117 P4.2/xD_CE/SDCLK 120 P3.2/CF_A2 119 P3.1/CF_A1 122 P3.4/CF_CE1 121 P3.3/CF_CE0 128 MDA4/P5.6 127 MDA5/P5.7 126 MDA6/P1.5 125 MDA7/P1.6 124 VDDP7 123 P4.3/NAND_R/B PRODUCT OVERVIEW PACKAGE S5L2010 MDA3 1 MDA2 2 MDA1 3 MDA0 4 MDA8 5 MDA10 6 VDDP0 7 MDA9 8 MDA11 9 BA1_NDCS1 10 BA0 11 NDCS0 12 NRAS 13 VDDC0 14 DCLK 15 NCAS 16 NDWE 17 DQM 18 MDB8 19 MDB7 20 MDB9 21 MDB6 22 75 BOOT1 MDB10 23 74 BOOT0 Memory Card Interface UART Serial Flash Touch ADC SDRAM I/F 96 P0.5/SF_D0 95 P0.7/SF_CS 94 VDD33A_ADC 93 ADCAIN7(XP) 92 ADCAIN6(XM) 91 ADCAIN5(YP) 90 ADCAIN4(YM) 89 AVDD331 USB2.0 OTG S5L2010D 128-eTQFP Digital LCD/DDI I/F 88 DP_USB20 87 TXRTUNE 86 DM_USB20 85 VDD12_USB 84 XO 83 XI 82 VDDP5 PLL RTC 81 PLL2VDD12 80 PLL1VDD12 79 PLL0VDD12 78 RTCXTAL1 77 RTCEXTAL1 76 VDDRTC MDB5 24 MDB11 25 MDB4 26 MDB12 27 MDB3 28 VDDP1 29 68 P5.3/Audio_R MDB2 30 67 P5.2/Audio_L MDB1 31 MDB0 32 Audio 2-ch SDRAM I/F 73 NRESET 72 P10.4/PWM3 71 P10.3/PWM2 70 VDDP4 69 P10.2/INT6/A_mute DDI/LCD Interface 66 P5.1/PWM2 65 P5.0/PWM1 B0 P6.7/VCOM P6.2/STV_U P6.0/CPV P6.1/TCON_OE VDDP3 P6.6/POL P6.5/LATCH P6.4/PCLK P6.3/STH_L VDDC1 B5 B4 B3 B2 B1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 G5 50 49 G4 G3 48 G2 47 46 G1 VDDP2 44 G0 45 43 R4 R5 R2 42 40 R1 41 38 R3 37 R0 MDB13/P4.6 MDB15/P4.5 MDB14/P4.4 39 36 35 34 33 Figure 1-7. S5L2010D Pin Assignments (128-eTQFP-1414) Email:Tech@fosvos.com HotTel:+86-21-58998693 1-13
  • 15. S5L2010D S5L2010X01-X080 S5L2010A S5L2010X01-X081 S5L2010L S5L2010X02-X080 111 P4.0/CF_RESET/SDCLK 110 P2.7/CF_DATA7 109 P2.6/CF_DATA6 108 P2.5/CF_DATA5 107 P2.4/CF_DATA4 106 P2.3/CF_DATA3 105 P2.2/CF_DATA2 104 P2.1/CF_DATA1 103 P2.0/CF_DATA0 102 P1.7/IRIN 101 P0.2/TXD1 100 P0.3/RXD1 99 VDDP6 98 P0.6/SF_CLK 97 P0.4/SF_D1 113 P3.6/CF_IOWR 112 VDDC2 114 P3.7/CF_IORD 116 P4.1/NAND_CE 115 P3.5/CF_IORDY 118 P3.0/CF_A0 117 P4.2/xD_CE/SDCLK 120 P3.2/CF_A2 119 P3.1/CF_A1 122 P3.4/CF_CE1 121 P3.3/CF_CE0 124 VDDP7 123 P4.3/NAND_R/B S5L2010 128 MDA4/P5.6 127 MDA5/P5.7 126 MDA6/P1.5 125 MDA7/P1.6 PACKAGE PRODUCT OVERVIEW MDA3 1 MDA2 2 MDA1 3 MDA0 4 MDA8 5 MDA10 6 VDDP0 7 MDA9 8 89 AVDD331 MDA11 9 88 DP_USB20 BA1_NDCS1 10 BA0 11 NDCS0 12 NRAS 13 VDDC0 14 DCLK 15 NCAS 16 NDWE 17 DQM 18 MDB8 19 MDB7 20 MDB9 21 MDB6 22 MDB10 23 74 BOOT0 Serial Flash UART Memory Card Interface Touch ADC SDRAM I/F 96 P0.5/SF_D0 95 P0.7/SF_CS 94 VDD33A_ADC 93 ADCAIN7(XP) 92 ADCAIN6(XM) 91 ADCAIN5(YP) 90 ADCAIN4(YM) 87 TXRTUNE USB2.0 OTG S5L2010A 128-eTQFP Analog LCD/DDI I/F 86 DM_USB20 85 VDD12_USB 84 XO 83 XI 82 VDDP5 81 PLL2VDD12 80 PLL1VDD12 PLL 79 PLL0VDD12 78 RTCXTAL1 77 RTCEXTAL1 RTC 76 VDDRTC 75 BOOT1 MDB5 24 73 NRESET MDB11 25 72 P10.4/PWM3 MDB4 26 MDB12 27 MDB3 28 VDDP1 29 MDB2 30 MDB1 31 MDB0 32 71 P10.3/PWM2 SDRAM I/F Audio 2-ch Video DAC DDI/LCD I/F DACIREF P10.1/PWM2 P10.0/PWM1 P6.7/VCOM P6.2/STV_U P6.0/CPV P6.1/TCON_OE VDDP3 P6.6/POL P6.5/LATCH P6.4/PCLK P6.3/STH_L VDDC1 P10.5 DACCOMP DACVREF 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DACVDD33A1 50 49 DAC1_R DAC2_G 48 47 DACVDD33D DAC3_B P9.1/LEFT_RIGHT 46 44 P8.4/STHR/RxD1 45 43 VDDP2 P8.3/STVD/TxD1 P7.4/Sample_Hold 42 40 P7.2/PWM2/NRTS1 41 38 P8.1/UP_DOWN 37 P7.1/PWM1/NCTS1 MDB13/P4.6 MDB15/P4.5 MDB14/P4.4 39 36 35 34 33 Figure 1-8. S5L2010A Pin Assignments (128-eTQFP-1414) Email:Tech@fosvos.com 1-14 HotTel:+86-21-58998693 70 VDDP4 69 P10.2/INT6/A_mute 68 P5.3/Audio_R 67 P5.2/Audio_L 66 P5.1/PWM2 65 P5.0/PWM1
  • 16. S5L2010D S5L2010X01-X080 S5L2010A S5L2010X01-X081 S5L2010L S5L2010X02-X080 S5L2010 PRODUCT OVERVIEW GPIO TABLE 128D핀 101 100 97 96 98 95 126 125 102 103 104 105 106 107 108 109 110 118 119 120 121 122 115 113 114 111 116 117 123 33 34 35 65 66 67 68 10 9 128 127 128D핀 62 61 63 56 57 58 59 64 36 37 38 39 40 41 42 43 44 46 47 48 49 50 51 52 53 54 69 71 72 PORT 128A핀 160핀 127 126 101 125 100 124 97 121 96 119 98 122 95 120 155 154 153 152 156 126 158 125 157 102 128 103 129 104 130 105 131 106 132 107 133 108 134 109 135 110 136 118 145 119 146 120 147 121 148 122 149 115 142 113 140 114 141 111 137 116 143 117 144 123 150 42 33 41 34 35 65 81 66 82 67 83 68 84 10 14 9 13 128 160 127 159 PORT 128A핀 160핀 60 78 59 77 61 79 54 72 55 73 56 74 57 75 62 80 43 36 44 37 45 46 38 47 48 49 39 50 51 41 53 42 54 55 56 43 57 66 67 68 69 63 64 69 85 71 87 72 52 Name P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P4.6 P5.0 P5.1 P5.2 P5.3 P5.4 P5.5 P5.6 P5.7 Name P6.0 P6.1 P6.2 P6.3 P6.4 P6.5 P6.6 P6.7 P7.0 P7.1 P7.2 P7.3 P7.4 P7.5 P8.0 P8.1 P8.2 P8.3 P8.4 P8.5 P9.0 P9.1 P9.2 P9.3 P9.4 P9.5 P10.0 P10.1 P10.2 P10.3 P10.4 P10.5 Func0 Func1 Func2 Func3 Name Name Name I/O Name INT0 output NCTS1 I TxD2 input output NRTS1 O RxD2 input output TXD1 O NTRST INT7 output RXD1 I TDI input output SF_D1 B TDO input output SF_D0 B TMS input output SF_CLK O RTCK TCK input output SF_CS O input output PWM1 O TxD1 input output PWM2 O NCTS2 input output PWM3 O NRTS2 INT1 output TAOUT(PWM) O TxD2 INT2 output TBOUT(PWM) O TACLK input output PWM1 O MDA6 input output PWM2 O MDA7 PWM3 O input output IRIN input output CF_DATA[0] B IO[0] input output CF_DATA[1] B IO[1] input output CF_DATA[2] B IO[2] input output CF_DATA[3] B IO[3] input output CF_DATA[4] B IO[4] input output CF_DATA[5] B IO[5] input output CF_DATA[6] B IO[6] input output CF_DATA[7] B IO[7] input output CF_A0 O CLE input output CF_A1 O ALE input output CF_A2 O RE input output CF_CE0 O WE input output CF_CE1 O input output CF_IORDY I R/B0 input output CF_IOWR O R/B1(xD) input output CF_IORD O input output CF_RESET O input output CE0 input output CE1(xD) input output MDA12 O R/B0 input output I2CDAT B MDB14 input output I2CCLK B MDB15 INT3 output PWM1 O MDB13 input output PWM1 O INT5 output PWM2 O input output PWM0_L_REG O PWM0_L input output PWM0_R_REG O PWM0_R input output BA1_nDCS1 O input output MDA11 O input output MDA4 O I2CDAT input output MDA5 O I2CCLK Func0 Func1 Name Name input output input output input output input output input output input output input output INT4 output input output input output input output input output input output input output input output input output input output input output input output input output input output input output input output input output input output input output input output input output INT6 output input output input output input output LCD(Digital) Func2 Name PWM1 DE PWM1 PWM2 PCLK H-Sync V-Sync PWM2 R0 R1 R2 R3 R4 R5 G0 G1 G2 G3 G4 G5 B0 B1 B2 B3 B4 B5 PWM1 PWM2 TxD2 RxD2 I/O O I I I O I O I O I O O I O O I B B B B B B B B O O O O Func4 Name TAOUT(PWM) TBOUT(PWM) PWM1 IRIN PWM1 PWM2 CKO Func5 Name EMG1 EMG2 EMG3 PWM3 NCTS1 NRTS1 TACLK I/O O O O I O O O NCTS2 NRTS2 RxD2 TxD2 I O I O PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 DIO[0] DIO[1] DIO[2] DIO[3] I/O O O O O Func7 Name TACAP TBCAP IIS_IN IIS_DAT0 IISLRCK IISBCLK IISMCLK I/O I I I O O O O nPWM1 nPWM2 nPWM3 TxD2 RxD2 O O O O I I I I I I SPICLK MOSI MISO B B B SPDIFO CKO O O RTCOSC O PWM1 O NTRSTADM TDOADM TDIADM TMSADM TCKADM NTRST TDI TDO TMS TCK O O CLK0 I B JOG1 B JOG2 B PCLK B BS O nRST_LCD Ext_LCD_Int Ext_LCD_Int O I I PG0 PG1 PG2 PG3 PCLK SPDIFO EMG1 EMG2 I I I I TxD2 RxD2 O O O O O O O O I CF_DATA[8] CF_DATA[9] CF_DATA[10] CF_DATA[11] CF_DATA[12] CF_DATA[13] CF_DATA[14] B B B B B B B CF_DATA[15] O I I O NRTS1 B O O SCLK I/O O O I I CMD0 CLK0 Func8 Name I O I I I I I O I I PWM2 TS_CLK TS_SYNC TS_DATA TS_VALID TS_ERROR O O O O O O O O B B B B Func6 Name STV_D UD STH_R LR RTCK TS_CLK TS_SYNC TS_DATA TS_VALID TS_ERROR SPICLK MOSI MISO DAT[0] DAT[1] DAT[2] DAT[3] DAT[4] DAT[5] DAT[6] DAT[7] I I I I I B B B B B B B B B B B I/O I I I O I O I O O B B JOG1 JOG2 LCD(Analog) TCON(Digital) Func3 Func4 I/O Name I/O Name O I CPV TS_CLK O I OE TS_SYNC O I STV_U TS_DATA O I STH_L TS_VALID O I PCLK TS_ERROR O O LATCH H-Sync O O POL V-Sync O SPDIFO O VCOM O R0 O PWM1 O R1 O PWM2 O R2 O X R3 O SPDIFO O R4 O X R5 O G0 O SPDIF_IN I G1 O X G2 O TxD1 O G3 O RxD1 I G4 O X G5 O JOG1 I B0 O JOG2 I B1 O X B2 O X B3 O X B4 O X B5 O O O JOG1 I I2CDAT I JOG2 I I2CCLK I/O O O O O O O O O O O O O O O O O O O O O O O O O O O TCON(Analog) CPU IF Func5 Func6 Name I/O Name O CPU_CS CPV O OE(OEV) O CPU_RS STV_U O CPU_RD STH_L O R_CLK O G_CLK O CPU_V-Sync B_CLK VCOM O WR D1 O D2 MODE1 O D3 MODE2 X D4 Sample&Hold O D5 X D6 D7 UD O D8 X D9 STV_D O D10 STH_R O D11 X D12 D13 LR O D14 X D15 X D16 X D17 X D18 B B PG1 PG0 TBCLK SPDIFO O O I O Auto_mute PWM2 PWM3 I/O O O O O O B B B B B B B B B B B B B B B B B B O O O Func7 Name VDAT0 VDAT1 VDAT2 VDAT3 VDAT4 VDAT5 VDAT6 VDAT7 BTCLK NCTS1 NRTS1 Auto_mute I I I/O O O O O O O CF_DATA[8] CF_DATA[9] B B B CF_DATA[11] CF_DATA[12] CF_DATA[13] CF_DATA[14] B B B B CF_INTREQ CF_DATA[15] CF_DMACK CF_DMAREQ JOG1 JOG2 Func8 Name IISMCLK IISBCLK IISLRCK IIS_DAT0 IIS_DAT1 IIS_DAT2 CF_DATA[10] I/O O O O O O O O O O I O I B O I O Email:Tech@fosvos.com HotTel:+86-21-58998693 1-15
  • 17. S5L2010D S5L2010X01-X080 S5L2010A S5L2010X01-X081 S5L2010L S5L2010X02-X080 PRODUCT OVERVIEW S5L2010 PIN DESCRIPTION Table 1-1. S5L2010F/D/A Pin Descriptions Pin name I/O Description S5L2010F 160-LQFP S5L2010D 128-eTQPF S5L2010A 128-eTQPF GPIO NRESET B XI I XO O BOOT1 BOOT0 I I System Global reset input when LVD is disabled. Global reset output when LVD is enabled. (active low) 27MHz Oscillator clock input, or crystal input Oscillator out to connected to XI, If no crystal used, must be left NC. Boot mode control 1 Boot mode control 0 CKO O PLLs Clock out for test RTC RTC Crystal output RTC Crystal Input RTC power(3.3V) RTC ground ARM9 Debugger Tap controller reset (active low) for ARM JTAG. RTCXTAL1 RTCEXTAL1 VDDRTC VSSRTC O I P P NTRST I TDI I Test data input for ARM JTAG TDO O Test data output for ARM JTAG TMS I Tap controller Machine State control for ARM JTAG TCK I ARM JTAG Clock Input RTCK O ARM debug sync clock NTRSTADM I TDOADM TDIADM O I TMSADM I TCKADM I ADM Debugger Tap controller reset (active low) for ADM JTAG Test data output for ADM JTAG Test data input for ADM JTAG Tap controller Machine State control for ADM JTAG ADM JTAG Clock Input Email:Tech@fosvos.com 1-16 HotTel:+86-21-58998693 PIN GPIO PIN GPIO PIN - 88 - 73 - 73 - 99 - 83 - 83 - 100 - 84 - 84 90 89 P0.6 122 P1.7 128 S5L2010F 94 93 92 91 S5L2010F P0.2 125 P3.0 145 P0.3 124 P3.1 146 P0.4 121 P3.2 147 P0.5 119 P3.3 148 P0.7 120 P3.4 149 P0.6 122 P3.6 140 S5L2010F 75 74 P0.6 98 P1.7 102 S5L2010D 78 77 76 S5L2010D P0.2 101 P3.0 118 P0.3 100 P3.1 119 P0.4 97 P3.2 120 P0.5 96 P3.3 121 P0.7 95 P3.4 122 P0.6 98 P3.6 113 S5L2010D 75 74 P0.6 98 P1.7 102 S5L2010A 78 77 76 S5L2010A P0.2 101 P3.0 118 P0.3 100 P3.1 119 P0.4 97 P3.2 120 P0.5 96 P3.3 121 P0.7 95 P3.4 122 P0.6 98 P3.6 113 S5L2010A P2.3 132 P2.3 106 P2.3 106 P2.4 P2.5 133 134 P2.4 P2.5 107 108 P2.4 P2.5 107 108 P2.6 135 P2.6 109 P2.6 109 P2.7 136 P2.7 110 P2.7 110