3 d ic

3D IC 設計簡介

STC/ITRI 特助
半導體產業推動辦公室副主任
唐經洲

1
20090612 成大CAD

Outline

More than Moore
Process of 3D IC
Advantages of 3D IC

2

Moore 咒 (1965)
Relative Manufacturing cost per Computer

Number of Computer per Integrated Circuit

3
2008/04 in Golden Moore’s Office

Moore’s 1st and 2nd Law
Moore’s First Law
Chip Density will double ever 18months.
This means that memory sizes, processor power,
etc. all follow the same curve.
Moore’s Second Law
The cost of building chip fabrication plants will
continue to increase (and the return on investment
to decrease) until it becomes fiscally untenable to
build new plants.
i.e. while it may be technologically possible to
continue to double the density of chips every 18
months, the cost of achieving this goal will
eventually surpass the profit.
4
www.ucd.ie/mecheng/ams/S%20Daniels%20Recent%20advances%202.pdf

Moore’s Law on Microprocessor
Duo core Itanium

1.7 B Trs.

Pentium

486

4004

5

2003-2008年台灣IC設計業各項重要指標 (1/2)

2003 2004 2005 2006 2007 2008
廠商家數 250 260 268 267 272 275
營業額(億元新台幣) 1,902 2,608 2,850 3,234 3,997 3,749
成長率 28.7% 37.1% 9.3% 13.5% 23.6% -6.2%
內銷比例 45% 37% 34% 34% 33% 39%
資本支出/營業額 3.5% 2.5% 3.0% 3.2% 3.3% 3.1%
R&D/營業額 12.8% 9.1% 10.0% 10.8% 11.2% 11.5%
營業額成長率
5,000 40.00%
4,000 30.00%
3,000
20.00%
2,000
1,000 10.00%

0 0.00%
2002 2004 2006 2008 2010 2002 2004 2006 2008 2010
-10.00%
6

2003-2008年台灣IC設計業各項重要指標 (2/2)

2003 2004 2005 2006 2007 2008
毛利率
37.0% 34.6% 36.0% 37.0% 37.3% 36.9%
營業利益率
21.4% 19.0% 20.1% 20.6% 20.8% 20.7%
稅後淨利率
20.4% 15.0% 16.3% 16.8% 17.1% 16.9%
平均員工產值
1,514 1,242 1,124 916 1,132 1,116
(萬/新台幣)

1999~2007年各主要
貨幣兌美元走勢圖

7
(年)

More than Moore 3D ICIC ??
More Money – – 3D ??

8
20090612 成大CAD

Skyscrapers

Location : Dubai Location : Taiwan Location : Malaysia
Height : 705 Meters Height : 508 M Height : 452 Meters
Floors : 160 Floors : 101 Floors : 88 9
To Be Completed : 2008 Built : 2004 Built : 1998

More Than Moore: 3D IC
3-D Integrated
Planar (2-D) Integrated Circuits
Solid State Discrete Circuits
Transistors

Heterogeneous Integration
1947
1950s 1960s 1958
1970s 1980s 1990s 2000s
2000s 2010s 2020s
1950s 2000s 2010s 2020s
>>1B
transistors

Source: Fairchild, Intel
10
& CS Tan(NTU-SG)

2D vs. 3D

20顆晶片
堆疊(TSV)

11
http://www.jonathassociates.com/AJA/droppedImage.png

Why Not SOC ?

投資成本 (Cost) 負擔太高
材料 (Material) 發展不易
微影技術 (Lithography) 太過困難
3D 電晶體架構 (Transistor Architecture)
尚未成熟
製程變異性(Variability) 難以掌握
散熱問題 (Thermal Dissipation)影響深遠

14

投資成本 (Cost) 負擔太高(1/2)

SOC 早在 2003 年的 ISSCC 已經被 Intel 的一
位Architecture 主管 Jay Heeb宣告``死刑‘’了

15

投資成本 (Cost) 負擔太高(2/2)

16

材料 (Material) 發展不易 (1/2)

17

材料 (Material) 發展不易 (2/2)
1990~2000 2000~2005 2005~2010
Glass (oxide) Glass (oxide) Glass (oxide)
Tungsten Tungsten Tungsten
Copper Copper
Shallow Trench Shallow Trench
Polysilicon Polysilicon
Low K
Cap Ultra Low k
Metal Gates
Gate Insulators
High k Dielectrics
Ir & Pt Electrodes
Magnetics

18

Delay in Low-k Implementation

19

微影技術 (Lithography) 太過困難 (1/2)

45nm
Lithography
Lithography
Layout pattern
Layout pattern
65nm dependence
dependence
90nm Lithography
Lithography Immersion litho,
Immersion litho,
Back-end integration
Back-end integration OPC/PSM integr. w/
OPC/PSM integr. w/ OPC/PSM integration
OPC/PSM integration
Low-k
Low-k photo-window
photo-window w/ photo window
w/ photo window
CMP
CMP Front-end/Transistor
Front-end/Transistor Front end/Transistor
Front end/Transistor
Product ramp issues
Product ramp issues Layout dependent
Layout dependent New gate/oxide
New gate/oxide
Yield vs.
Yield vs. performance
performance architectures
architectures
performance
performance Parametric variation
Parametric variation Reliability
Reliability
20

微影技術 (Lithography) 太過困難 (2/2)
Layout 0.25µ 0.18µ

0.13µ 90-nm 65-nm

21

3D 電晶體架構 (Transistor
Architecture) 尚未成熟

22

製程變異性(Variability) 難以掌握

23

散熱問題 (Thermal Dissipation)影響深遠 (1/2)

IBM
24

散熱問題 (Thermal Dissipation)影響深遠 (2/2)

Intel
25

Via First Process

26

Via Last Process

Laser drilling

Wet Etching Plasma (DRIE) Etching
27

FSI (Front Side Illumination) vs. BSI

29

SoC vs. SiP vs. 3D IC 之比較
SOC SIP 3DIC
Form Factor Δ Δ √
Density Δ Δ √
Performance (speed, Δ X √
frequency, power)
Signal process packing Δ X √
density
Manufacturing cost in high Δ X √
quantities
Heterogeneous integration X √ Δ
Manufacturing cost in √ Δ X
low/medium quantities
Manufacturing ready (2007) Δ √ X
√: Best, Δ: Medium, X: Worst 30

用3D-IC 技術來設計的好處 (1/2)
提高連線密度 (Improve Interconnect Density)
減小外觀尺寸(Reduce Form Factor)
減少雜散電容與電感 (Reduce Parasitic
Capacitance/Inductance)
提高速度(Increase Speed)
降低功耗(Reduce Power Consumption)
減低生產費用(Reduce Cost)
提供異質整合 (Provide Heterogeneous Integration)
改善可靠度 (Improve Reliability)

31

用3D-IC 技術來設計的好處 (2/2)

減少 ESD 需求 (Reduce ESD
Requirement)
提高散熱效果 (Improve Heat Dissipation)
提高良率 (Increase Yield)
提高資料安全性 (Improve Data Security)
可延展性/可規畫性/可替換性
(Scalable/Reconfigurable/Replaceable)
簡易的互連體(Simple Interposer)

32

Technical Barriers -- Design

EDA Tools
Front-end
Back-end
Multi-Process
Application

33

Technical Barriers -- Thermal

Thermally aware P&R
Cooling
Thermal vias
Micro-fluid

34

Technical Barriers -- Test

KGD (Known Good Die)
Yield

35

Major Applications of 3D IC

影像感測器(CMOS Image Sensors)
記憶體(Memories)
SRAM/DRAM
NAND
處理器(Processor)
感測器與 DSP (Sensor and DSP)
現場可規劃邏輯陣列 (FPGA)
微機電系統 (MEMS)

36

3D IC Application Forecast

37

不同公司對於3D-IC 市場之預估
預估者註
iSuppli 到2010 年三維晶片市場約有 33 億美金
iSuppli 到2014 年三維晶片市場總值約有 173 億美金
Prismark 到2006 年互連市場的總值約有 340 億美金
Prismark 到2010 年14億顆3D 封裝形式的 IC
Yole 到2010 年10 億顆Flash Memory 會用 TSV 堆疊技術
Yole 到2015 年，測試 (Test) ，電子設計自動化工具 (EDA)，與熱管理(Thermal
Management)，到了 2011 年這些工具都不會成熟
Yole 到2015 年25% 的記憶體會由 3D-TSV 所設計
Yole 到2015 年6% 的IC (不含記憶體) 會由 3D-TSV 所設計
ITIS 應用3D IC 之 SSD渴望在 2010~2012 大幅成長
EMC-3D 2007年3D-LSI的加工成本約為410美元，預估到2008年降為約241美元，到2009
年則降為約162美元，已經在200美元之下，下降程度為現在成本的約60%以上
NXP 2012 年3D IC 就會真實呈現在市場上，其推動力量為 Cost, performance, 及
Form factor. 2008 3D-IC t產能為 45000 Wafer, 到了 2014 會有4 百萬片
Aviza 2007: 未來5~10 年會有50% 的晶片是由 TSV 技術所製造
Advanced 2008 年TSV 市場開始， 2009 年Flash Memory可以量產，2010 年3D SRAM 與
Package DRAM 市場開始 38

3D IC 廠商產品佈局概況
廠商型態廠商名稱主要應用產品及進度
Elpida 工業及消費性 DRAM (Prototype)
Freescale 工業 RF (Prototype), 消費性 MEMS (R&D)
Hynix 工業及消費性 Flash 及 DRAM (Prototype)
IBM RF (Prototype), CIS (R&D)
Intel Logic (R&D)
Micron Flash, DRAM (Prototype), 汽車用 CIS (Production)
IDM NEC DRAM (Prototype)
NXP RF (Production), 消費性 MEMS (R&D)
Renesas Logic (R&D)
Samsung 通訊 CIS (Prototype), Flash, DRAM (Prototype)
Sharp CIS (Prototype), Logic (R&D)
Sony Logic (R&D)
STM RF (Production), CIS (Production)，MEMS (R&D)
Chartered DRAM (Production), Logic (Prototype)
Foundry
TSMC CIS, MEMS (R&D)
Amkor Flash, DRAM (Prototype)
Packaging ASE RF (Prototype), DRAM, Flash (Prototype)
Xintec CIS (Production) 39

3D IC Example: Samsung

Samsung 16Gb NAND stack with TSV

http://www.techpowerup.com/10837/Samsung_Develops_3D_Memory_Package.html
40

3D IC Example: IMEC

41

Intel 80 cores 3D IC structure

42

歐盟 e-Cube

德積 /MuChip…
雷凌/RaLink…
聯發科/MediaTek
盛群/Holtek, 義隆/ELAN…
原相/PixArt…
力錡/Richtek…

學術界 (台清交成…)

將環境變化轉化為電力

43

3D IC EDA Tool: R3 Logic

44

3D EDA Tool: Cadence

45

2 ½ D or 3D ?

Intel 45nm

Systems-in-a-Cube
(Source: IMEC)

http://www.solid-state.com/articles/article_display.html?id=224942
46

Effort Needed for Manufacutrable 3D

47

Technical Challenges for 3D IC

48

Business Challenge for 3D IC

49

More Closed Link on 3D IC ??
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佳茂
化學品訊利

台銷（硝酸）金線
永光（光阻劑）
致茂
長興（CMP劑） 50

加量不加價 ?

51

新的3D 定義

altitu D e
D ocument
rea D ing
52

Thanks for Your Attention

53

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