The document discusses how adaptive system on chips (SoCs) can be achieved using policy-based control similar to how networks adapt using policies. It introduces ChipStart's Subsystem Management Module (SSM) which acts as a control plane that operates based on software policies. The SSM allows policies to be loaded and converted into commands to adaptively control cache utilization, power management, and error recovery based on the applications and operational conditions. The SSM provides a way to scale SoC architectures efficiently with high reliability.

1. Adaptive SoC Operations Using Policy Based System Control
Network devices often include “tap points” dispersed across the network’s flows that collect analytics
for monitoring and adapting the network’s behavior according to the actual usage, priority, and type of
content passing through it. Policies such as Quality of Service (QoS), Policy Based Routing (PBR), and
even Call Admission Control (CAC) can then be applied based on the analytics that form the policies for
the adaptation.
As the complexity of SoC operations grow, they too are more resembling networks. For example, the
concept of distributed caches with coherency, recently introduced as an innovation in SoC interconnect
technology, resembles the queues in a network device. But where are the equivalentQoS or PBR
“policies” for the SoC that are present in networks and provide the key adaptive decision making
components?
ChipStart’s SSM represents a control plane for SoCs that operates based on software policies. SSM is a
key subsystem IP component that can be added to any SoC to provide the key missing components to
enable adaptive SoC operations.
The figure above represents a typical implementation of a multicore SoC which contains the SSM
Subsystem IP. Software policies are loaded in the SSM Controller, which in turn converts those policies
into commands. These commands are sent to the SSM MCB’s via the SSM bus for further conversion to
signals and messages to the corresponding IP Blocks. However, since SSM supports bidirectional
communications, the IP Blocks, via the SSM MCBs, can also feedback state data to the SSM Controller via
the SSM bus. This creates the infrastructure for adaptation.
For example, each of the data plane caches associated with the IP blocks can be monitored for cache
misses by the SSM MCBs and reported to the SSM Controller. The SSM Controller then can send the
rolled up view of cache utilization as a global view analytic to the host processor. The host processor
selects the appropriate SSM policy from a set of policies optimized for use cases, a decision that is made
in conjunction with the application requirements, and loads the policy into the SSM Controller memory
for execution. The SSM Controller can then work together with the memory scheduler to better
optimize data block retrieval and distribution, driven by the SSM policy. The result, improved cache
utilization and increased system performance. Alternatively more complex polices can be loaded that
allow the SSM Controller itself to make decisions based on operations conditions. minimizing host
processor participation.

2. While the main benefit is more effective execution of the application, this can also lead to improved
power management (turning on and off IP blocks when caches are empty for example) and more
predictable error recovery.
Another alternative is to add intelligence to the SSM MCBs themselves, localizing the monitoring and
decision making, which is globally managed by the SSM Controller. This is especially effective when the
IP Blocks transition to IP subsystems and hierarchical interconnect structures become a reality. By using
control plane policy commandsto drive arbitrationdecisions for all the interconnects, data path control
globally across the SoC and within the subsystems themselves can be tied efficiently to application
behavior. This effectively creates policy based routing. Congestion can also be detected which in turn
can trigger flow control, using a profile of subsystem behavior, and communication back to the host
processor would enable the application to adapt as well.
SoC architectures which compliment complex data plane interconnects with control plane subsystems
will scale more efficiently and with higher operations reliability. SSM is the industry’s first merchant
subsystem IP designed for adapting control planes on SoCs while abstracting specific device
personalization to software policies. SSM has also been designed such that overhead is minimized and
real estate and power consumption required are both nominal.