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Vlsi mini project list 2013

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VLSI MINI PROJECT LIST (VHDL/VERILOG) S.NO PROJECT TITLES 1 Design Of Kogge-Stone Adder 2 Design Of (9,7 ) Using 1D-Dwt Lifting Scheme 3 Design of 16 Bit Spanning Tree Carry Look Ahead Adder 4 Design of 16 Point Radix-4 FFT (Fast Fourier Transform) Algorithm 5 Design of ATM (Automated Teller Machine) 6 A Spurious Power Suppression Technique for Multimedia/ DSP Applications 7 Design Carry Select Adder 8 Design of Dual Elevator Controller 9 Design of RCEAT for RFID Tag 10 Design of 16 Bit Ripple Carry Adder 11 Design of Dual Port SRAM 12 Multiplication Acceleration through Twin Precision 13 Design of Vending Machine 14 Design of Complex Number Multiplier Using Booth Algorithm 15 Design of Open Core Protocol (OCP) Ip Block 16 Design of Single Precision Floating Point Multiplier
17 Design and Implementation Of 8 Point FFT 18 Design and Implementation Of 8 Point IFFT 19 Design of Digital Clock 20 Design of AMBA-AHB Protocol 21 Design of DDRSD RAM Controller 22 Implementation of Traffic Light Controller 23 Implementation of Dual Port Ram 24 Implementation of Universal Asynchronous Receiver/Transmitter (UART). 25 Implementation of 32-Bit Carry Look Ahead Adders For Fast Addition 26 Implementation of 32-Bit Carry Save Adders For Fast Addition 27 Implementation of 32-Bit Pseudo Random Test Pattern Generator 28 Implementation of Mealy Type And Moore Type Serial Adders 29 Implementation of 32-Bit Braun Multipliers 30 Implementation of Matrix Multiplication 31 Implementation of Cyclic Redundancy Check 32 Implementation of 16-Bit Hamming Code Encoder And Decoder For Single Bit Error Detector And Corrector 33 Implementation of Sequence Detector Using Finite State Machines 34 Implementation of 32-Bit Wallace Tree Multipliers 36 Implementation of 8-Bit ALU 37 Implementation of Fir Filter 38 Implementation of 16-Bit Conditional Sum Adder And Parallel Prefix Adders For Fast Addition 39 Implementation of Seven Segment Display and Code Converters
40 An Efficient Architecture For 2-D Discrete Wavelet Transform.
41 Discrete Wavelet Transform Using Lifting Scheme 42 Real Time Design of Car Light Indicator 43 An Interface Between On Chip and Off Chip 44 An Efficient Linear Convolution for DSP Applications 45 Design of Traffic Light Controller Using VHDL 46 Image Compression Standards for DSP Applications (VERILOG) 47 Low Power Multiplier Using Ancient Mathematics 48 Implementation of Hamming Code Using Verilog HDL 49 Design Of Radix-2 Butterfly Processor To Prevent Overflow In The Arithmetic 50 An Efficient Architecture For 3-D Discrete Wavelet Transform. 51 Implementation Of Guessing Game Using VHDL 52 Orthogonal Frequency Division Multiplexing Using FFT/IFFT Blocks. 53 High-Accuracy Fixed-Width Modified Booth Multipliers For Lossy Applications Design Of An Advanced High Performance Bus For Real Time Internal Bus 54 Architecture 55 High-Performance Controller For Memory Processing. 56 A High Speed Controller Between Memory And Processer 57 Slave Side Implementation For The Multi-Layer High Performance Bus. 58 High Speed VLSI Architecture for General Linear Feedback Shift Registers 59 Design of High Speed Fast Fourier Transform Algorithm
60 The Design Cost Effective Binary Tree Implementation For ID Authentication System

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Vlsi mini project list 2013

  • 1. VLSI MINI PROJECT LIST (VHDL/VERILOG) S.NO PROJECT TITLES 1 Design Of Kogge-Stone Adder 2 Design Of (9,7 ) Using 1D-Dwt Lifting Scheme 3 Design of 16 Bit Spanning Tree Carry Look Ahead Adder 4 Design of 16 Point Radix-4 FFT (Fast Fourier Transform) Algorithm 5 Design of ATM (Automated Teller Machine) 6 A Spurious Power Suppression Technique for Multimedia/ DSP Applications 7 Design Carry Select Adder 8 Design of Dual Elevator Controller 9 Design of RCEAT for RFID Tag 10 Design of 16 Bit Ripple Carry Adder 11 Design of Dual Port SRAM 12 Multiplication Acceleration through Twin Precision 13 Design of Vending Machine 14 Design of Complex Number Multiplier Using Booth Algorithm 15 Design of Open Core Protocol (OCP) Ip Block 16 Design of Single Precision Floating Point Multiplier
  • 2. 17 Design and Implementation Of 8 Point FFT 18 Design and Implementation Of 8 Point IFFT 19 Design of Digital Clock 20 Design of AMBA-AHB Protocol 21 Design of DDRSD RAM Controller 22 Implementation of Traffic Light Controller 23 Implementation of Dual Port Ram 24 Implementation of Universal Asynchronous Receiver/Transmitter (UART). 25 Implementation of 32-Bit Carry Look Ahead Adders For Fast Addition 26 Implementation of 32-Bit Carry Save Adders For Fast Addition 27 Implementation of 32-Bit Pseudo Random Test Pattern Generator 28 Implementation of Mealy Type And Moore Type Serial Adders 29 Implementation of 32-Bit Braun Multipliers 30 Implementation of Matrix Multiplication 31 Implementation of Cyclic Redundancy Check 32 Implementation of 16-Bit Hamming Code Encoder And Decoder For Single Bit Error Detector And Corrector 33 Implementation of Sequence Detector Using Finite State Machines 34 Implementation of 32-Bit Wallace Tree Multipliers 36 Implementation of 8-Bit ALU 37 Implementation of Fir Filter 38 Implementation of 16-Bit Conditional Sum Adder And Parallel Prefix Adders For Fast Addition 39 Implementation of Seven Segment Display and Code Converters
  • 3. 40 An Efficient Architecture For 2-D Discrete Wavelet Transform.
  • 4. 41 Discrete Wavelet Transform Using Lifting Scheme 42 Real Time Design of Car Light Indicator 43 An Interface Between On Chip and Off Chip 44 An Efficient Linear Convolution for DSP Applications 45 Design of Traffic Light Controller Using VHDL 46 Image Compression Standards for DSP Applications (VERILOG) 47 Low Power Multiplier Using Ancient Mathematics 48 Implementation of Hamming Code Using Verilog HDL 49 Design Of Radix-2 Butterfly Processor To Prevent Overflow In The Arithmetic 50 An Efficient Architecture For 3-D Discrete Wavelet Transform. 51 Implementation Of Guessing Game Using VHDL 52 Orthogonal Frequency Division Multiplexing Using FFT/IFFT Blocks. 53 High-Accuracy Fixed-Width Modified Booth Multipliers For Lossy Applications Design Of An Advanced High Performance Bus For Real Time Internal Bus 54 Architecture 55 High-Performance Controller For Memory Processing. 56 A High Speed Controller Between Memory And Processer 57 Slave Side Implementation For The Multi-Layer High Performance Bus. 58 High Speed VLSI Architecture for General Linear Feedback Shift Registers 59 Design of High Speed Fast Fourier Transform Algorithm
  • 5. 60 The Design Cost Effective Binary Tree Implementation For ID Authentication System