1.
A Continuous-Time S-D ADC
in an
InP-based HBT Technology
Sundararajan Krishnan (PK)
A Ph. D. defense, June 25, 2002

2.
Outline
• DHBTs by substrate-transfer
design, fabrication and device results
inability to achieve medium scales of integration
• DHBTs in a conventional mesa technology
process features and device results
• Static Frequency Dividers in the mesa technology
• S - D A – D converters
metastability errors in the quantizer
excess delay in the loop
circuit techniques and results

3.
HBTs by substrate transfer
Single-Heterojunction Devices
• Substrate transfer allows independent
definition of emitter and collector widths
• Lateral scaling  ultra-high fmax
ft=204 GHz and 500-1000 GHz (??) fmax
• Vertical & lateral scaling
 simultaneous high ft and fmax
ft =295 GHz and fmax =295 GHz
0
10
20
30
40
50
1 10 10
2
Gains
(dB)
Frequency (GHz)
h
21
U
V
CE
= 1 V, J
C
= 1.5 mA/um
2
f
MAX
= 295 GHz
f
t
= 295 GHz
0
5
10
15
20
25
30
10 100 1000
Gains,
dB
Frequency, GHz
fmax
= 1.1 THz ?
ft
= 204 GHz
Mason's
gain, U
H21
MSG
emitter, 0.4 x 6 mm2
collector, 0.4 x 6 mm2
Ic
= 6 mA, V
ce
= 1.2 V
Emitter 1 x 8 mm2, Collector 2 x 8.5 mm2.
2000 Å collector
300 Å base with 52 meV grading
AlInAs / GaInAs / GaInAs HBT
3000 Å collector
400 Å base with 52 meV
grading
AlInAs / GaInAs / GaInAs
HBT
Michelle Lee
Yoram Betser

4.
Motivation for InP DHBTs
Amplifier 10 mW, 78 GHz 66 GHz static divider
• mm-wave power amplifiers
goal: fmax = 400 GHz ; BVCEO > 8 V
• High-speed logic
Ccb.DVlogic/I  major delay term
Ccb/I reduced by thinner collectors
(Icmax,kirk a 1/Tc
2)
Properties of InP
• High breakdown field (30V/mm)
• G-L spacing and mobility
comparable to InGaAs  overshoot
• Thermal conductivity
15:1 better than InGaAs
Michelle
Lee
James
Guthrie

5.
DHBT Layer Structure and Band diagram
InGaAs 1E19 Si 1000 Å
Grade 1E19 Si 200 Å
InP 1E19 Si 900 Å
InP 8E17 Si 300 Å
Grade 8E17 Si 233 Å
Grade 2E18 Be 67 Å
InGaAs 4E19 Be 400 Å
Grade 1E16 Si 480 Å
InP 2E18 Si 20 Å
InP 1E16 Si 1500 Å
Multiple stopetch layers
Buffer layer 2500 Å
Bias conditions for the band diagram
Vbe = 0.7 V
Vce = 1.5 V

6.
Base-emitter junction – Wet-etch Undercut Profile
• Extremely rough surfaces with dry etching; subsequent wet
etch unpredictable
• Wet etching results in smooth surface, but large undercut along
the length of the emitter
• Serious concern for devices with short emitter-stripes

7.
Processing Issues – Substrate Transfer
Surface spotty
with pieces of
semiconductor
InP collector
getting attacked
during substrate
removal
• InP collector has to be
effectively screened during
the substrate-removal etch
• Due to crack-initiation
issues, initial attempts used
etch-stop layers on devices
only
• Etching past the stop etch
layer when isolating mesas
resulted in removal of InP
collector during substrate
transfer
• A continuous film of InGaAs
(stop-etch layer) was needed
to protect the collector

8.
Transferred-Substrate HBT Process Flow
• emitter metal
• emitter etch
• self-aligned base
• mesa isolation
• polyimide planarization
• interconnect metal
• silicon nitride insulation
• spin Benzocyclobutene (BCB), etch vias
• electroplate gold
• bond to GaAs/AlN carrier wafer with solder
• remove InP substrate and etch-stops
• collector metal

9.
0
2 10
4
4 10
4
6 10
4
8 10
4
1 10
5
0 1 2 3 4 5
J
c
- V
ce
characteristics
J
c
(A/cm
2
)
V
ce
(volts)
DC characteristics
400 Å graded base,
500 Å base-collector
grade and 1500 Å
collector
400 Å graded base,
500 Å base-collector
grade and 2500 Å
collector
0
2 10
4
4 10
4
6 10
4
8 10
4
1 10
5
0 1 2 3 4 5 6 7
J
c
(A/cm
2
)
V
ce
(volts)
IB in steps of 50 mA
IB in steps of 50 mA
0.9*7 mm2 junction

10.
400 Å graded base,
500 Å base-collector
grade and 1500 Å
collector
400 Å graded base,
500 Å base-collector
grade and 2500 Å
collector
0
5
10
15
20
10 100
Gain
(dB)
frequency (GHz)
h
21
U
20 dB/decade
0
5
10
15
20
10 100
Gain
(dB)
Frequency (GHz)
h21
U
20 dB/decade
ft = 165 GHz; fmax = 300 GHz
ft = 215 GHz; fmax = 210 GHz
Microwave performance

11.
ICs with transferred-substrate DHBTs
• Good microwave characteristics ( 200 GHz ft,
200 GHz fmax HBT)
• Microstrip wiring environment with a low-loss
dielectric
• Initial circuit designs were in the transferred-
substrate DHBT process
• Poor yield due to process related problems

12.
Process-related problems in yielding MSI ICs
Collector-attack during
substrate transfer
In spite of multiple stop etch layers,
and bonding to AlN, 1 in 200
transistors get attacked
InP Substrate
emitter
metal
base
metal
e
b
c
polyimide
mesa
SiN
SiN
SiN
metal-1 metal-2
metal-2 heat sink
SiN
SiN
metal-1
metal-2
Large occurrence of emitter-to-ground shorts
on device mesas
Quantified using series B-E diode chains
Metal1(emitter) - Metal2 shorts

13.
Failure statistics for a 60 transistor circuit
25
50
75
100
Yield
in
%
41 %
83 %
Emitter
shorts
Base emitter
diode shorts
~ 100 %
others
Source : T. Mathew, Ph. D. thesis, 2001

14.
Metal1 (Emitter) – Metal2 shorts
Hypothesis
• Problem due to metal1 profile (spikes from angled
evaporation)
Approach
• Abandoned angled evap in favour of direct evap : much
smoother profile, but Metal1-Metal2 shorts still present
• Blanket-evaporated a thin film of dielectric (SiO2) between
Metal1 and Metal2. Reduced frequency of shorts, but not
well enough to allow MSI ICs.

15.
Need for an alternate technology
• Problems with the transferred-substrate technology
never resolved
• New, more conventional mesa-HBT technology that
circumvented both process problems
• Problem of metal1-metal2 shorts resolved by
eliminating heat-sink, avoiding metal1-metal2
crossovers; collector metal used as second level of
metal-interconnect
• Most features of the transferred-substrate process
retained (wiring environment, resistors and capacitors)

16.
Narrow-Mesa HBT
Objectives
• High yield on devices
• Good RF performance (200 GHz ft and fmax)
• Low Ccb
Approach
• Used device dimensions that had high yield in the transferred-
substrate technology (0.7 mm emitters)
• Narrow mesa for low Ccb (1.7 - 2.1 mm base-mesa ): limited by
transfer length, yield
• Pd/Ti/Pd/Au base-ohmics for reduced Rbb

17.
InP/InGaAs/InP Mesa DHBT
Device Results
• narrow 1.7 mm base mesa, 0.7 mm
emitter
• Jkirk = 2e5 A/cm2 @ Vce = 0.7 V
ft = 200 GHz; fmax=205 GHz
b = 35; BVCEO = 6 V
0
1
2
3
4
5
6
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
I
c
(mA)
V
ce
(Volts)
junction : 0.6 * 7mm2
b  -
0
10
20
30
40
50
1 10 100 1000
Gains
(dB)
Frequency (GHz)
h
21
U
Emitter metal 0.7 X 8 um
2
junction 0.6 X 7 um
2
V
ce
= 1.2 V ; J
c
= 2e5 A/cm
2
E
B
C

18.
IC wiring environment
Interconnect cross-section top view after plating ground-plane
BCB
ground plane
resistors metal1 SiN metal2
• Thin-film-dielectric (5 mm BCB) microstrip wiring
• Reduced ground via inductance, Minimal line - line
coupling
• 8 mm line gives controlled 50 W impedance

19.
Key digital element: often sets system’s maximum
clock
Neither ft nor fmax predicts digital speed
CcbDVlogic/Ic is very important
 collector capacitance reduction is critical
 increased current density is critical
Rex must be very low for low DVlogic at high Jc
Static Frequency Dividers
clock clock clock clock
in
in
out
out
ECL M-S latch
 
 
 










D








D











 D
c
ex
LOGIC
LOGIC
C
c
b
be
cb
be
cb
C
LOGIC
I
R
q
kT
V
V
I
R
C
C
R
C
C
I
V
6
least
at
be
must
swing
logic
The
resistance
base
the
through
charge
stored
collector
base
Supplying
resistance
base
the
through
charging
e
capacitanc
Depletion
swing
logic
the
through
charging
e
capacitanc
Depletion
:
by
Determined
Delay
Gate
bb
depletion
,
bb
depletion
,
t
t

20.
Divider : IC Micrograph
28 HBTs
0.7X0.7 mm2 die area
Ac/Ae ~ 4 (large)
Resistive pull-downs for
biasing to minimise
transistor count
Terminated-TL based
wiring environment to
minimise speed-of-light
delays and reduce
reflections
Output buffer to drive 50
ohm load

21.
Measurements: 4 - 40GHz Range
-0.3
-0.25
-0.2
-0.15
-0.1
-0.05
0
22 22.5 23 23.5 24
V
out
(Volts)
time (nsec)
CLK
CLK
OUT
Vee
Digitizing
Oscilloscope
10 MHz - 40 GHz
Frequency
Synthesiser
Frequency synthesiser output directly drives clock input
Measurement at fclk= 4 GHz establishes that divider is
fully static
fclk = 4 GHz

22.
Measurements: 50 – 75 GHz
• Available input power to
clock ~ + (5 - 9) dBm
• Signal delivered through
V -band waveguide, probes
CLK
CLK
OUT
Vee
Digitizing
Oscilloscope
10 MHz - 40 GHz
Frequency
Synthesiser
16.67 - 25 GHz
frequency tripler
Pout : 5 - 9 dBm
Pin = 7 dBm
-0.35
-0.3
-0.25
-0.2
-0.15
-0.1
-0.05
0
22 22.02 22.04 22.06 22.08 22.1 22.12 22.14
V
out
(Volts)
time (nsec)
fclk = 75 GHz
-0.3
-0.25
-0.2
-0.15
-0.1
-0.05
22 22.05 22.1 22.15 22.2
V
out
(Volts)
time (nsec)
fclk = 60 GHz

23.
Measurements : 75 – 110 GHz
-0.2
-0.18
-0.16
-0.14
-0.12
-0.1
-0.08
-0.06
22 22.02 22.04 22.06 22.08 22.1 22.12 22.14
V
out
(Volts)
time (nsec)
fclk = 87 GHz
CLK
CLK
OUT
Vee
Digitizing
Oscilloscope
10 MHz - 40 GHz
Frequency
Synthesiser
Pin = -12 dBm
20 - 40 GHz
Amplifier
75 - 110 GHz
Amplifier
25 - 36.67 GHz
frequency tripler
Pout : 3 - 6 dBm
5 -10 dBm
10 dBm
• fclk, max = 87 GHz
• Jc = 2.6 mA/mm2
• Pdiss = 700 mW

24.
D-S : Theory, Design and Results

25.
Motivation: Why D-S ADCs
Nyquist rate ADCs require :
Extremely high component precision
(16 bit ADC may require up to 216 high resolution comparators)
Anti-aliasing filter with very sharp cut-off
Oversampling ADCs :
Trade resolution in time for resolution in bandwidth ,
tolerates imprecise analog circuits
Specs. on analog anti-aliasing filter eased
D-S ADCs : Use negative feedback to improve
ADC resolution
Typical applications :
Digital Audio, Digital Telephony, and instrumentation
Radar systems with faster technologies

26.
Delta Sigma Modulation : Introduction
D-S ADC : High resolution
through
• Oversampling
• Noise shaping
Oversampling : Sampling
above Nyquist rate
Noise shaping : Use of
negative feedback to
control the spectrum of
the quantization noise
Signal
bandwidth
Power
spectral
density
Frequency
With just
oversampling
With noise
shaping
S. Jaganathan

27.
System level block diagram
Linear system in forward path
• Low pass filter (Base band ADC)
• Band pass filter (Band pass ADC)
Order of filter  order of ADC
Quantizer is a n-bit ADC (n=1  Latched comparator)
Feedback path may have n-bit DAC
A Linear
System
S
fclock
x(t) x’(t) u(t) y(t)
+
-
quantizer
S. Jaganathan

28.
Frequency (log scale)
Linear Model for Quantizer
)
.E(j
)
G(j
1
1
)
.X(j
)
G(j
1
)
G(j
)
Y(j 









Signal TF Noise TF
Signal TF Noise TF
Need large DC gain G(0) in
forward path to have maximum
in-band noise suppression
S
+
-
G(j)
X’(j)
X(j) U(j)
S
+
+
E(j)
Y(j)
= +
S. Jaganathan

29.
ADC Figure of Merit : SNR
0
40
80
1 10 100
Output
Power
Spectrum
(dB)
Frequency (arb. units)
40 dB/dec
52
Noise spectrum of 2nd order S-D
15 dB improvement in SNR for
every doubling of OSR
• Each input sample
contributes a whole train
of output samples
• Need signal processing
techniques to specify
performance (SNR)
SNR depends on
a) Order of the filter (n)
b) Over sampling Ratio
(OSR)

30.
First generation ADC results
-90
-80
-70
-60
-50
-40
-30
-20
-10
10
8
10
9
Output
Power
(dBm)
Frequency (Hz)
Pin
= -11 dBm
f
1
= 149.9 MHz
f1
= 150.1 MHz
RBW = 10 KHz
VBW = 10 KHz
Shrinivasan Jaganathan,
Ph. D. thesis, Aug 2000
• IC was built in an
InAlAs/InGaAs SHBT
substrate-transfer
process
• 160 transistors, 20
GHz clock
• Analog spectrum
analysis was used to
measure the ADC
• No noise shaping
observed below 1 GHz
Shrinivasan
Jaganathan

31.
Vout
CLK
Vin
CLK
CLK
Strong
Weak
Comparator Output edge timing
modulated by input strength
Comparator inputs DAC output pulse: error
degrades SNR directly
DAC
Output
Current
MASTER SLAVE
CML
MSFF
Feedback Error due to Metastability
logic 0
logic 1
DAC error not noise shaped : degrades SNR directly
S. Jaganathan

32.
Full loop Spice simulations
out
ADC
Transient
ADS simulation
Hard
Limiter
FFT
Matlab
in
• Circuit simulated for large number of cycles to allow
system to stabilize
• Hard limiter used to simulate a logic analyzer

33.
Reducing metastability errors
-120
-100
-80
-60
-40
-20
0
10
6
10
7
10
8
10
9
10
10
Output
Power
Spectrum
(dBFS)
Frequency (Hz)
with pre-amp
without pre-amp
  A M-S-S
DAC
S
gm
in out
20 GHz clock

34.
IC Micrograph of the 2nd
generation ADC
input
output
• Clocked at 20 GHz, used an additional stage of regeneration,
pre-amplification immediately prior to the quantizer
• Never tested due to various process-related problems

35.
Effect of M-S-S latch on SNR
• Additional stage of
regeneration necessary to
minimise metastability errors
• Excess delay introduced by
the additional stage alters
quantizer input, output
spectrum and degrades SNR
• Loss in SNR fully recovered
by moving centroid of DAC to
original position
CLK
Idac
M-S latch
Idac
M-S-S
latch
t
t
t
-120
-100
-80
-60
-40
-20
0
106
107
108
109
1010
Output
Power
Spectrum
(dBFS)
Frequency (Hz)
M-S latch
M-S-S latch
  M-S S
DAC
addl. stage of regeneration
V
S

36.
RTZ DAC : A way to recover SNR
• RTZ DAC pushes centroid
forward by Tclk/4
• Zeroes of the loop can be
adjusted to compensate for
the rest of the delay (Tclk/4)
CLK
Idac
M-S latch
t
t
-120
-100
-80
-60
-40
-20
0
106
107
108
109
1010
Output
Power
Spectrum
(dBFS)
Frequency (Hz)
MSS latch; RTZ DAC
t
z
changed
MS latch
Idac
Ideal location
RTZ DAC
t
t

T
0
dac
I
Idac
M-S-S latch
RTZ DAC
t

37.
Excess delay - Multibit quantizer
-120
-100
-80
-60
-40
-20
0
106
107
108
109
1010
Output
Power
Spectrum
(dBFS)
Frequency (Hz)
M-S latch
M-S-S latch
• ADC resolution does not
depend on excess delay in the
loop if quantizer is multi-bit
• Linear approximation holds if
quantizer is multi-bit
• Transfer function is unaltered
at low frequencies; at high
frequencies, damping factor
and overshoot will change
1 + sTz
s2Ts
2
S
E(s)
e-st
S
+
-
Vin Vout

38.
Input Stage Design
RL RL
2RL
2Rdeg
Negative resistance
• Negative Resistance loads for high DC gain
• Integrator bias current >> DAC current for high linearity ; S - D
loop overload occurs before integrator overload
• Good compromise between transistor count and performance
• Trading DC power for circuit complexity
-80
-60
-40
-20
0
20
40
-200
-150
-100
-50
0
50
100
150
200
10
6
10
7
10
8
10
9
10
10
10
11
10
12
gain
(dB)
phase
(deg)
frequency (Hz) 38 dB DC gain, pole @ 30 MHz

39.
Final designs (10 GHz clock)
-120
-100
-80
-60
-40
-20
0
10
6
10
7
10
8
10
9
Output
Power
Spectrum
(dBFS)
Frequency (Hz)
-120
-100
-80
-60
-40
-20
0
10
6
10
7
10
8
10
9
Output
Power
Spectrum
(dBFS)
Frequency (Hz)
Integrator-1
Integrator-2
Master
Slave
Slave DAC

40.
Analog measurements
-80
-70
-60
-50
-40
-30
-20
-10
0
0 5 10
8
1 10
9
1.5 10
9
Output
Power
Spectrum
(dB)
Frequency (Hz)
RBW = 3 MHz
VBW = 10 KHz
NRZ DAC
RTZ DAC
RTZ-DAC-based ADC has higher resolution (as expected)
Noise-floor of RTZ-DAC-based ADC evens out at low
frequencies ( < 125 MHz); digital acquistion needed to accurately
measure dynamic range (DR) at lower end of spectrum

41.
Measurement by Digital Acquistion
Logic Analyzer cannot read 8 Gbps; demux to 500 Mbps
Signal reconstructed in software
FFT performed in Math; no dynamic-range problems
S-D
ADC
1:16
10 G
DEMUX
LOGIC
ANAL.
16:1
MUX
FFT
CLK
IN
In software

42.
-120
-100
-80
-60
-40
-20
0
10
7
10
8
10
9
Output
Power
Spectrum
(dBFS)
Frequency (Hz)
-120
-100
-80
-60
-40
-20
0
10
7
10
8
10
9
Output
Power
Spectrum
(dBFS)
Frequency (Hz)
One-tone measurements
• Output power referenced to power in fundamental for a square-
wave at that frequency
• Performance not ideal; residual excess delay, latch latency
• Metastability and latch latency dominate at lower end of
spectrum
fin = 62.5 MHz; Pin = 3 dBm fin = 250 MHz; Pin = 3 dBm
FFT bin size = 61 kHz

43.
-120
-100
-80
-60
-40
-20
0
10
7
10
8
10
9
Output
Power
Spectrum
(dBFS)
Frequency (Hz)
SNR and # of bits of resolution
Signal
Frequency,
Hz
Equivalent
Sampling
rate, S/s
SNR,
dB
61 kHz
SNR,
dB
1 Hz
SNR,
dB
Nyquist
ENOB SNR,
dB
61 kHz
SNR,
dB
1 Hz
SNR,
dB
Nyquist
ENOB
6.25e7 1.25e8 85.37 133.23 55.3 8.89 87.54 135.39 57.4 9.25
1.25e8 2.5e8 81.3 129.16 48.2 7.71 84.8 132.65 51.7 8.29
2.5e8 5e8 70.7 118.56 34.6 5.45 76.3 124.15 40.2 6.38
Noise power measured at upper band edge Noise power integrated to signal frequency
For an equivalent
Nyquist-rate ADC, SNR
and effective # of bits of
resolution, ENOB, are
related by
ENOB = (SNR-1.76)/6.02

44.
Effect of latch latency on output spectrum
• Clock signal to RTZ-DAC delayed (relative to comparator) to
avoid glitches in DAC pulse
• If delay not optimum (probably the case), output spectrum not
ideal
-100
-80
-60
-40
-20
0
10
6
10
7
10
8
10
9
Output
Power
Spectrum
(dBFS)
Frequency (Hz)
RTZ DAC, 3ps clock delay
RTZ DAC, no clock delay
2.5001 2.5002 2.5003 2.5004 2.5005 2.5006 2.5007 2.5008 2.5009
2.5000 2.5010
-12
-10
-8
-6
-4
-2
0
2
4
6
8
10
12
-14
14
time, usec
I_dac.i,
mA
I_dac_bar.i,
mA
Spurious glitches if
clock not delayed

45.
Effect of comparator speed on noise-shaping
• Comparator speed increased by increasing bias current
• With a slower comparator, output spectrum is dominated by
metastability at frequencies < 150 MHz
• M-S latches 10:1 faster than clock rate for low metastability
-120
-100
-80
-60
-40
-20
0
10
7
10
8
10
9
Output
Power
Spectrum
(dBFS)
Frequency (Hz)
slower comparator
faster comparator

46.
Two-tone measurements
• Integrator bias current >> RTZ-DAC current to achieve linearity
in the input stage
• > 80 dBc suppression of intermodulation at lower bias
• Same voltage source for integrator, DAC and comparator; DAC
current increases much faster than Integrator bias current;
Intermodulation suppression degrades with increasing bias
-100
-80
-60
-40
-20
0
1.2 10
8
1.22 10
8
1.24 10
8
1.26 10
8
1.28 10
8
1.3 10
8
Output
Power
Spectrum
(dBFS)
Frequency (Hz)
-100
-80
-60
-40
-20
0
1.2 10
8
1.22 10
8
1.24 10
8
1.26 10
8
1.28 10
8
1.3 10
8
Output
Power
Spectrum
(dBFS)
Frequency (Hz)
Slower comparator – lower bias Faster comparator – higher bias
FFT bin size = 61 kHz

47.
Summary of Achievements
• Demonstrated a mesa-HBT technology for MSI ICs (200 GHz
ft, 200 GHz fmax HBT, microstrip wiring environment)
• Demonstrated a 87 GHz static frequency divider in the mesa-
HBT technology. Divider functional at all frequencies between 4
and 87 GHz
• Studied the effect of metastability errors and excess delay on
ADC performance and proposed circuit techniques to
circumvent the problems
• Demonstrated a 2nd order continuous-time S - D ADC clocked
at 8 GHz. ADC has 48 dB SNR at an OSR of 32.

48.
Future Work
With the self-aligned mesa-HBT process
• Yield still very low (only 2 out of 60 ADCs worked)
• Problems include base-emitter shorts and MIM capacitor
shorts
• Further scaling of device dimensions a considerable challenge
For reliably yielding high-speed MSI ICs
• non self-aligned process
• junctions formed by ion-implant and regrowth, rather than
mesa-etching
• planar Si/SiGe like HBT, consistent with MSI/LSI is needed