The 25th Annual SEMI Advanced Semiconductor Manufacturing Conference – ASMC 2014 May 19-21, 2014 Saratoga Hilton/City Center 534 Broadway Saratoga Springs, NY 12866 USA Tel: 1-518-584-4000 Fax: 1-518-584-7430

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The 25 Annual SEMI Advanced Semiconductor Manufacturing Conference – ASMC 2014
May 19-21, 2014 – Saratoga Hilton/City Center (Saratoga Springs, NY)
30Jan2013
Sunday, May 18, 2014
6:30-7:30
Registration
Monday, May 19, 2014
7:30-8:30
Registration
8:30
Welcome to the Conference (Israel Ne’eman, Applied Materials / Oliver Patterson, IBM) and 2013 Best Paper Awards
8:45
Keynote: Dr. Been-Jon Woo, Vice President, Business Development, Taiwan Semiconductor Manufacturing Company, Ltd.
Session 1: Yield Enhancement
Chairs: Larry Pulvirent, GLOBALFOUNDRIES; Raymond van Roijen, IBM
Characterization techniques for driving yield are critical for successful semiconductor
manufacturing. This session covers analysis of volume diagnostic data, an alternative
array design to SRAM as a yield learning vehicle and a case study on eliminating
a contact shorting mechanism.
Session 2 - Advanced Metrology I
Chairs: Sathish Veeraraghavan, KLA-Tencor; Alok Vaid, GLOBALFOUNDRIES
Novel processes and complex materials are putting significant pressure on measurement
tool-sets. Advanced metrology session that discusses novel applications and use-cases of
metrology techniques including ellipsometry, X-Ray, MBIR, to characterize various
advanced processes.
9:50
1.1 Successful Yield Ramp using Product Test, Scan and Memory Diagnosis
Venkatesan Muthumalai, David Iverson, Aaron Sinnott, Himanshu Joshi, Rao Desineni,
Ritesh Turakhia, Thomas Berndt, Nancy Bell, GLOBALFOUNDRIES
9:50
2.1 Silicon-Germanium (SiGe) Composition and Thickness
Determination via Simultaneous Small-spot XPS and XRF measurements
Benoit Lherron, Nicolas Loubet, Qing Liu, STMicroelectronics; Wei Ti Lee, Mark Klare,
Heath Pois, Mike Kwan, Ying Wang, Tom Larson, ReVera, Inc.; Saiqa Farhat, Jennifer
Fullam, John Gaudiello, Srinivasan Rangarajan, Bing Sun, IBM; Romain Wacquez, Sylvian
Maitrejean, Emmanuel Augendre, LETI
10:20
1.2 Tristate Inverter Array: A new test structure that compliments traditional SRAM arrays
as yield learning
Ishtiaq Ahsan, Fred Towler, Carl Schiller, Zhigong Song, Robert Wong, David Clark, Felix
Beaudoin, IBM Systems and Technology Group
10:45 Break
11:00
1.3 Novel Process Window and Product Yield Improvement by Eliminating Contact Shorts
Yuan-Chieh Chiu, Shih-Ping Hong, Fang-Hao Hsu, Hong-Ji Lee, Nan-Tzu Lian, Tahone
Yang, Kuang-Chao Chen and Chih-Yuan Lu, Macronix International
11:25
1.4 DiagBridge: Analyzing Scan Diagnosis Data in a Yield Perspective
Yan Pan, Atul Chittora, Kannan Sekar, Shobhit Malik, Lim Seng Keat,
GLOBALFOUNDRIES
11:50
1.5 The Importance of Reporting both Composite and Maze Yield for Process Split Yield
Learning
Fan Zheng, Amanda Piper, Yongchun Xin, Jang Sim, Jason J. Mazzotti, IBM
10:20
2.2 Benefit of Combining Metrology Techniques for Thin SiGe Layers
Delphine Le Cunff, T. Nguyen, R. Duru, F. Abbate, STMicroelectronics; N. Laurent, J.
Hoglund, SemiLab; F. Pernot, M. Wormington, Jordan Valley Semiconductors
10:45 Break
11:00
2.3 New Interferometric Measurement Technique For small Diameter TSV
Padraig Timoney, Daniel Fisher, Yeong-Uk Ko,, Alok Vaid, Sarasvathi Thangaraju,, Daniel
Smith, Himani Kamineni,, Dingyou Zhang, Ramakanth Alapati, Wonwoo Kim,
GLOBALFOUNDRIES; Ke Xiao, Holly Edmundson, Nigel Smith, Brennan Peterson,
Hemant Amin, Jonathan Peak,Timothy Johnson, Nanometrics
11:25
2.4 Broadband Spectroscopic Ellipsometry for cSiGe process control
Saiqa Farhat, Srinivasan Rangarajan, Timothy J. Mcardle, Michael Steigerwalt,
IBM; Dawei Hu, KLA-Tencor
11:50
2.5 MBIR Characterization of Photosensitive Polyimide in High Volume
Manufacturing
Taher E. Kagalwala, Yuri M. Brovman, Brian M. Erwin, Victoria L. Calero-DdelC, IBM;
Jonny Hoglund, SemiLab
12:15 Networking Lunch
1

2. Session 3 – 3D/TSV
Chairs: Sagar Kekare, KLA-Tencor; James Lu, RPI; Thuy Tran-Quinn, IBM
This session will cover key innovation in the field of 3D/Through-silicon via technology
(TSV) including TSV processing, wafer thinning, and metrology.
Session 4A – Advanced Process Control (APC )
Chairs: Agnes Roussy, EMSE; Philippe Campion, STMicroelectronics
Innovations for advanced process control, including prediction of
deposition rates,predictive maintenance and virtual metrology.
1:15
3.1 A Successful Void Free Gap Fill of 3µm, High AR Via Middle, Through Silicon Vias
at Wafer Level
S. Thangaraju, R. Alapati, D. Smith, A. Selsley, M. Wien, R.R. Giridharan, V.
Seshachalam, G. Kumarapuram, C. Wang, GLOBALFOUNDRIES
1:15
4.1 First Time Right Deposition of embedded SiGe in new Products
E. Harley, M. Linskey, A. Herbert, M. Fayaz, M. Brodfuehrer, A. Mocuta, M. Steigerwalt,
C. Snavely, IBM
1:40
3.2 Wafer Thinning for High-Density 3D-LSIs: 12 Inch Wafer-Level 3D-Integration at
GINTI
M. Murugesan, T. Fukushima, J.C. Bea, H. Hashimoto, Y. Sato, K.W. Lee
and M. Koyanagi, GINTI, Tohoku University; NICHe ohoku University
1:40
4.2 Addressing The Chamber Matching Lifecycle With Predictive
Maintenance, Equipment Health Monitoring, Virtual Metrology And Run-To-Run Control
James Moyne, Manjunath Yedatore, Jimmy Iskandar, Parris Hawkins, John Scoville,
Applied Materials
2:05
3.3 Use of Optical Metrology Techniques for Uniformity Control of 3D Stacked ICs
D. Le Cunff , M. Tardif , N. Hotellier, K. Le Chao, L.L. Chapelon, P. Bar, S. Eynard,
STMicroelectronics; J.P. Piel, G. Fresquet, Fogale Nanotech
2:05
4.3 FDC Run-to-Run Variation Monitoring for Sensor Level Diagnosis
in Tool Condition Hierarchy
Jakey Blue, Agnès Roussy, École des Mines de Saint Etienne; Jacques Pinaton,
STMicroelectronics
2:30 BREAK
2:30 BREAK
2:55
3.4 Analysis of TSV Geometric Parameter Impact on Switching Noise
Power Distribution Network
Huanyu He, J. -Q. Lu, Rensselaer Polytechnic Institute; Xiaoxiong Gu, IBM T.J. Watson
Research Center
Session 4B – Factory Optimization
Chairs: Dave Gross, GLOBALFOUNDRIES; Thomas Beeg, GLOBALFOUNDRIES
Semiconductor equipment and manufacturing is increasingly complex and driven by strict
economic constraints, making it essential for IC makers to maximize fab productivity and
efficiency. This session discusses new strategies and solutions to optimize fab layout,
production logistics, and equipment maintenance.
3:20
3.5 RF Characterization of Through Silicon Vias Test Structures in a 3-Tier Stacked
Wafer
Min Xu, Robert Carroll, Harika Manem, Robert Geer, College of Nanoscale Science and
Engineering, University at Albany, SUNY
3:45
3.6 3D Technology Applications Market Trends & Key Challenges
Thibault Buisson, Rozalia Beica, Yole Développement
2:55
4.4 300mm+ Factory Design and Innovations for Advanced
Semiconductor Manufacturing
Yih-Jan Huang, Chia-Yin Kuo, Ming-Te Kao, Rich Huang, Fiona Lee, Taiwan
Semiconductor Manufacturing Company
3:20
4.5 Emerging Challenges to Carrier Logistics
Jan Rothe, Gabriel Gaxiola,GLOBALFOUNDRIES; Terry Asakawa,Tokyo Electron Ltd.;
Kenji Yamagata, Daifuku; Makoto Yamamoto, Murata
3:45
4.6 Ipm- A Fab Preventative Maintenance Forecasting & Downtime Management Tool
Guy Senerman, Intel Corporation
4:30-5:30
Tutorial (DSA): Dr. Michael A. Guillorn, Research Staff Member/ Manager, Nanofabrication and Electron Beam Lithography
T. J. Watson Research, IBM
2

3. Monday, May 19, 2014 - 5:30-7:30
Session 5 - Poster Session
Chairs: Alan Brightman, Edwards Vacuum; Russell Dover, Lam Research; Eric Eisenbraun, CNSE; Larry Hennessy, CHM2 Hill; Dick James, Chipworks; Jason J. Mazzotti, IBM;
Kazunori Nemoto, Hitachi High Tech; Jan Rothe, GLOBALFOUNDRIES; Patrick Varekamp, IBM; Naomi Yoshida, Applied Materials
3D ICs in the Real World (3D)
Dick James, Chipworks
Accelerated technology development by the use of Critical Point Inspection SEM
Dominique Sanchez , Remi Le Tiec, Benoit Hinshberger, STMicroelectronics; Loemba Bouckou, Olivier Moreau,
Paolo Parisi, KLA-Tencor
Advancement of Microelectronics-Grade Carbon Nanotube Materials for NRAM® Device Manufacture
James E. Lamb III, Stephen Gibbons, Yongqing Jiang, Kay Mangelson, Kathryn Kremer, Dan Janzen, John
Bledsoe, Mathew Boeser, Brewer Science
Challenges in Atomistic Doping Profiling Using Capacitance-Voltage Measurements
Petru Andrei, Samira Aghaei, Mohit Mehta, Florida State University; Mark J. Hagmann, NewPath Research
Correlation Study of spatial ESC temperature profile and optical CD measurements
Marcus Wollenweber, Robert Melzer, Giampietro Bieli, John Newby, KLA-Tencor;Thomas Nogatz, Joerg Sobek
GLOBALFOUNDRIES
Correlation Study of White Light Interferometer Measurements with Atomic Force Microscope Measurements for
Post-CMP dishing Measurements Applied to TSV Processing
Daniel Fisher, Padraig Timoney, Yeong-Uk Ko, Alok Vaid, Sarasvathi Thangaraju, Daniel Smith, Sung Pyo Jung,
Ramakanth Alapati, Wonwoo Kim, GLOBALFOUNDRIES; Hemant Amin, Jonathan Peak, Tim Johnson,
Nanometrics
Defect Engineering for Carrier Lifetime Control in High Voltage GaAs Power Diodes
Vladimir A. Kozlov, FID-Technology Ltd.; F.Yu. Soldatenkov, Power Semiconductors Ltd.; I.L. Shulpina,V.G.
Danilchenko, V.I.Korolkov, Ioffe Institute of RAS
Early Detection of Pattern Defect on ADI Wafer
Robert A Teagle, Frank Wilhelm Mont, GLOBALFOUNDRIES;Erin C Mclellan, Nicole Saulnier, Carol Boye,
Dong-Ryul Lee, IBM; Fei Wang, HungYu Tien, Amy Chiang, Hermes-Microvision
The Effect of H3PO4 Processing on Power DMOS Gate Oxide Integrity in Poly Buffered LOCOS Isolation
Tan Chan Lik, Cheng Chin Siong, Ng Cheah Ling, Infineon Malaysia
Effective Testing for Wafer Reject Minimization by Terahertz Analysis and Sub-Surface Imaging
Anis Rahman, Applied Research & Photonics
Evaluation of FKM/PTFE Hybrid Material Seal
Ippei Nakagawa, Nippon Valqua Industries, Ltd
Fluorine interaction on SICN and SIOC layers detected by fault detection
Jean-Rene Raguet, Laurent Blaya, STMicroelectronics
FOUP Purge with Diffusers for FOUP Door
Seong Chan Kim, Bo Liu, Entegris
Hidden Equipment Productivity Opportunities
Jochen Kinauer, AIS Automation
Highly-stable Four-Point-Probe Metrology in Implant and Epitaxy Processes
Franz Heider, Walter Petersmann, Martin Haberjahn,Infineon; Qing Ye, Jianli Cui, Lu Yu, Tetyana Shapoval,
Florian Flach Ronny Haupt, KLA-Tencor
Improvement of Characteristic of Redistribution Layer (RDL ) on Mobile Application
C.S. Liu, Ann Hsu, C.T. Ni, Ponder Pang, Justin Lo, Wallace Su, Harry Ku, Taiwan Semiconductor Manufacturing
Company
Improving Yield through Elimination of Nitride Stringers in 180nm EEPROM Process Technology
Moshe Agam, Santosh Menon, Sorin Georgescu, Roger Young, Peter Cosmin, ON Semiconductor
Modeling the Impact of Supply Contract Modifications in Mid -term Master Planning of Semiconductor
Manufacturing (Student)
Marwa Attiya, Dr. Ali Diabat, Dr. Irfan Saadat, Masdar Institute of Science and Technology
Mueller Matrix Optical Scatterometry of Directed Self-Assembly Block Copolymer Line Arrays (PS-b-PMMA)
(student)
Dhairya J. Dixit, Alain C. Diebold, CNSE; Vimal Kaminen, Richard Farrell, Erik Hosler, Moshe Preil,
GLOBALFOUNDRIES, Joe Race, Brennan Peterson, Nanometrics
Multivariate Method for the Monitoring of Etch Chamber Insitu Cleaning
Suradej Promreuk, Freescale, Inc.
Novel Metrology and Wafer Grinder Technologies Combine for Improved Capability
Russ Dudley, Thomas Brake, David Grant, Bill Kalenian, Michael Kirkpatrick, David Marx, Rajiv Roy, Rudolph
Technologies
Optical Technologies for TSV Inspection
Arun A. Aiyer, Nikolai Maltsev, Jae Ryu, Frontier Semiconductor
People Productivity Improvement via Cloud Machine Monitor
Y.H. Chen, C.J. Huang, C.L. Wang, Taiwan Semiconductor Manufacturing Company
Rethinking the Approach to Higher 450mm Process Gas Flows: A Case Study
William Corbin, Adrienne Pierce, Edwards Vacuum
Scanning frequency comb microscopy (SFCM): A new method showing promise for high-resolution dopant
profiling in semiconductors
Mark Hagmann,Shashank Pandey, Ajay Nahata, University of Utah; Petru Andrei, Florida State University
Screen Printed Flexible Sensors Electronic Skin
Saleem Khan,University of Trento; R. S. Dahiya, Unversity of Glasgow; L. Lorenzelli, Fondazione Bruno Kessler
Short-Interval Scheduling of Litho Area with Ezdfs
Myoungsoo Ham, Siyoung Cho, Liberty University
Six Sigma in a Semiconductor Company
Karen D. Riding, Michael J. Cifaratta; Dirk Alexander Bruedern, GLOBALFOUNDRIES
Smart Feature Selection Development for advanced Virtual Metrology
Benjamin Lenz, Bernd Barak, Julia Mührwald, Infineon; Carolin Leicht, Eberhard-Karls University Tuebingen
Surface Metal Contamination on Tool Components – a Case Study for Evaluating Acid Extraction ICP-MS
Measurement Process (CFM) Shi Liu, Bin Liu, ChemTrace
Trench Multiplication Process by a sacrificial SiGe Epitaxial Layer
Thomas Popp, Rudolf Berger, Stefan Pompl, Infineon Technologies AG
Uniformity Control for High Selective DownFlow Plasma Etching on Silicon Oxide
Fang-Hao Hsu, Kuo-Feng Lo, Xin-Guan Lin, Yuan-Chieh Chiu, Hong-Ji Lee, Nan-Tzu Lian, Tahone Yang,
Kuang-Chao Chen and Chih-Yuan Lu, Macronix
Using in-line Film Measurement as a Proxy for Device Matching to Speed up Process Change Qualification
Chienfan Yu, Shailesh Shah, Eric Woodard, Raymond Van Roijen, Javier Ayala, Edward Sziklas, IBM
3

4. The 25th Annual SEMI Advanced Semiconductor Manufacturing Conference - ASMC 2014
Tuesday, May 20, 2014 (Day Two)
7:30-8:00 Registration
8:00-9:00 Keynote: (Invited) Naga Chandrasekaran, Vice President, Process Research and Development, Micron
Session 6 - Advanced Metrology II
Chairs: Alok Vaid, GLOBALFOUNDRIES; Amiad Conley, Applied Materials
Novel processes and complex materials are putting significant pressure on
measurement tool-sets. The advanced metrology session that covers novel applications
and implementation of metrology techniques including CD-SEM, Kelvin Probe, CV probe
to characterize various advanced processes.
Session 7 – Defect Inspection I
Chairs: Jeanne Bickford, IBM; Jeff Barnum, KLA-Tencor
Defect inspection is integral to the development and manufacture of semiconductor
devices. This session will feature papers describing various optical techniques to detect
defects in advanced designs and materials, including 2x nm CMOS, 3D NAND, and IIIV epitaxial layer growth.
9:05
6.1 CD-SEM Metrology Evaluation of Gate-All-Around Si Nanowire MOSFET with
Improved Control of Nanowire Suspension by Using a Buried Boron Nitride Etch-Stop
Layer
Shimon Levi, Ori Shoval, Ofer Adan, Maayan Bar Tzi, Amiad Conley, Applied Materials;
Guy M. Cohen, Leathen Shi, Sarunya Bangsaruntip, Alfred Grill, Deborah Neumayer,
IBM T.J. Watson Research Center
9:05
7.1 Advanced Optical Inspection Methodologies for Discovery and Monitoring of YieldKiller Defects at 2x nm Design Nodes
Abhishek Vikram, Peter Lin, Aleister Mraz, Victor Lim, GLOBALFOUNDRIES; Ravi
Sanapala2, Rahul Lakhawat, Ankit Jain, Sumanth Kini, Satya Kurada, KLA-Tencor
9:30
6.2 Air Gap CV Measurement for Doping Concentration in Epitaxial Silicon
Franz Heider and Johannes Baumgartl, Infineon Technologies; Peter Horvath, Thomas
Jährling, Semilab
9:30
7.2 A Novel Approach for improving the Inspection Sensitivity using Design
Context information
Young Su Kim, Chul Woo Kim, Jong Tae Won, Kwang Il Shin, Ki Ho KIM, Jin Woo Kim,
Samsung Electronics Co. Ltd; Satya Kurada, Mingwei Li, Raghav Babulnath,
Gangadharan Sivaraman, KLA-Tencor
9:55 Break
9:55 Break
10:15
6.3 Addressing Thin Film Thickness Metrology Challenges of 14nm BEOL Layers
Alok Vaid, Michael Lenahan,GLOBALFOUNDRIES; Zhiming Jiang, Ronny
Haupt, Carlos Ygartua, KLA-Tencor
10:15
7.3 Detection Sensitivity Improvement in Key Layers in the STI and Via Modules in 28
nm process foundry logic node
Dan Koronel , Govinda Soni, Vijeet Gupta, Mirko Beyer, Applied Materials
10:40
6.4 Assessment of Minority-Alloy Component Segregation (e.g. Mn , Al) in Back End of
Line Copper Trench Structures Using Kelvin Probe Technique
Joyeeta Nag, Shishir Ray, Felipe Tijiwa-Birk, GLOBALFOUNDRIES;Kriti Kohli, Andrew
Simon, Siddarth Krishnan, Christopher Parks, IBM
10:40
7.4 Investigation of Novel Inspection Capability for 3D NAND Device Wordline
Inspection
Soon Kyu Lee, Seong-Min Ma, IlSeok Seo, Hyeon Sang Shin, Hyeon Soo Kim,
SK Hynix; Andrew Cross, Oksen Baris, DoOh Kim, Steve Lange, KLA-Tencor
11:05
6.5 450mm Metrology and Inspection: The Current State and the Road Ahead
Rand Cottle, CNSE, Katherine Sieg, Intel Corporation; Nithin Yathapu,
GLOBALFOUNDRIES; Jeffrey Lee, Taiwan Semiconductor Manufacturing Corporation
11:05
7.5 Progress on background signal analysis of bare wafer inspection systems based
on light scattering for III/V epitaxial layer growth monitoring
Sandip Halder, Yves Mols, Dieter van den Heuvel, Jan van Puymbroeck, Matty
Caymax, Eric Vancoille, Nancy Nieuborg, imec; Gerhard Bast, Gavin Simpson, Milko
Peikert, Marco Polli, Seong Ho Yoo, KLA-Tencor
11:30 Boxed Lunch
11:30 Boxed Lunch
4

5. Session 8 – Equipment Reliability and Productivity Enhancement
Chairs: Stefan Radloff, Intel Corporation; Gary Green, Alphray; Adrienne Pierce,
Edwards Vacuum
The challenges of current and future semiconductor process technologies require a
higher level of equipment reliability, quality, repeatability and productivity. Optimizing
equipment performance will help improve fab metrics, minimize wafer costs and
maximize competitiveness. Papers in this session will review ideas and successes which
helped optimize equipment utilization and tool performance.
12:00
8.1 Implementation of an Advanced Recipe Management System in a 28 nm Fab
Andrew Lu, Jeff Hanan, Kevin Drinkwine, GLOBALFOUNDRIES Andreas Weber,
Matthias Hanisch, Dan Cogut, Vrunda Bhagwat, camLine; Robert Sinn, Gary Green,
Alphray
12:25
8.2 - Study of Central Supply Methodology for Silica-Based CMP Slurry
CN Chang, SS Lien, HC Hsiao, KT Tsai, JP Yu, Taiwan Semiconductor Manufacturing
Company
12:50
8.3 Extending Dry Pump Reliability on High-k ALD Furnaces
Kastumi Nishimura, Maiku Boger, Edwards Japan, Ltd.
1:15
8.4 Laser Marking Equipment Process & Productivity $0 Improvement
Darin Moreira, Anthony Vincent, Intel Technology (M) Sdn Bhd; Bhuvenesh
Rajamony, University Malaysia Perlis UNIMAP
Session 9 - Contamination Free Manufacturing (CFM)
Chairs: Chris Long, IBM; Matt Wagner, Pall
Contamination Free Manufacturing: Control of the local wafer environment is vital to achieving
critical rapid yield ramps. This session will feature papers focused on next generation carriers,
wafer edge defectivity mitigation, and environment control.
12:00
9.1 450mm Carrier Interoperability Effects on Particle Generation
Angelo Alaestante, G450C (Intel assignee; Christopher Borst, G450C (SUNY College of
Nanoscale Science and Engineering assignee)
12:25
9.2 A study on the Defect induced by Ambient Moisture and Ammonia During
Perhydropolysilazane Spin on Glass Process
Jeongin Yoon, Jinho Kim, Juhyun Park, Joonho Jang, Kwangshin Lim, Jongsu Kim, Samsung
12:50
9.3 Surface treatment against bromine defectivity in plasma etch reactor
Yoann Goasduff, Patrice Laurens, Marylaine Nguyen, STMicroelectronics;
Giuseppe Distefano, Lam Research Corporation
1:15
9.4 Optimized BARC Films and Etch Byproduct Removal For Wafer Edge Defectivity Reduction
Mohamad Boumerzoug, Freescale, Inc.
1:40 BREAK
1:40 BREAK
5

6. Session 10 – Data and Yield Management
Chairs: Franz Heider, Infineon; Dieter Rathei, D R Yield
Semiconductor engineers are continuously striving to improve data capture and analysis
techniques to speed up yield ramps and extract the last possible yield in the fab. In this
session, we explore hard and soft SRAM bit fail analyses for faster ramp, yield
optimization using scribe referencing and advanced data mining techniques for
consumables.
2:00
10.1 Integrated System for Consumable Yield Analysis
Zhuqing Zong, Ute Nehring, GLOBALFOUNDRIES
2:25
10.2 Methodology of Utilizing Inline Defect Data Overlay to SRAM Bitmap Failure and
Logic Diagnostics for Fast Yield Ramp in Limited Engineering Resources
Venkatesan Muthumalai, Yoong Ern Ling, Ryan Lockwood, Ryan Ross, Robert Schkade,
Christian Hobert, GLOBALFOUNDRIES; Michael Wu, Steve White, Synopsys
2:50
10.3 Line Centering Yield Optimization Method
Jeanne Paulette Bickford, Erik Hedberg, Kevin Dezfulian, Troy Perry, IBM
3:15
10.4 Advanced Soft Fail Characterization Methodology for Sub-28nm
Nanoscale SRAM Yield Improvement
Jianhua Yin, Sherwin Fernandes, Yinzhe Ma, Sheng Xie, Xuemei Liu, Qiushi Wang,
Mark Dexter, Meixiong Zhao, Randy Mann, Chong Khiam Oh, Mark Tay, Seng
Keat Lim, Dapeng Sun, Paulo Chao, Jeffrey Lam, GLOBALFOUNDRIES
Session 11 - Discrete Power Devices/Emerging Technologies
Chairs: George Kong, Peregrine Semiconductor; Rob Pearson, Rochester Institute of
Technology
Emerging Technologies must address trades offs and challenges to solve problems such
as power density, communication and integration. This session presents improvements
and potentially disruptive technologies in power device parametrics, photonic integration
with CMOS, discrete semiconductor and novel material characterization which address
these challenges.
2:00
11.1 Impact of High Voltage LDMOS process added to a 0.18um CMOS flow (ET)
Moshe Agam, Tracy Myers, Agajan Suwhanov, Yutaka Ota, Sallie Hose, Thierry Yao, Matt
Comard, ON Semiconductor
2:25
11.2 Improved Deep Body Implant on Breakdown Voltage in Super Junction of Vertical
DMOS Transistors
Tan Chan Lik, Marc Strasser, Infineon
2:50
11.3 Plasma-Assisted Printing and Doping Processes for
Manufacturing Few-Layer MoS2-Based Electronic and
Optoelectronic Devices
Xiaogan Liang, Hongsuk Nam, Sungjin Wi, Mikai Chen, University of Michigan
3:15
11.4 Challenges for Photonics Integration in a CMOS Foundry
Thomas N. Adam, Gerald Leake, Douglas Coolbaugh, College of Nanoscale Science and
Engineering; Michael Watts, Massachusetts Institute of Technology
3:40 Break
3:40 Break
4:00-5:30 Panel Discussion
‘25 Years of Semiconductor Manufacturing: Accomplishments, Current Challenges, Future Directions - From the Internet to the Internet of Things’
Moderator: Paul Werbaneth, 3D InCites
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Daniel Armbrust, Chief Executive Officer, SEMATECH
Lynn Fuller, Professor, Microelectronics Dept., Rochester Institute of Technology
Dave Gross, Director, Manufacturing Systems Technology, GLOBALFOUNDRIES
William Miller, Sr. Director of Engineering, Qualcomm (invited)
Charlie Pappis, Group VP, General Manager, Applied Global Systems, Applied Materials
6:00-7:30
Saratoga Reception
6

7. 25th Annual IEEE/SEMI Advanced Semiconductor Manufacturing Conference - ASMC 2014
Wednesday, May 21, 2014 (Day Three)
7:30-8:00
Registration
8:00-9:00
Tutorial (Silicon Photonics): Dr. Haisheng Rong, Sr. Research Scientist, Intel Corporation
Session 12 - Advanced Patterning/DFM
Chairs: Jacek Tyminski, Nikon Research; Anton deVilliers, Tokyo Electron
Advanced patterning and design for manufacturing (DFM) are key elements of leading
edge semiconductor fabrication. This session covers innovations in improving double
patterning, in DSA metrology, and in a DFM methodology exploring how local proximity
can affect device performance.
9:05
12.1 Environment Dependence of Analog Matching and Improvement
through Design and Process Optimization on a 28LP SoC Technology for
Smart Mobile Devices
M. Cai, S. Sengupta, J. Choi, W. Qi, H. Wang, V. Huang, D. Alladi, D. Yuan, PR.
Chidambaram, G. Yeap, Qualcomm
9:30
12.2 Incorporation of Direct Current Superposition (DCS) as a Means
for High Quality Contact and Slotted Contact Structures utilizing Lith-FreezeLitho-Etch (LFLE)
Jeffrey Smith, Anton deVilliers, Nihar Mohanty, Tokyo Electron Technology Center
Session 13 – Advanced Equipment and Materials I
Chairs: Russell Dover, Lam Research; Brett Williams, ON Semiconductor
Advanced memory, analog and logic manufacturers face daunting challenges as the
next generation device nodes come on line. These challenges are being met by the
development and applications of innovations in equipment, materials, and processes.
This session will focus on and will highlight some of the latest innovations that are being
implemented in leading edge high volume manufacturing.
9:05
13.1 The Effect of Backside Roughness on Al Interconnect Dimensions
for RF CMOS SOI Devices
Shawn Adderly, Jeffrey Gambino, Matthew Moon, Jeff Hanrahan, IBM
9:30
13.2 Improvement for 200 mm APCVD Epitaxial Si Films Enabled by
Retrofit of Applied Materials Epi Centura
Matthias Künle, Johannes Baumgartl, Infineon Technologies; Thomas Ackermann
Applied Materials
9:55
12.3 Advanced Lithography Process Control Strategies
Prashant Aji, Wing-Shan Ribi Leung, Catherine Perry-Sullivan, KLA-Tencor
9:55
13.3 A New Systematic Approach for Etch Chamber Matching To Meet
Leading Edge Requirements
Stephen Hwang, Lam Research Corporation
10:20 Break
10:20 Break
7

8. Session 14 – Defect Inspection II
Chairs: Jennifer Braggin, Entegris; Anand Subramani, KLA-Tencor
Defect inspection is integral to the development and manufacture of semiconductor
devices. This session will feature papers describing new ways to utilize e-beam and
bare wafer inspection data while leveraging complementary defect inspection
techniques.
10:35
14.1 Full-Wafer Electron Beam Inspection
Richard Hafer, Oliver D. Patterson, IBM; Roland Hahn, Hong Xiao; KLA-Tencor
11:00
14.2 High-K Metal Gate Contact Process Optimization for Yield
Improvement via Innovative Defect Inspection Technique
Polly Lan, Chang I Lin, Charles CY Tsai, Jung Yan Yang, Garry Chen, White Pai,
United Microelectronics Corporation
11:25
14.3 Sub-threshold Defect Detection using Advanced Inspection Methodology
Sandeep Gaan, ZhiGuo Sun, Sipeng Gu, Yang Bum Lee, GLOBALFOUNDRIES;
Chandar Palamadai, Joey Li, Lingyan Zhao, Lucy Fan, KLA-Tencor
11:50
14.4 Use of Diodes to Enable mLoop® Test Structures for Buried Defects and Voltage
to Intensity Calibration
Oliver Patterson, IBM
Session 15 - Advanced Equipment and Materials II
Chairs: Holly Magoon, Nikon; Scott Lantz, Intel Corporation
Advanced memory, analog and logic manufacturers face daunting challenges as the
next generation device nodes come on line. These challenges are bei ng met by the
development and applications of innovations in equipment, materials, and processes.
This session will focus on and will highlight some of the latest innovations that are being
implemented in leading edge high volume manufacturing.
10:35
15.1 Comparison Study Between Optical Emission Spectroscopy and XRay Photoelectron Spectroscopy Techniques During Process Etch Plasma
M. Rizquez, Y.Goasduff, A.Roussy, Ecole des Mines de Saint Etienne; J. Pinaton,
A. James STMicroelectronics
11:00
15.2 Etch Planarization – A New Way of Correcting Post CMP Non-Uniformity
Meihua Shen, Baosuo Zhou, Yifeng Zhou, John Hoang, Andrew Bailey, Eric Pape,
Harmeet Singh, Lam Research Corporation
11:25
15.3 CMP Solution for Enabling STT-RAM Fabrication using Via-less Process Flow
Sajjad Hassan, Mahendra Pakala, Motoyo Okazaki, Garrett Sin, Applied Materials
11:50
15.4 High-k/Metal Gates in the 2010s
Dick James, Chipworks
12:30 Keynote:
From Germanium, to Gallium Arsenide, to Silicon and back again: a Perspective
on the Semiconductor Manufacturing Industry
Dean Freeman, Vice President of Research, Gartner
1:15 Closing Remarks
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