1. INTRODUCCIÓN A VERILOG Objetivos comprender el uso de un HDL en el diseño de sistemas digitales estudiar Verilog como Lenguaje de Descripción de Hardware (HDL)
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3. SÍNTESIS AL NIVEL DE TRANSFERENCIA ENTRE REGISTROS Simulación Lógica Arquitectura RT Circuito Lógico Posicionamiento Interconexión Síntesis RT-Lógica Implementación Retroanotación Simulación RT Optimización aritmética Identificación de elementos de memoria Codificación de tipos Extracción de las funciones lógicas Minimización Lógica
4. NIVELES DE ABSTRACCIÓN Modelo de Computación: Tiempo discreto Señal transición activa de la señal de reloj Señal t Simulación RT
5. NIVELES DE ABSTRACCIÓN Modelo de Computación: eventos discretos Simulación dirigida por eventos Simulación Lógica Señal t Señal t transición activa de la señal de reloj Simulación RT
6. NIVELES DE ABSTRACCIÓN ventana de comparación corrección del diseño valores compatibles Simulación Lógica Señal t Señal t transición activa de la señal de reloj Simulación RT Señal t Simulación Lógica retroanotada transición activa de la señal de reloj tiempo de ‘ set-up’ periodo de reloj - tiempo de ‘set-up’ camino crítico ‘ X’ ‘ 1’ ‘ 1’
7. SISTEMA DIGITAL A NIVEL RT Entradas de Control Entradas de Datos Salidas de Control Señales de Control Señales de Estatus Salidas de Datos Unidad de Control Unidad de Datos
8. SISTEMA DIGITAL A NIVEL RT Lógica Combinacional de Control Registro de Estado reloj reset set Estado de Control próximo Estado de Control actual Salidas de Control Entradas de Control Señales de Control Señales de Estatus Lógica Combinacional y Unidades Operacionales Registros de Datos reloj reset set Datos próximos Valores actuales en registros Salidas de Datos Entradas de Datos
9. VALORES LÓGICOS Interpretación en modelado y síntesis ‘ don’t care’ desconocido x tri-estado (‘don’t care’ en sentencias ‘case’) tri-estado z (?) ‘ 1’ lógico ‘ 1’ lógico 1 ‘ 0’ lógico ‘ 0’ lógico 0 síntesis simulación
11. TIPOS DE DATOS Nodos de red (‘net data types’) wire Ax; // línea de un ‘bit’ wire [4:0] Dak; // agrupación de 5 líneas wire línea tri idéntico a ‘wire’ (sólo informa de múltiples drivers) supply0 y supply1 ‘ 0’ ‘ 1’
12. TIPOS DE DATOS Nodos de red (‘net data types’) wire Error BpW Wait Valid Clear module Ejemplo (BpW, Error, Wait, Valid, Clear); input Error, Wait, Valid, Clear; output BpW; wire BpW; assign BpW = Error&Wait; endmodule Ejemplo
17. TIPOS DE DATOS Nodos de red (‘net data types’) wand Error BpW Wait Valid Clear module Ejemplo (BpW, Error, Wait, Valid, Clear); input Error, Wait, Valid, Clear; output BpW; wand BpW; assign BpW = Error&Wait; assign BpW = Valid | Clear; endmodule
18. TIPOS DE DATOS Registros reg Ax; // registro de un ‘bit’ reg [4:0] Dak; // registro de 5 ‘bits’ reg integer registros de hasta 32 ‘bits’ en complemento-2 la herramienta de síntesis debe sintetizar el tamaño mínimo wire [1:5] Brq, Rbu; integer Arb; . . . Arb = Brq + Rbu; . . . 6 + Brq Rbu Arb 5 5
19. TIPOS DE DATOS Constantes 30 -2 decimal simple 32 ‘bits’ en complemento-2 formato con base 2’b10 6’d-4 ’d-10 [size]’base value base=h,H,o,O,b,B,d,D
20. TIPOS DE DATOS Parámetros constantes nominales parameter RED = -1, GREEN = 2; // constantes decimales (32 bits en complemento-2) parameter READY = 2’b01, BUSY = 2’b11, EXIT = 2’b10; // constantes de 2 ‘bits’
29. SENTENCIAS DE ASIGNACIÓN Asignación procesal las asignaciones dobles a un mismo objeto son un error Count <= Preset + 1; . . . Count = Mask; los retrasos se ignoran #5 Count <= Preset + 1; . . . Count = #5 Mask; retrasos ignorados en síntesis
30. OPERADORES Operadores lógicos expresiones de conmutación module FullAdder (A, B, Carryin, Sum, Carryout); input A, B, Carryin; output Sum, Carryout; assign Sum = (A ^ B) ^ Carryin; assign Carryout = (A & B) | (B & Carryin) | (A & Carryin); endmodule xor ^ or | and & complemento ~ A B Carryin Carryout Sum
47. COMPORTAMIENTO COMBINACIONAL descripción de comportamiento código secuencial Sentencia ‘always’ module EvenParity (A, B, C, D, Z); input A, B, C, D; output Z; reg Z, Temp1, Temp2; always @ (A or B or C or D) begin Temp1 = A ^ B; Temp2 = C ^ D; Z = Temp1 ^ Temp2; end endmodule Z A B C D
48. lista de sensibilidad lógica combinacional Sentencia ‘always’ module EvenParity (A, B, C, D, Z); input A, B, C, D; output Z; reg Z; always @ (A or B) begin Z = A ^ B ^ C ^ D; end endmodule COMPORTAMIENTO COMBINACIONAL Z A B C D
49. Condición COMPORTAMIENTO COMBINACIONAL module Condition (StartXM, ShiftVal, Reset, StopXM); input StartXM, ShiftVal, Reset; output StopXM; reg StopXM; always @ (StartXM or ShiftVal or Reset) begin if (Reset) StopXM = StartXM | ShiftVal ; else StopXM = StartXM ^ ShiftVal ; end endmodule 1 0 StartXM ShiftVal Reset StopXM
50. Selección COMPORTAMIENTO COMBINACIONAL module ALU (Op, A, B, Z); input [1:2] Op; input [0:1] A, B; output [0:1] Z; reg [0:1] Z; parameter ADD = 'b00, SUB = 'b01, MUL = 'b10, AND = 'b11; always @ (Op or A or B) begin case (Op) ADD: Z = A + B; SUB: Z = A - B; MUL: Z = A * B; DIV: Z = A / B; endcase endmodule A Z B +/- * Op[1] Op[2] 00 01 10 11
59. Condición LÓGICA COMBINACIONAL toda señal o variable o es asignada bajo cualquier condición de ejecución del proceso, o es utilizada después de ser asignada module NonCombinationalLogic (A, B, C, Z); input A, B, C; output Z; reg Z; always @ (A or B or C) begin : VAR_LABEL reg D; if (! A) Z = D; else begin D = B & C; Z = 1; end end endmodule module NonCombinationalLogic (A, B, C, Z); input A, B, C; output Z; reg Z; always @ (A or B or C) begin : VAR_LABEL reg D; D = B & C; if (! A) Z = D; end endmodule
60. COMPORTAMIENTO COMBINACIONAL module DeMultiplexer (Address, Data, Line); input [1:0] Address; input Data; output [3:0] Line; reg [3:0] Line; integer J; always @ (Address) for (J = 3; J >= 0; J = J – 1) if (Address == J) Line[J] = Data; endmodule Condición toda señal o variable o es asignada bajo cualquier condición de ejecución del proceso, o es utilizada después de ser asignada
61. Condición LÓGICA COMBINACIONAL toda señal o variable o es asignada bajo cualquier condición de ejecución del proceso, o es utilizada después de ser asignada module CombinationalLogic (A, B, C, Z); input A, B, C; output Z; reg Z; always @ (A or B or C) begin : VAR_LABEL reg D; if (! A) Z = 1; else begin D = B & C; Z = D; end end endmodule B C A Z
62. Condición LÓGICA COMBINACIONAL toda señal o variable o es asignada bajo cualquier condición de ejecución del proceso, o es utilizada después de ser asignada module CombinationalLogic (A, B, C); input A, B, C; output Z; reg Z; always @ (A or B or C) begin : VAR_LABEL reg D; D = B & C; if (! A) Z = D; else Z = 1; end endmodule B C A Z
63. Tareas LÓGICA COMBINACIONAL encapsulado de lógica combinacional module FunctionCall (XBC, DataIn); input [0:5] DataIn; output [0:2] XBC; reg [0:2] XBCTemp; task CountOnes; input [0:5] A; output [0:2] B; integer K; begin B = 0; for (K = 0; K <= 5; K = K+1) if (A[K]) B = B + 1; end ; endtask always @ (DataIn) CountOnes(DataIn, XBCTemp); assign XBC = XBCTemp; endmodule + + + DataIn[0] DataIn[1] DataIn[2] DataIn[3] DataIn[4] DataIn[5] XBC
Notas del editor
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
[This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages