A 4-bit down counter is used to generate a 1 Hz pulse from a 10 Hz clock. At each positive clock edge, the counter state is evaluated. At the first 3 clock edges, the counter remains in the wait state with an output of 0. At the 4th clock edge, the counter transitions to state K1 with an output of 1. At the 5th clock edge, the counter transitions to state K2 with an output of 0.