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YOLE DEVELOPPEMENT
FROM TECHNOLOGIES TO MARKET
COLLABORATION
INNOVATION
NEW PERSPECTIVES
Advanced Packaging Role after Moore’s Law
Transition from Technology Node Era to Functionality Era
13 January 2016
Rozalia Beica

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 AP Growth
Presentation Outline
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From TECHNOLOGIES to MARKET
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• Europea
n Market
 AP Platforms
 WLCSP
 Conclusions
 Flip-Chip
 Fan-Out
 2.5D & 3D-IC
 Market Drivers
 Evolution
 Platforms
 Computing Trends

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YOLE DEVELOPPEMENT
Introduction
YOLE DEVELOPPEMENT
FROM TECHNOLOGIES TO MARKET
Founded in 1998 in Lyon, France
Introduction

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Yole – A Group of Companies
The company is involved in the following areas:
From TECHNOLOGIES to MARKET
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Finance
MEMS & Sensors Microfluidics & Bio Tech
Photovoltaics LED & Compound Semi Materials
Advanced Packaging
Photonics Power Electronics Equipment
Rev. Eng./Costing
Intellectual PropertyMarket, technology & strategy consulting
Manufacturing costs analysis
Reverse engineering
M&A operations
Due diligences
IP Analysis
Patent Assessment
Fundraising
Maturation of companies
IP Portfolio Management
Innovation Mgmt.

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Providing:
 market analysis
 technology evaluation
 strategic analysis
 business plan
 finance
 ….
Consultancy
across multiple
fields
and entire value
chain
Serving the Entire Value Chain across Multiple Fields
Non-exhaustive list of clients
From TECHNOLOGIES to MARKET
Copyright @ Yole Developpement SA.. All rights reserved
Transportation
makers
Mobile &
consumer
electronics
Automotive Medical
systems
Industrial &
defense
Energy
From A to Z…

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Providing:
 market analysis
 technology evaluation
 strategic analysis
 business plan
 finance
 ….
Consultancy
across multiple
fields
and entire value
chain
Serving the Entire Value Chain across Multiple Fields
Non-exhaustive list of clients
From TECHNOLOGIES to MARKET
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Integrators
and end-
users
Device
makers
OSAT,
foundries…
R&D centers
Financial
Investores
etc.
Suppliers:
Equipment &
Materials

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Yole’s research is focused on:
 Applicative Packaging: moving to high performance, low cost, application driven
packaging techniques
 Advanced Packaging: moving to high performance, low cost, collective wafer
level packaging techniques
Semiconductor Packaging
Camera Level Packaging Power Module Packaging MEMS Packaging LED Packaging
Lead-Frame LCC Wirebonding BGA WLCSP 3D WLP SIP 3DIC
QFN PGA Flip Chip POP FOWLP 2.5D Interposer
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From TECHNOLOGIES to MARKET
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8 Increased integration and flexible packaging solutions
 Increased volumes
 Growing applications
 More users
Computing Trends
New Major Technology Cycles
10x More Users, Devices
 Increased performance
 Smaller form factor
 Increased functionality
 Reduced cost
Mainframe
Mini-computers
PCs
Desktop internet
Mobile Internet
Internet of Things
1MM+
10MM+
100MM+
1Bill+
10Bill+
10Bill+
1960 1970 1980 1990 2000 2010 2020 2030 2040…

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From TECHNOLOGIES to MARKET
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http://ec.europa.eu/digital-agenda/en/about-mobility
The Driving Forces are Changing
From TECHNOLOGIES to MARKET
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Driver
Mainframe
computers
Fixed personal
computer
Mobile
Consumer
Internet of
Things and the
Cloud
Key success
Parameters
1. Performance
2. Cost
1. Cost
2. Performance
1. Cost
2. Power
3. Performance
4. Size
1. Cost
2. Power
3. Latency
4. Bandwidth
density
5. Size
Adapted after Bill Bottoms – ECS 2014, Orlando
Time
Wired Wireless

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From TECHNOLOGIES to MARKET
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Silicon / Interconnection trend
500
020406080100
Number
I/O per cm²
20.000
10.000
1500
CMOS90 CMOS45
CMOS28
CMOS16
CMOS65
FinFET
Technology Node
CMOS [nm]
Scaling of Transistor
Nodes => I/Os Density
Increase

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 Continue with development of advanced technology nodes (follow
Moore’s Law)
 Develop new alternative technologies/packages (More than Moore)
in order to be able to meet the market requirements:
What Options Do We Have?
 The CMOS transistors continue to shrink but at the
increase of fab expenses.
 Although performance is increasing, the same trend of
reduced cost has reached its end

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3D Integration: Packaging Added Value
Hybrid Memory Cube
More Moore : miniaturization
130nm 90nm 65nm 45nm 32nm 22nm 14nm 10nm
Analog
+RF
PassivesPowerSensorsEnergy
Sources
Biochips
MoreThanMoore:diversification
SoC
SiP
IPD
RF
CMOS
SMOS
Analog
Power
Low
Power
CMOS
High
Perf. SOI
Non
volatile
Memory
GaAs RF
MEMS
…
3DIC technology is seen today
as a new paradigm for the future
of the semiconductor industry,
as it will enable several more
decades of chip evolution at
ever lower cost, higher
performance and smaller-size
features.
…

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Microelectronics Packaging Evolution
Surface Mount
Ball grid arrays
SiPs
WLCSP
FC BGA
PoP
More SiPs
WLCSP
Flip-Chip
Fan-Out
Interposers
3DIC
SiP
1980
TechnologyIntroduction
GapFeaturesSivsPCB
Through hole
Mature
1970 1990 2000 2010
DIP, PGA
SOP, QFP, PLCC CSPs/BGAs
Today
Established Emerging
Feature sizes CMOS
Bridging the Gap Between Si and PCB Processing Capabilities
Feature sizes of PCBs

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Advanced Packaging Evolution
The growing and diversifying system requirements have continued to drive the development of a
variety of new package styles and configurations:
 Small-form-factor
 Lightweight technology
 Low-profile technology
 High-pin-count technology
 High-speed technology
 High Reliability
 Improved thermal management
 Lower cost
Increased functionality, speed, higher bandwidth, increased I/Os, …
Complexity:
Lead-frame based Packages Wirebonded
FCBGA
Through Silicon Via
FCCSP
PoP, PiP
3D Wirebonding ….
3D SiP
Performance:

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Advanced Packaging Platforms
Leadframes
QFN,QFP
w/o IC substrates
Fan-in Fan-out
IC substrates-based
BGA
(organic substrate)
W/B BGA Flip Chip BGA 3DIC
Interposer
based
(Si, Glass, Org)
SiP
Embedded
die
(in substrate)
PCB substrate
Increased functionality, I/Os, integration complexity
Interconnect:
Single die
Multiple Dies
FO MCP
Integration:2D 3D
Embedded die
(in substrate)
3D Stacking SiP
Bumping, Pillars, Studs, Through-silicon-via, Bump-less, Embedded Technologies...

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Fan-In WLCSP Market Drivers & Activities
 Fan-in WLP maintains its appeal as the package that can provide 2
unmatchable advantages:
• Reduced form factor
• Low cost
 Demand is reaching available capacity
 Technology innovation in fan-in WLP continues:
• Die size increases
• Bump pitch reduces
 Foundry involvement is no longer a dent in fan-in WLP production
 Increased activity of Chinese capital on the market
 New applications are emerging while other are declining
• Disruptions also expected in the MEMS and CIS domains
• Internet of Things
Mobile sector is driving fan-in WLP production and growing
IoT is on the horizon and is expected to have a significant impact on
fan-in packages and the packaging industry as a whole
Mobile

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CPU
Drivers Devices packaged using
‘Fan-in’ WLP
Discrete passives
Devices using other packaging
technologies (not ‘Fan-in’ WLP
WLCSP ICs in Handsets
WLCSP
27%
Others
73%
WLCSP
35%
Others
65%
WLCSP
33%
Others
67%
Samsung
Galaxy S6
Huawei Ascend
Mate 7
iPhone 6+
 Avg. 30% WLCSP packages in the latest high end smartphones!

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Flip Chip Market Drivers & Benefits
CPUs / GPUs/chipsets, the
earlier adopters of flip chip
Has transitioned to other devices –
due to several benefits it can bring

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Flip Chip Markets
 Applied across several different markets
…and much more!
Consumer
Automotive
Medical
Industrial
Mobile/wireless
Computing
Smartphones
Tablets
Laptops
UHD TV
Game Station
Desktop PC
Set-up Box
Cars
Ultrasonic Handler
Servers

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Bumping in 2.5D/3DIC Package
Bumps/Cu Pillars:
40-250µm
PCB
BGA Substrate
2.5D Silicon
interposer
X-PU Logic Die
Memory
stack
400-800µm
µ-Bumps: 10-40µm
µ-Bumps
20-80µm
1
2
3
BGA balls
 broad range of bumps, from larger BGAs (connection to the substrate) to very small microbumps
used in stacking the memories
4

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Top Players in 2014!
2014
(#1playe
r)
Bumping &
Assembly
location
TAIWAN
Advanced
Underfill
HENKEL
Flip chip
bonder
BESI
Solder ECD
bumping
SPIL
Gold
bumping
ChipBOND
Cu pillar
bumping
INTEL
Top Players

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Fan-Out vs. Fan-In and Flip-Chip
1 2 3 5 Package/IC
size ratio*
Fan-in WLCSP Fan-out WLCSP Flip Chip
This limit will move to higher ratios as eWLB production moves from
300mm wafers to large panels and the cost of eWLB/fan-out moves lowers.
4 6
IC
IC
IC
Advantages of Fan-Out
vs. Fan - In
• Higher board-level reliability
• Bumping is not limited to the die size, fan-out
area beyond chip area limitation
• Built-in back-side protection (protection
available for WLCSP as an option only)
• Lower thermal resistance
• Higher potential for SiP integration
vs. FCBGA
• Smaller footprint
• No substrate/interposer  Shorter
interconnections
• Higher electrical performance
• lower cost
• thinner package
• Lower thermal resistance
• Higher potential for SiP and 3D integration

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FOWLP End Applications
Mobile and wireless applications are the main markets for FOWLP
 LGE was the first OEM to integrate the eWLB to the wireless baseband in the following models:
• PMB8810 phone, T310 phone, T300 phone, GD350 phone, GB220 phone, GB230 phone, GS170 phone, GU230 phones
 We can also find eWLB in Samsung cell phones (baseband modem)
• Galaxy Tab tablet, Galaxy S phones
 Some Nokia phones use eWLB for the baseband modem and RF transceiver
Extension of the technology platform to a wider field of application areas is starting
 FOWLP is starting to be integrated into automotive and medical applications
 Infineon is using it for its 77GHz RADAR System IC Chipset (RASIC™)
• SiGe transmitter and receiver used by Bosch
 Analogic Ultra Sound is using it for its Sonic Window handheld ultrasound device made for vascular observation
• 10 dies embedded, 33*28 mm² package
2012 2013 20142011

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Fan-Out Applications
Typical view of a smart phone board
RF
SiP
Digital
SiP
Sensor
SiP
Mixed Signal
SiP
SiP Modules:
BGA/PoP/QFN/TSOP
DC/DC
converters
Drivers IPD
ESD/EMI Stand-alone chips:
WL-CSP, SOT, QFN, UTLP, BGA
Discrete passives
Blue: Devices that can be found in FOWLP
packages today
Discrete passives
Yellow: Devices that could be found
in the future in FOWLP
Grey: Devices that will likelyremain on WLCSP or
flip-chip package or move to 3DIC or Embedded
die
TODAY TOMORROW
From TECHNOLOGIES to MARKET
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First Fan-out WLP Technologies
eWLB RCP
59%25%
16%
Main products:
- Single Die: Mobile and Wireless
- BB and Wireless SoC, RF, PMIC
- MCP/SiP products for Mobile (PMU),
Industrial, Medical and Security
applications
Main products:
- Mobile and Wireless
 BB and Wireless SoC
- RF Transceivers
- ASIC
Others
Total 2014
$174M
Wider adoption

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$0M
$500M
$1,000M
$1,500M
$2,000M
$2,500M
2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020
TOTAL $80 $115 $131 $158 $174 $244 $790 $1,223 $1,573 $1,993 $2,391
TSMC addition Mobile $471 $814 $1,088 $1,391 $1,715
TOTAL without TSMC $80 $115 $131 $158 $174 $244 $318 $409 $485 $602 $676
FO-WLPRevenues(M$)
FOWLP activity Revenues (M$)
Overall evolution since eWLB technology introduction
Yole Developpement © Sep 2015
FO WLP Market Forecast
CAGR ~ 55%
CAGR ~ 15%
Transition plateau
• Entry of A10 APE of iPhone7, 7+ and newer from 2016!
• Previous 2014-2020 CAGR was rated at 25%, while new 2014-2020 CAGR is estimated at 55%!
• After the jump, further 2016-2020 CAGR estimated at 32%
• Market estimated to exceed 2B$ by 2020
APPLE/TSMC entry

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650x830mm – Gen 4 LCD
650x650mm – WLP/LCD/PCB
2009 - 2014 2015 2016 2017 > 20182018
450mm
FOWLP 1st-gen - single die
• BB SoC
• RF Transceiver
• ASIC
• PMIC
High yield
Semiconductor WLP
infrastructure
Fusion
WLP/PCB/LCD
infrastructures ?
204x508mm (8”x20” ) - Semi/PCB laminate substrate
500x650mm – PCB laminate
470x370mm – LCD Gen 2
FOWLP 2nd-gen - MCP/SiP/PoP
• DRAM memory
• NAND Flash memory
• APE/BB modem
• RF Tx, RF connectivity
• PMU/PMIC
• GPS
• MOEMS
330mm
Fan-out Infrastructure Evolution

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Drivers and Trends for 2.5D & 3DIC
Evolution
or Revolution?
3DIC / 3D SiP2D SOC
“All-in-One chip system integration”
All functions on 28nm lithography
 Chip area ↑, Cost ↑
MEMS 130 nm 200 mm
Memory 45 nm 300 mm
Logic 20 nm 450 mm
Analog 90 nm 300 mm
3D enables integration of
heterogeneous functions:
• On different lithography nodes
• On different wafer sizes
• In different wafer fabs
• By different players
 Cost ↓, Performance ↑, Size ↓
Time to Market ↓, Flexibility ↑
Market Drivers

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Photonics
Others
(Power,
LED, RF…)
Memory
TSV in a nutshell
MEMS
Logic
CMOS
Image
Sensors
Through
Silicon
Via
TSV

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2.5/3DIC Commercial Announcements!
 Several product announcements using TSV
2014
2011
2015
2017
2016
Nvidia Pascal
Graphics Module
EX-800 Blade Server
using HMC
New second generation
Xenon Phi processor
“Knights Landing” using HMC
Next Generation PRIMEHPC
POST FX10 CPU memory board
using 8 HMC
DDR4 3D
Dual Inline Memory Modules
(RDIMMs)
First Heterogeneous
3D FPGA Virtex-7 H580T
AMD R9 390X
Graphics product with HBM built with
20nm technology
2013
2012
Altera 10 Generation
FPGA using HMC
Stacked NAND Flash
Arria 10
Stratix 10
HMC
HBM
DiRAM4

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Market Evolution
100µm 10µm 1µm 100nm 10nm
PCB Design Rule Wafer Design Rule
Organic Substrate
Silicon/Glass Interposer
~8-> 5µm
More functionalities and advanced technologies nodes
OSAT /
Wafer foundries
Substrate
Manufacturers
High Cost
Lower cost than
Si/Glass Interposer
Opportunity for
organic interposers
Opportunity for Fan-Out
GAP!
Competing technologies

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System in Package
 Enabled by various packaging platforms & interconnect technologies:
• Wirebonding
• Flip-Chip
• Embedded technologies:
‒ Mold (fan-out)
‒ Laminate (embedded dies)
• 2.5D/3DIC
 Substrates:
• Lead-frames
• Laminates
• LTCC substrates
 Protective features:
• Metal lids
• Overmold encapsulation
• EMI shielding
Source: ASE
Side-by-side (Fan-Out)
Stacked (PoP/PiP)
Embedded die in laminate

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Major Benefits and Markets
 Smaller form factor
 Increased flexibility
 Integrating different technologies
 Higher performance: signal propagation, power
dissipation, noise and EMC performance
 Faster time-to-market
 Lower cost
 High added value
 IP protection
 Wireless communications
 Consumer
 Automotive
 IoT (connectivity)
 Medical
 ...
Various Markets

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Leadframes
QFN,QFP
w/o IC substrates
Fan-in Fan-out
IC substrates-based
BGA
(organic substrate)
W/B BGA Flip Chip BGA 3DIC
Interposer
based
(Si, Glass, Org)
SiP
Embedded
die
(in substrate)
SiP Positioning in Advance Packaging
PCB substrate
Increased functionality, performance…
Interconnect:
Single die
Multiple Dies
Integration:2D 3D
Embedded die
(in substrate)
Bumping, Pillas, Studs, Through-silicon-via, Bump-less, Embedded Technologies...
Platform enabling
functionality
through the use of
various packaging
techniques

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 High interest in the industry in several packaging platforms:
Conclusions and Future Perspectives
 Fan-in – stable growth, still driven by low cost and
introduction of new consumer applications requiring
low cost and pin count
 Flip-chip – will continue to grow, but expected to loose
overall market share to platforms such as WLCSP, Fan-
Out and 3DIC. Cu Pillar will continue to be the dominant
flip chip metallurgy
 Fan-Out – very promising platforms already established
in production. Currently using wafer infrastructure, may
move to panel manufacturing in the future
 2.5D & 3DIC – finally in production and adoption
expected to further grow. Fan-out could be a disruptive
technology for consumer applications
 SiP – enabling functionality packaging in a more flexible
way and with a faster time to market. Expected to have
a significant growth
 Advanced Packaging will continue to grow – driven by consumer & IoT

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Thank you!
YOLE DEVELOPPEMENT
COLLABORATION
INNOVATION
NEW PERSPECTIVES
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