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HiPEAC 2019 Workshop - Vision Processing

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Presentation by Cathal McCabe (Xilinx) from one of our Advisory Board Members.

Publicada em: Dispositivos e hardware
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HiPEAC 2019 Workshop - Vision Processing

  1. 1. © Copyright 2018 Xilinx Cathal McCabe, Xilinx University Program Vision processing
  2. 2. © Copyright 2018 Xilinx Agenda ˃ Machine vision ˃ Zynq/Zynq Ultrascale ˃ SDSoC ˃ Libraries ˃ PYNQ ˃ Reduced precision ˃ XUP >> 2
  3. 3. © Copyright 2018 Xilinx “Machine Vision Market Size to Gain USD 15.46 Billion by 2022 Growing at 8.18% CAGR” ˃ Key areas that can benefit most from machine vision Food & beverage Automotive Healthcare ˃ Requirements High speed Low latency Low Power Reliability ˃ =Heterogeneous architectures >> 3 *Market Research Future (MRFR) 2017
  4. 4. © Copyright 2018 Xilinx Slowing to 3% per year Page 4 Computing performance increase *John Hennessy and David Patterson, Computer Architecture: A Quantitative Approach, 6/e. 2018
  5. 5. © Copyright 2018 Xilinx Zynq-7000 Architeture >> 5
  6. 6. © Copyright 2018 Xilinx Zynq® UltraScale+ MPSoC System Features >> 6
  7. 7. © Copyright 2018 Xilinx
  8. 8. © Copyright 2018 Xilinx Scaling the Productivity with Technology Advancement Performance / Watt & ‘Any to Any’ Connectivity EaseofDevelopment CPU Zynq SoC & MPSoC GPU ARM SoCs & DSPs Zynq SoC & MPSoC HLS >> 8
  9. 9. © Copyright 2018 Xilinx ˃ ASSP-like programming experience ˃ Full system optimizing compiler ˃ System-level profiling ˃ Expert use model for platform developers and system architects The SDSoC Development Environment C/C++ Development System-level Profiling Specify C/C++Functions for Acceleration Full system Optimizing Compiler Rapid System Level Performance Estimation Page 9
  10. 10. © Copyright 2018 Xilinx ˃ Eliminates manual design of SW drivers and HW connectivity ˃ Automatically calls HLS to generate IPs ˃ Enables reuse of optimized HDL IP Blocks as C-callable libraries ˃ ‘One-click’ function acceleration in Programmable Logic ˃ Rapid system performance and area what-if analysis SDSoC: Design Flow Page 10 PL PS IP Application Driver Datamover PS-PL interface IP’s
  11. 11. © Copyright 2018 Xilinx ˃ Optimized libraries for faster programming ˃ Available from Xilinx and ecosystem partners https://www.xilinx.com/products/design-tools/software-zone/sdsoc.html#libraries Libraries & Design Examples >> 11
  12. 12. © Copyright 2018 Xilinx Python Productivity for Zynq
  13. 13. © Copyright 2018 Xilinx Frameworks & Libraries Development tools Platforms HDMI MIPI USB3 Machine Learning
  14. 14. © Copyright 2018 Xilinx DeePhi Solution Stack for Deep Learning Core API Driver Runtime Loader Profiler Models Framework Tools & IP AI HW Platforms Compression Pruning Quantization Compilation Compiler Assembler Face detection Pose estimation Video analytics Lane detection Object detection Segmentation Z7020 Board Z7020 SOM ZU2 SOM ZU2/3 Card ZU9 Card ZCU102 ZCU104 Ultra96 Darknet
  15. 15. © Copyright 2018 Xilinx Python Productivity for Zynq
  16. 16. © Copyright 2018 Xilinx >> 16 *https://xkcd.com/353/
  17. 17. © Copyright 2018 Xilinx PYNQ Python Productivity on Zynq Hardware Engineers Embedded software Engineers New users are not always hardware designers, or embedded systems designers Domain Experts Software Engineers Enables more people to program Xilinx processing platforms, more productively PYNQ also enables more rapid development for h/w designers and embedded s/w engineers >> 17
  18. 18. © Copyright 2018 Xilinx Framework for Zynq, Zynq UltraScale+ APIs Drivers Bitstreams Linux kernel Python FPGA Overlay fpga_manager sysgpio uio devmem dma axi_intc Apps Jupyter/ IPython numpy opencvscikit-learnmatplotlib PYNQ notebooks XLNK xlnk GPIOPL Interrupt libcma.soMMIO PYNQ libs PYNQ IPs PYNQ overlays User designs >> 18
  19. 19. © Copyright 2018 Xilinx Software-style Packaging & Distribution of Designs >> 19 Enabled by new hybrid packages xDNN, A. Sirasao et al OpenCV, K. Denolf et alIIoT, C. Fritsch et alQNN, M. Blott et al
  20. 20. © Copyright 2018 Xilinx Machine Learning on Xilinx FPGAs with FINN ˃ Experimental framework from Xilinx Research Labs ˃ Explore low precision deep neural network inference on FPGAs ˃ FINN Framework Tool flow for rapid design generation Templated Vivado HLS library of streaming components Ultra low-latency and high performance with dataflow Many end-to-end example designs >> 20 https://xilinx.github.io/FINN/
  21. 21. © Copyright 2018 Xilinx >> 21
  22. 22. © Copyright 2018 Xilinx Summary ˃Zynq architecture ideal for machine vision ˃SDSoC for automated algorithm to hardware ˃Libraries ˃PYNQ ˃Reduced precision DNN
  23. 23. © Copyright 2018 Xilinx >> 23 ˃ Vivado ˃ SDSoC ˃ SDAccel Zynq MPSoC Ultrascale Academic boards Workshops Partnership program Teaching Research enablement Technical Support Conferences Design Contests Special Events http://www.xilinx.com/university
  24. 24. © Copyright 2018 Xilinx Adaptable. Intelligent.

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