Flip Flop | Counters & Registers | Computer Fundamental and Organization

2
Sequential Circuits
A sequential circuit is a circuit where the output depends
upon not only the present state of the inputs but also past
state of the inputs.
Each of the input and output can have either of the two
states :
– Logic 0 (low)
– Logic 1 (high)
– Examples : Flip-Flop, counter, timer, RAM, Latches.

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Flip-Flops
A flip-flop is a bi-stable circuit, which has two stable states
either high or low.
It can store the bit 0 or 1 and is used for storing values till
required.
The flip-flop has the property to remain in one stable state
until it is directed by an input signal/pulse to switch over to
the other state.
This input signal/pulse is known as a trigger.

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Flip-Flops
When a trigger is received, the flip-flop outputs change their
states according some pre-defined rules, and they will
remain in that state until another trigger is received.
Types of flip – flops :
• R-S Flip – Flop
• J-K Flip - Flop
• Master – Slave Flip - Flop
• Toggle Flip - Flop
• D Flip - Flop

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A basic FF symbol/logic circuit

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R-S/S-R Flip-Flops
An RS flip-flop is a simple building block of a FF. It has two input states
SET and RESET. It is also known as R-S Latch.
It can be constructed by two NANDs or two NOR gates.
When R-S FF is set, the output Q goes to the state ‘1’ and when it is
reset, the output Q goes to a ‘0’ state.
SET- RESET (R-S/ S-R Flip Flop)
S
R
Q
Q
FIG : NAND GATE – S/R FF
with two inputs

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Operation of R-S/S-R Flip-Flops
1. SET = RESET = 1 is the normal resting condition of the ff.
It has no effect on the output state of the flip –flop.
Both Q and Q’ outputs remain in the same logic state in which
they were prior to this input condition.
2. SET = 1 and RESET = 0 sets the ff. Q will become 1 and Q’ will
become 0.
3. SET = 0 and RESET = 1 resets or clears the ff. Q becomes 0 and Q’
becomes 1.
4. SET=RESET=0 is a forbidden condition of a ff. Such a condition tries
to set and reset the ff at the same time i.e. tries to set Q=Q’=1.

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Truth Table - R-S/S-R Flip-Flops

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R-S/S-R Flip-Flops
FIG : NOT/OR GATE – S/R FF
NOTE : THIS R-S FF IS ALSO KNOWN AS R-S FF WITH ACTIVE – HIGH STATE
(I.E. A FF WHERE SET =1 SETS THE FF, SET =0 RESETS THE FF)

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R-S/S-R Flip-Flops
R-S/ S-R Flip Flop – ACTIVE LOW STATE
An R-S FF is a ‘LOW STATE’ FF when, SET =0 sets the FF and SET =1 resets the FF.
In an ACTIVE –LOW RS FF, if SET=RESET=1, the FF values will remain unchanged,
If SET=RESET=0, the FF values will be forbidden.
R
S
Q
Q
S R Q Q’ STATE
0 0 x X Forbidden/ Invalid
0 1 1 0 SET
1 0 0 1 RESET
1 1 NC NC NO CHANGE

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Clocked R-S FF- HIGH ACTIVE STATE
A clocked FF is a FF, in which the operations of the flip flop are carried out
based on the value of the clock i.e. the FF will change its state only when the
CLOCK has a specific input value.
For A HIGH active state Clocked RS FF, the input values and output values will
change only when the input value of the clock will be 1.
The state of the FF will change based on the values of R,S only when Clock = 1.

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S R Q Q’ CLK STATE
0 0 - - 0 NO CHANGE
0 0 NC NC 1 NO CHANGE
0 1 0 1 0 NO CHANGE
0 1 0 1 1 RESET
1 0 1 0 0 NO CHANGE
1 0 1 0 1 SET
1 1 X X 0 NO CHANGE
1 1 X X 1 FORBIDDEN /
INVALID

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Working of clocked RS HIGH ACTIVE STATE FF
• When the clock signal is high (clk=1), the two NAND gates are enabled and
the S and R inputs are passed in the FF, with their states in complement
form (see figure).
• The output can change the states as per values of R and S.When S=1 and
R=0, the FF will be set if the CLOCK is high, i.e. clk =1.
• When S=0 and R=1, the FF will be reset if clk =1.
• When S=R=1 the FF will be in a forbidden state and when S=R=0 the state of
the FF will remain unchanged.
• IF CLK=0, the inputs R,S will be disabled and hence there would be no
change in the state of the FF.

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Clocked R-S FF- LOW ACTIVE STATE
For A LOW active state Clocked RS FF, the input values and output values will
change only when the input value of the clock will be 1.
The state of the FF will change based on the values of R,S only when Clock = 1.

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S R Q Q’ CLK STATE
0 0 - - 0 NO CHANGE
0 0 X X 1 FORBIDDEN/INVAL
ID
0 1 0 1 0 NO CHANGE
0 1 0 1 1 SET
1 0 1 0 0 NO CHANGE
1 0 1 0 1 RESET
1 1 - - 0 NO CHANGE

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Working of clocked RS HIGH ACTIVE STATE FF
• When the clock signal is high (clk=1), the two NAND gates are enabled and
the S and R inputs are passed in the FF, with their states in complement
form (see figure).
• The output can change the states as per values of R and S. When S=0 and
R=1, the FF will be set if the CLOCK is high, i.e. clk =1.
• When S=1 and R=0, the FF will be reset if clk =1.
• When S=R=1 the FF will be remain unchanged and when S=R=0 the state of
the FF will be forbidden of invalid.
• IF CLK=0, the inputs R,S will be disabled and hence there would be no
change in the state of the FF.

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J-K FLIP FLOP
• A JK FF is a modified version of RS/SR FF with no invalid or forbidden state.
• Note: Edge/Level triggered FF diagram page - 291

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Master- Slave FLIP FLOP
• In JK FF, when J=K=1 and CLK =1, their might be a situation when the clock
pulse takes longer then the inputs or the inputs take longer to come then
the clk pulse.
• This is because each of the inputs come by different channels and so there
are chances of delay.
• If the delay occurs in either of the three inputs then the input which has
already come will toggle constantly and it will not be possible to determine
the output value. This situation is called the RACE CONDITION.
• M-S FF is used to avoid race condition.

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• A MS FF is a cascade of two JK FFs. The outputs from Q and Q’ from the
“Slave” flip-flop are fed back to the inputs of the “Master” with the outputs
of the “Master” flip flop being connected to the two inputs of the “Slave”
flip flop.
• The clocks of both the FF are connected by a inverter which controls the
clock pulse of both the FFs.
• Due to the inverter, when clock of the master FF is high, the clock of the
slave FF will be low or 0 i.e. disabled.When clock of the slave FF is high, the
clock of the master will be low or 0 i.e. disabled.

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J K Q Q’ CLK STATE
1 0 1 0 1 SET
0 1 0 1 1 RESET
1 1 Q’ Q 1 TOGGLE

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T-FLIP FLOP
A T FF or a Toggle FF is a modified JK FF in which J and K input are connected permanently together. It is
also called as single input JK FF.
The T flip flop has only two states hold and toggle and it has only two possible values.
When T =0 , the FF will be in a hold state and there will be no change in the outputs.
When T=1, the FF will be in a toggle state and the outputs will toggle their values.
T Q Q’ STATE
0 NC NC NO CHANGE
1 Q’ Q TOGGLE

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D-FLIP FLOP
A D FF also called a delay FF, is a modified version of the S-R FF.
It is used to provide temporary storage of one bit of data. Also, D FF is one of the most important clocked FF, as it
ensures that S and R will be never equal to 1 at the same time.
The D-type flip flop is constructed from a gated SR flip-flop with an inverter added between the S and the R inputs
to allow for a single D(data) input.The input D is used to set the FF and the inverter is used to reset the FF.
When D=0, the FF will be reset , and when D=1 the FF will be set.
D Q Q’ STATE
0 0 1 RESET
1 1 0 SET

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FLIP FLOP Applications
Flip-flops are used in a variety of application circuits such as : -
1. Frequency Division and Counting Circuits. (Using Counters)
2. Data Storage and Transfer Circuits. (Using Registers)
Both these applications use a cascaded arrangement of flip-flops with or without some additional combinational
logic to perform the desired function.
Other applications of flip-flops are:
1. Switch debouncing
2. Flip-Flop synchronization
3. Detecting Edge sequence

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Unit -6
Counters & Registers

25
Introduction
Counters and registers are Medium Scale Integration type of sequential logic circuits.
Both of them are made by cascaded arrangement of more than one flip flops with or without combinational
circuits.
Counters are mainly used to measure time interval or to measure frequency of a given signal. Registers are used
to store data temporarily until they are given to a digital circuit.
Counters:
There are two main types of counters :
1. Asynchronous Counters
2. Synchronous Counters

26
Counters
There are two main types of counters :
1. Asynchronous Counters
In these types of counters, the clock input is given only to the first flip flop, the remaining clocks get the
input as an output of the previous flip flop and thus there is a delay of getting inputs in all the clocks.
2. Synchronous Counters
In these types of counters, the clock input is given simultaneously to all the flip-flops at once.

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Counters : Ripple Counter
A ripple counter is a cascaded arrangement of flip-flops where the output of one flip-flop drives the clock input of
the following flip-flop.
In a ripple counter, the clock input is applied only to the first flip-flop, also called the input flip-flop, in the
cascaded arrangement. The output of the first flip-flop acts as the clock input to the second flip-flop, the output of
the second flip-flop is the clock input of the third flip-flop and so on.
In general, in an arrangement of n flip-flops, the clock input to the nth flip-flop comes from the output of the
(n − 1) th flip-flop for n > 1.
Delay in the clock input can be counted by : n x propagation delay of one flip flop.
Limitation : All FFs cannot change their state at the same time as the clock signal is not available to all the FFs at
the same time.

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Counters : Synchronous Counters
Also known as parallel counters.
all the flip-flops in the counter change state at the same time in synchronism with the input clock signal.
The clock signal is simultaneously applied to the clock inputs of all the flip-flops. The delay involved in this
case is equal to the propagation delay of one flip-flop only, irrespective of the number of flip-flops used to
construct the counter.

30
Counters : Binary Ripple Counter
A binary ripple counter consists of a series connection of complementing flip-flops in which the output of
each flip-flop is connected to the C input of the next higher-order flip-flop.
The output of the first flip-flop feeds the clock input of the second, and the output of the second flip-flop
feeds the clock input of the third and so on.
The flip flop here is made by using negative edge triggerreing flip flops.

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The flip flop holding the LSB receives the input.
For an incremental counter, the count starts with binary 0 and increments by one with receiving each
clock input. After count 15, the counter goes back to 0 and begins the counter again.
For an decremental counter, the count starts with binary 15 and decrements by one with receiving each
clock input. After count 0, the counter goes back to 15 and begins the counter again.

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.

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Registers
.
Types of registers:
• Shift registers such as
▪ Serial ln Serial Out
▪ Serial In Parallel Out
▪ Parallel In Serial Out
▪ Parallel In Parallel Out
Register:
− A set of n flip-flops
− Each flip-flop stores one bit
− Two basic functions: data storage and data

34
Registers- Shift Registers
A shift register is a digital device used for storage and transfer of data.
The shift register forms an important link between the main digital system and the
input/output channels.
The task of the shift register is
- allow each of the flip flop to pass stored data to its adjacent register.
- design counters for arithmetic operations
The basic building block of a shift register is the D- Flip Flop.
The storage capacity of a shift register depends on the number of flip flops used to design the
shift register.
Shift registers are classified based on the method of load data and read data from shift
registers.

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Shift Registers – Serial In Serial Out
The SISO register accepts the data serially, i.e. one bit at a time on a single line. The output is
also produced serially, one bit at a time.
Circuit/ Symbol Representation

36
The SISO register accepts the data serially, i.e. one bit at a time on a single line. The output is
also produced serially, one bit at a time.
The operation of the shift register is as follows:
1. The register is first cleared, forcing all four outputs to zero.
2. The input data is then applied sequentially to the D input of the first flip-flop
on the left (QA).
3. During each clock pulse, one bit is transmitted from left to right.
4. Assume a data word to be 1001.
5. The least significant bit of the data has to be shifted through the register from QA to QD.
In order to get the data out of the register, they must be shifted out serially.

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The clock corresponds to the rising edge of the serial input.
If the serial input goes from 0 to 1 just before CK pulse 1, the Q output of flip-flop QA will go high at the rising
edge of CK pulse 1. At the next clock pulse rising edge, the logic 1 will be transferred to QB and so on until it
reaches QD, and the serial output.

38

39
Shift Registers – Serial In Parallel Out
In a SIPO, the register is loaded with serial data, one bit at a time, with the stored data being available at the
output in a parallel form.
An 8-bit SIPO Register

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Shift Registers – Serial In Parallel Out
The gated serial inputs A and B control the incoming serial data and to enable the shift register.
Once the data are stored, each bit appears on its respective shift register output line, and all bits are
available simultaneously.

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Shift Registers – Parallel In Serial Out
In PISO register, he parallel data is loaded into the register simultaneously and is shifted out of the
register serially one bit at a time under clock control.
D0, D1, D2 and D3 are the parallel inputs, where D0 is the most significant bit and D3 is the least
significant bit. To write data in, the mode control line is taken to LOW and the data is clocked in. The
data can be shifted when the mode control line is HIGH as SHIFT is active high

42
Shift Registers – Parallel In Serial Out

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Shift Registers – Parallel In Parallel Out
In PIPO register, the parallel data is loaded simultaneously into the register, and transferred together to
their respective outputs by the same clock pulse.
Here, D’s are the parallel inputs and Q’s are the parallel outputs. There is no interconnection between the
individual flip-flops as no serial shifting of data is required.

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Shift Registers – Parallel In Parallel Out

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