PhD evaluation presentation
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This document outlines Muhammad Sanaullah's master's thesis on developing a formal modeling and verification methodology for smart environments at Politecnico di Torino under the supervision of Professor Fulvio Corno. The methodology takes an incremental approach, first verifying device models, then the intelligent domotic environment (IDE) logic, and finally integrating it all into a smart environment model. Formal modeling languages and model checking techniques are used at each stage. The goal is to identify errors early and ensure smart environments behave reliably given their safety-critical nature. Several case studies and publications demonstrate the approach.
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- 1. Politecnico di Torino Dipartimento di Automatica e Informatica Torino, Italy http://elite.polito.it Design Time Methodology for the Formal Modeling and Verification of Smart Environments Tutor: Prof. Fulvio Corno Muhammad Sanaullah 4 year (25 Cycle)
- 2. Smart Environment (SmE) The environment which is richly integrated with multitude of devices and performs operations, in an intelligent manner, by considering the actions and presences of users is known as Smart Environment (SmE). Basic Components of SmE 2 Users Devices Decision Logic Environment Design Time Methodology for the Formal Modeling and Verification of Smart Environments
- 3. Motivation for the adoption of Formal Verification The intricate communication among these components along with satisfaction of varied natured constraints introduced a high degree of complexity, in-result the likelihood of error may increase. Due to their sensitive implementation scenarios (e.g. homes, hospitals, offices, industries, airports or railways) the reliance on these systems demands consistent behavior. The reliable behavior of such system can be ensured by using verification approaches, which help in identifying and correcting the errors in early design stages of the system. Of the many available modeling and verification techniques, formal methods appear to be the most promising. 3 Design Time Methodology for the Formal Modeling and Verification of Smart Environments
- 4. Adopted Incremental Strategy Devices Verification IDE Verification SmE Verification A comprehensive compression with state-of-the- art Satisfaction of High-Level SmE Goals 4 Design Time Methodology for the Formal Modeling and Verification of Smart Environments
- 5. Devices verification Consistency Verification Ontology Modeling Statechart Modeling Ontology Reliable Behavior Verification Statechart Modeling Statechart Fulvio Corno, Muhammad Sanaullah, “Formal Verification of Device State Chart Models”, IEEE Computer Society (USA), The 7th International Conference on Intelligent Environments, Nottingham (UK) 25-28 July 2011, page no. 66 to 73, ISBN: 9780769544526, DOI:10.1109/IE.2011.36 5 Design Time Methodology for the Formal Modeling and Verification of Smart Environments
- 6. IDE Modeling Main Components Devices Decision/Control Logic Verifies Reliable interaction Control strategy Safety Security A case study: Bank Door Security Booth System (BDSB) Fulvio Corno, Muhammad Sanaullah, “Design time Methodology for the Formal Verification of Intelligent Domotic Environments”, In: Ambient Intelligence- Software and Applications, Springer Berlin (DEU), International Symposium on Ambient Intelligence, Salamanca (ES) 6 - 8 April 2011, pp. 8, 2011, Vol. 92, page no. 9 to 16, ISBN: 9783642199363, DOI:10.1007/978-3-642-19937-0_2 6 Design Time Methodology for the Formal Modeling and Verification of Smart Environments
- 7. SmE Verification Main Components Devices Decision/Control Logic Users Environment/Context A generic methodology modeling and verification of SmE Verification Interaction Control Context Extended case study of BDSB Fulvio Corno, Muhammad Sanaullah, “Modeling and Formal Verification of Smart Environments”, In: Hangbae C, Lee D, Overill R (ed) Special Issue: Human-centric Security Service and Its Application in Smart Space, Security and Communication Networks, 2013, pages 17, DOI: 10.1002/sec.794. 7 Design Time Methodology for the Formal Modeling and Verification of Smart Environments
- 8. A comprehensive comparison with state-of-the-art Comparison by proposing Parameter-Based Empirical Methodology Focusing on the adopted modeling and verification State-of-the art Covering Aspects Uncovered Areas Employed Tools Fulvio Corno, Muhammad Sanaullah, “Design-Time Formal Verification for Smart Environments: An Exploratory Perspective”, Journal of Ambient Intelligence and Humanized Computing, 2013, pages22, DOI: 10.1007/s12652-0130209-4 8 Design Time Methodology for the Formal Modeling and Verification of Smart Environments
- 9. Satisfaction of High-Level SmE Goals Relate to acquiring the functionalities of a single device or a group of devices Muhammad Sanaullah, Fulvio Corno, Faisal Razzak, “Automatic Device Activation Regarding High-Level Goals in Smart Environments”, Journal of Ambient Intelligence and Smart Environments, 2013, pages 17 (Minor Revision submitted: 26 November 2013). 9 Design Time Methodology for the Formal Modeling and Verification of Smart Environments
- 10. Adopted formalisms Design Artifact Technique Formalism System Specifications Temporal Logics UCTL Temporal Logic Device Interface Modeling Ontology DogOnt Classes Device Behaviour Modeling Parallel State Machines UML Statecharts in SCXML Control Algorithms State Machines UML Statecharts in SCXML Users Modeling Parallel State Machines UML Statecharts in SCXML Environment Modeling Parallel State Machines UML Statecharts in SCXML System Configuration Ontology DogOnt Instances Whole System Behavior Modeling Parallel State Machines UML Statecharts in SCXML High Level SmE Goals Modeling Ontology DogEffect Classes Formal Verificaiton Model Checking UMC Model Checker Set based enforcement Domotic Effect Framework User Goals Enforcement 10 Design Time Methodology for the Formal Modeling and Verification of Smart Environments
- 11. Publications Journal: Muhammad Sanaullah, Fulvio Corno, Faisal Razzak, “Automatic Device Activation Regarding HighLevel Goals in Smart Environments”, Journal of Ambient Intelligence and Smart Environments, 2013, pages 17 (Minor Revision submitted: 26 November 2013). Fulvio Corno, Muhammad Sanaullah, “Design-Time Formal Verification for Smart Environments: An Exploratory Perspective”, Journal of Ambient Intelligence and Humanized Computing, 2013, pages 22, DOI: 10.1007/s12652-013-0209-4 Fulvio Corno, Muhammad Sanaullah, “Modeling and Formal Verification of Smart Environments”, In: Hangbae C, Lee D, Overill R (ed) Special Issue: Human-centric Security Service and Its Application in Smart Space, Security and Communication Networks, 2013, pages 17, DOI: 10.1002/sec.794. Conferences: Fulvio Corno, Muhammad Sanaullah, “Formal Verification of Device State Chart Models”, IEEE Computer Society (USA), The 7th International Conference on Intelligent Environments, Nottingham (UK) 25-28 July 2011, page no. 66 to 73, ISBN: 9780769544526, DOI:10.1109/IE.2011.36 Fulvio Corno, Muhammad Sanaullah, “Design time Methodology for the Formal Verification of Intelligent Domotic Environments”, In: Ambient Intelligence- Software and Applications, Springer Berlin (DEU), International Symposium on Ambient Intelligence, Salamanca (ES) 6 - 8 April 2011, pp. 8, 2011, Vol. 92, page no. 9 to 16, ISBN: 9783642199363, DOI:10.1007/978-3-642-19937-0_2 11 Design Time Methodology for the Formal Modeling and Verification of Smart Environments
- 12. http://elite.polito.it muhammad.sanaullah@polito.it 12 Design Time Methodology for the Formal Modeling and Verification of Smart Environments
Editor's Notes
- For obtaining the reliable behavior of the system an incremental strategy is adopted which works at different levels and ensured the reliance of the system. In 5 steps the overall goal is achieved. The work carried out in each step is explained in the following presentation.
- The devices are major components of SmE. They range from simple (e.g. lamp) to complex (e.g. TV). Due to their heterogeneous nature, they differ with each other and may have complex internal behavior. The formal modeling of these devices can be performed by adopting Black box or white box modeling conventions.Black box modeling can be used as a core reference point for communication. For systematically designing the system, the consistency among the adopted conventions is important, Moreover, the behavior of each device have to consistent with specification.In this step such consistencies are ensured. The work is published in conference organized by IEEE compute society of USA.
- In the second step, a formal methodology is designed for the system which control the interaction among devices by imposing certain constraints. Then with the help of model checker the specification related to the reliable interactions, control, safety and security of the system is ensured. BDSB is used as a case study. Results show the reliable interaction and control under the certain constraints. This work is published in a well reputed conference, and the paper got a scientific excellence award.
- In this step, the remaining components of SmE (users and environment) are introduced in the system. More complex requirements related to context and environment are considered. For designing such context based environments a comprehensive methodology is designed, by identifying the tasks carried out in each steps. Following the methodology a technique is designed and an extended case study of BDSB is used for validating the methodology. The proposed methodology with the designed technique, case study and obtained results are published in the special issue (Human-centric Security Service and Its Application in Smart Space) of ISI indexed (Security and Communication Networks) Journal.
- Identified aspects regarding users modeling are 6. in our work user history and privileges are not considered.The identified aspects for interaction modeling are categorized in 6 groups. And our set of methodologies covered all.
- In our last step, the high level configuration of the system are tired to achieved.
- For the implementation the designed approaches adopted different formalisms and tools. The list of these adopted formalisms and tools are presented here.