SlideShare uma empresa Scribd logo
1 de 26
Baixar para ler offline
Power Dissipation 
CMOS
Outline 
• Motivation to estimate power dissipation 
• Sources of power dissipation 
• Dynamic power dissipation 
• Static power dissipation 
• Metrics 
• Conclusion
Need to estimate power dissipation 
Power dissipation affects 
• Performance 
• Reliability 
• Packaging 
• Cost 
• Portability
Where Does Power Go in CMOS? 
• Dynamic Power Consumption 
Charging and Discharging Capacitors 
• Short Circuit Currents 
Short Circuit Path between Supply Rails during Switching 
• Leakage 
Leaking diodes and transistors
Node Transition Activity and Power 
•Due to charging and discharging of capacitance 
Consider switching a CMOS gate for N clock cycles 
E 
N 
=  2  nN 
C 
L 
V 
dd 
EN : the energy consumed for N clock cycles 
n(N): the number o f 0->1 transition in N clock cycles 
P 
avg 
lim 
N  
E 
N 
N 
-------- f 
clk 
=  
nN 
N 
 lim 
------------ 
  C 
  
N  
L 
V 
dd 
 
2 
f 
clk 
=  
= lim 
 
0  1 
nN 
------------ 
N 
N   
P 
avg 
=  
 C 
0  1 
L 
 2 f 
V 
dd 
clk 

Activity factors of basic gates 
• AND 
• OR 
• XOR 
A B A B   (1 p p ) p p 
(1 )(1 )[1 (1 )(1 )] A B A B    p  p   p  p 
[1 ( 2 )]( 2 ) A B A B A B A B    p  p  p p p  p  p p
Dynamic Power dissipation 
• Power reduced by reducing Vdd, f, C and also activity 
• A signal transition can be classified into two categories 
 a functional transition and 
 a glitch
Glitch Power Dissipation 
• Glitches are temporary changes in the value of the output – 
unnecessary transitions 
• They are caused due to the skew in the input signals to a gate 
• Glitch power dissipation accounts for 15% – 20 % of the 
global power 
• Basic contributes of hazards to power dissipation are 
– Hazard generation 
– Hazard propagation
Glitch Power Dissipation 
• P = 1/2 .CL.Vdd . (Vdd – Vmin) ; 
Vmin : min voltage swing at the output 
• Glitch power dissipation is dependent on 
– Output load 
– Input pattern 
– Input slope
Power dissipation cmos
Glitch Power Dissipation 
• Hazard generation can be reduced by gate sizing and path 
balancing techniques 
• Hazard propagation can be reduced by using less number of 
inverters which tend to amplify and propagate glitches
Short Circuit Power Dissipation 
• Short circuit current occurs during signal transitions when 
both the NMOS and PMOS are ON and there is a direct path 
between Vdd and GND 
• Also called crowbar current 
• Accounts for more than 20% of total power dissipation 
• As clock frequency increases transitions increase 
consequently short circuit power dissipation increases 
• Can be reduced : 
– faster input and slower output 
– Vdd <= Vtn + |Vtp| 
• So both NMOS and PMOS are not on at the same time
Power dissipation cmos
Static Power Consumption 
Vin=5V 
Vout 
CL 
Vdd 
Istat 
Pstat = P(In=1).Vdd . Istat 
• Dominates over dynamic consumption 
Wasted energy … 
Should be avoided in almost all cases 
• Not a function of switching frequency
Static Power Dissipation 
• Power dissipation occurring when device is in standby mode 
• As technology scales this becomes significant 
• Leakage power dissipation 
• Components: 
– Reverse biased p-n junction 
– Sub threshold leakage 
– DIBL leakage 
– Channel punch through 
– GIDL Leakage 
– Narrow width effect 
– Oxide leakage 
– Hot carrier tunneling effect
Leakage Current
Power dissipation cmos
Power dissipation cmos
New Problem: Gate Leakage 
„Now about 20-30% of all leakage, and growing 
„Gate oxide is so thin, electrons tunnel thru it… 
„NMOS is much worse than PMOS
Principles for Power Reduction 
• Prime choice: Reduce voltage! 
– Recent years have seen an acceleration in 
supply voltage reduction 
– Design at very low voltages still open question 
(0.6 … 0.9 V by 2010!) 
• Reduce switching activity 
Logic synthesis 
Clock gating 
• Reduce physical capacitance 
– Proper Device Sizing 
– Good layout
Factors affecting leakage power 
• Temperature 
– Sub-threshold current increases exponentially 
• Reduction in Vt 
• Increase in thermal voltage 
– BTBT increases due to band gap narrowing 
– Gate leakage is insensitive to temperature change
Factors affecting leakage power 
• Gate oxide thickness 
– Sub-threshold current decreases in long channel transistors and 
increases in short channel 
– BTBT is insensitive 
– Gate leakage increases as thickness reduces
Solutions 
• MTCMOS 
• Dual Vt 
• Dual Vt domino logic 
• Adaptive Body Bias 
• Transistor stacking
Metrics 
• Power Delay product 
• Energy Delay Product 
– Average energy per instruction x average inter instruction 
delay 
• Cunit_area 
– Capacitance per unit area
Summary 
„Power Dissipation is already a prime design constraint 
„Low-power design requires operation at lowest possible 
voltage and clock speed 
„Low-power design requires optimization at
Conclusion 
• Power dissipation is unavoidable especially as technology 
scales down 
• Techniques must be devised to reduce power dissipation 
• Techniques must be devised to accurately estimate the power 
dissipation 
• Estimation and modeling of the sources of power dissipation 
for simulation purposes

Mais conteúdo relacionado

Mais procurados

Mos transistor
Mos transistorMos transistor
Mos transistorMurali Rai
 
Low Power VLSI Design Presentation_final
Low Power VLSI Design Presentation_finalLow Power VLSI Design Presentation_final
Low Power VLSI Design Presentation_finalJITENDER -
 
Introduction to CMOS Inverter
Introduction to CMOS InverterIntroduction to CMOS Inverter
Introduction to CMOS InverterVARUN KUMAR
 
Silicon on Insulator (SOI) Technology
Silicon on Insulator (SOI) TechnologySilicon on Insulator (SOI) Technology
Silicon on Insulator (SOI) TechnologySudhanshu Janwadkar
 
MOSFET and Short channel effects
MOSFET and Short channel effectsMOSFET and Short channel effects
MOSFET and Short channel effectsLee Rather
 
low pw and leakage current techniques for cmos circuits
low pw and leakage current techniques for cmos circuitslow pw and leakage current techniques for cmos circuits
low pw and leakage current techniques for cmos circuitsAnamika Pancholi
 
Low Power Design Approach in VLSI
Low Power Design Approach in VLSILow Power Design Approach in VLSI
Low Power Design Approach in VLSISilicon Mentor
 
Cmos design
Cmos designCmos design
Cmos designMahi
 
Introduction to VLSI Design
Introduction to VLSI DesignIntroduction to VLSI Design
Introduction to VLSI DesignKalyan Acharjya
 
Fan-in and Fan-out.ppt
Fan-in and Fan-out.pptFan-in and Fan-out.ppt
Fan-in and Fan-out.pptvsnishok
 
Short channel effects
Short channel effectsShort channel effects
Short channel effectsashish bait
 

Mais procurados (20)

Power Gating
Power GatingPower Gating
Power Gating
 
Mos transistor
Mos transistorMos transistor
Mos transistor
 
Low Power VLSI Design Presentation_final
Low Power VLSI Design Presentation_finalLow Power VLSI Design Presentation_final
Low Power VLSI Design Presentation_final
 
Introduction to CMOS Inverter
Introduction to CMOS InverterIntroduction to CMOS Inverter
Introduction to CMOS Inverter
 
Study of vlsi design methodologies and limitations using cad tools for cmos t...
Study of vlsi design methodologies and limitations using cad tools for cmos t...Study of vlsi design methodologies and limitations using cad tools for cmos t...
Study of vlsi design methodologies and limitations using cad tools for cmos t...
 
Pass Transistor Logic
Pass Transistor LogicPass Transistor Logic
Pass Transistor Logic
 
Silicon on Insulator (SOI) Technology
Silicon on Insulator (SOI) TechnologySilicon on Insulator (SOI) Technology
Silicon on Insulator (SOI) Technology
 
Second order effects
Second order effectsSecond order effects
Second order effects
 
Vlsi stick daigram (JCE)
Vlsi stick daigram (JCE)Vlsi stick daigram (JCE)
Vlsi stick daigram (JCE)
 
MOSFET and Short channel effects
MOSFET and Short channel effectsMOSFET and Short channel effects
MOSFET and Short channel effects
 
CMOS LOGIC STRUCTURES
CMOS LOGIC STRUCTURESCMOS LOGIC STRUCTURES
CMOS LOGIC STRUCTURES
 
low pw and leakage current techniques for cmos circuits
low pw and leakage current techniques for cmos circuitslow pw and leakage current techniques for cmos circuits
low pw and leakage current techniques for cmos circuits
 
Low Power Design Approach in VLSI
Low Power Design Approach in VLSILow Power Design Approach in VLSI
Low Power Design Approach in VLSI
 
Low Power VLSI Design
Low Power VLSI DesignLow Power VLSI Design
Low Power VLSI Design
 
Dynamic logic circuits
Dynamic logic circuitsDynamic logic circuits
Dynamic logic circuits
 
Asic design flow
Asic design flowAsic design flow
Asic design flow
 
Cmos design
Cmos designCmos design
Cmos design
 
Introduction to VLSI Design
Introduction to VLSI DesignIntroduction to VLSI Design
Introduction to VLSI Design
 
Fan-in and Fan-out.ppt
Fan-in and Fan-out.pptFan-in and Fan-out.ppt
Fan-in and Fan-out.ppt
 
Short channel effects
Short channel effectsShort channel effects
Short channel effects
 

Destaque

اسرع طريقة لاحتراف برمجة المايكروكنترولر
اسرع طريقة لاحتراف برمجة المايكروكنترولراسرع طريقة لاحتراف برمجة المايكروكنترولر
اسرع طريقة لاحتراف برمجة المايكروكنترولرmessaoudi mohamed
 
Power consumption
Power consumptionPower consumption
Power consumptionsdpable
 
Critical Path Analysis
Critical Path AnalysisCritical Path Analysis
Critical Path Analysistutor2u
 
Critical Path Ppt
Critical Path PptCritical Path Ppt
Critical Path PptJeff Hilton
 

Destaque (7)

Static Noise margin
Static Noise margin Static Noise margin
Static Noise margin
 
اسرع طريقة لاحتراف برمجة المايكروكنترولر
اسرع طريقة لاحتراف برمجة المايكروكنترولراسرع طريقة لاحتراف برمجة المايكروكنترولر
اسرع طريقة لاحتراف برمجة المايكروكنترولر
 
Power consumption
Power consumptionPower consumption
Power consumption
 
Critical Path Analysis
Critical Path AnalysisCritical Path Analysis
Critical Path Analysis
 
Critical Path Ppt
Critical Path PptCritical Path Ppt
Critical Path Ppt
 
555 Timer IC
555 Timer IC555 Timer IC
555 Timer IC
 
INTRODUCTION_TO_IC
INTRODUCTION_TO_ICINTRODUCTION_TO_IC
INTRODUCTION_TO_IC
 

Semelhante a Power dissipation cmos

MOS Inverters Switching Characterstics and interconnect Effects-converted.pptx
MOS Inverters Switching Characterstics and interconnect Effects-converted.pptxMOS Inverters Switching Characterstics and interconnect Effects-converted.pptx
MOS Inverters Switching Characterstics and interconnect Effects-converted.pptxBalraj Singh
 
lecture 10 - electrical machines - dc to dc converters 1.pptx
lecture 10 - electrical machines - dc to dc converters 1.pptxlecture 10 - electrical machines - dc to dc converters 1.pptx
lecture 10 - electrical machines - dc to dc converters 1.pptxJohnkamanda3
 
PCB Layout guidelines.pdf
PCB Layout guidelines.pdfPCB Layout guidelines.pdf
PCB Layout guidelines.pdfssuserf36d4d1
 
Unit no. 5 cmos logic design
Unit no. 5 cmos logic designUnit no. 5 cmos logic design
Unit no. 5 cmos logic designswagatkarve
 
Advd lecture 08 -inverte rpart3
Advd   lecture 08 -inverte rpart3Advd   lecture 08 -inverte rpart3
Advd lecture 08 -inverte rpart3Hardik Gupta
 
MY PROJECT-automatic load sharing of transformer by using GSM tecnique.
MY PROJECT-automatic load sharing of transformer by using GSM tecnique.MY PROJECT-automatic load sharing of transformer by using GSM tecnique.
MY PROJECT-automatic load sharing of transformer by using GSM tecnique.nikhilhiware
 
POWER CONSUMPTION AT CIRCUIT OR LOGIC LEVEL IN CIRCUIT
POWER CONSUMPTION AT CIRCUIT OR LOGIC LEVEL IN CIRCUITPOWER CONSUMPTION AT CIRCUIT OR LOGIC LEVEL IN CIRCUIT
POWER CONSUMPTION AT CIRCUIT OR LOGIC LEVEL IN CIRCUITAnil Yadav
 
Power Electronics- Power Semiconductor devices.pptx
Power Electronics- Power Semiconductor devices.pptxPower Electronics- Power Semiconductor devices.pptx
Power Electronics- Power Semiconductor devices.pptxPoornima D
 
Design_of_Power_Transformers.ppt
Design_of_Power_Transformers.pptDesign_of_Power_Transformers.ppt
Design_of_Power_Transformers.pptSelvaPriyaAEEE2020
 
Low power in vlsi with upf basics part 1
Low power in vlsi with upf basics part 1Low power in vlsi with upf basics part 1
Low power in vlsi with upf basics part 1SUNODH GARLAPATI
 
3-Anandi.ppt
3-Anandi.ppt3-Anandi.ppt
3-Anandi.pptECEHoD16
 

Semelhante a Power dissipation cmos (20)

lecture_10.ppt
lecture_10.pptlecture_10.ppt
lecture_10.ppt
 
cmos.ppt
cmos.pptcmos.ppt
cmos.ppt
 
Cmos circuits
Cmos circuitsCmos circuits
Cmos circuits
 
Power
PowerPower
Power
 
MOS Inverters Switching Characterstics and interconnect Effects-converted.pptx
MOS Inverters Switching Characterstics and interconnect Effects-converted.pptxMOS Inverters Switching Characterstics and interconnect Effects-converted.pptx
MOS Inverters Switching Characterstics and interconnect Effects-converted.pptx
 
lecture 10 - electrical machines - dc to dc converters 1.pptx
lecture 10 - electrical machines - dc to dc converters 1.pptxlecture 10 - electrical machines - dc to dc converters 1.pptx
lecture 10 - electrical machines - dc to dc converters 1.pptx
 
PCB Layout guidelines.pdf
PCB Layout guidelines.pdfPCB Layout guidelines.pdf
PCB Layout guidelines.pdf
 
Unit no. 5 cmos logic design
Unit no. 5 cmos logic designUnit no. 5 cmos logic design
Unit no. 5 cmos logic design
 
Advd lecture 08 -inverte rpart3
Advd   lecture 08 -inverte rpart3Advd   lecture 08 -inverte rpart3
Advd lecture 08 -inverte rpart3
 
MY PROJECT-automatic load sharing of transformer by using GSM tecnique.
MY PROJECT-automatic load sharing of transformer by using GSM tecnique.MY PROJECT-automatic load sharing of transformer by using GSM tecnique.
MY PROJECT-automatic load sharing of transformer by using GSM tecnique.
 
POWER CONSUMPTION AT CIRCUIT OR LOGIC LEVEL IN CIRCUIT
POWER CONSUMPTION AT CIRCUIT OR LOGIC LEVEL IN CIRCUITPOWER CONSUMPTION AT CIRCUIT OR LOGIC LEVEL IN CIRCUIT
POWER CONSUMPTION AT CIRCUIT OR LOGIC LEVEL IN CIRCUIT
 
Power Electronics- Power Semiconductor devices.pptx
Power Electronics- Power Semiconductor devices.pptxPower Electronics- Power Semiconductor devices.pptx
Power Electronics- Power Semiconductor devices.pptx
 
Low power embedded system design
Low power embedded system designLow power embedded system design
Low power embedded system design
 
CMOS Logic Circuits
CMOS Logic CircuitsCMOS Logic Circuits
CMOS Logic Circuits
 
IGBT.ppt
IGBT.pptIGBT.ppt
IGBT.ppt
 
Design_of_Power_Transformers.ppt
Design_of_Power_Transformers.pptDesign_of_Power_Transformers.ppt
Design_of_Power_Transformers.ppt
 
Low power in vlsi with upf basics part 1
Low power in vlsi with upf basics part 1Low power in vlsi with upf basics part 1
Low power in vlsi with upf basics part 1
 
3-Anandi.ppt
3-Anandi.ppt3-Anandi.ppt
3-Anandi.ppt
 
LPVLSI.ppt
LPVLSI.pptLPVLSI.ppt
LPVLSI.ppt
 
Anandi.ppt
Anandi.pptAnandi.ppt
Anandi.ppt
 

Mais de Rajesh Tiwary

Diufferential amplifier characteistics.pdf
Diufferential amplifier characteistics.pdfDiufferential amplifier characteistics.pdf
Diufferential amplifier characteistics.pdfRajesh Tiwary
 
diode connected NMOSdocx.pdf
diode connected NMOSdocx.pdfdiode connected NMOSdocx.pdf
diode connected NMOSdocx.pdfRajesh Tiwary
 
current mirror cascode.pdf
current mirror cascode.pdfcurrent mirror cascode.pdf
current mirror cascode.pdfRajesh Tiwary
 
Biased Current mirror variation with Vdd.pdf
Biased Current mirror variation with Vdd.pdfBiased Current mirror variation with Vdd.pdf
Biased Current mirror variation with Vdd.pdfRajesh Tiwary
 
Current mirror variation with Vdd.pdf
Current mirror variation with Vdd.pdfCurrent mirror variation with Vdd.pdf
Current mirror variation with Vdd.pdfRajesh Tiwary
 
Current mirror variation with Vo.pdf
Current mirror variation with Vo.pdfCurrent mirror variation with Vo.pdf
Current mirror variation with Vo.pdfRajesh Tiwary
 

Mais de Rajesh Tiwary (10)

intro.pdf
intro.pdfintro.pdf
intro.pdf
 
Diufferential amplifier characteistics.pdf
Diufferential amplifier characteistics.pdfDiufferential amplifier characteistics.pdf
Diufferential amplifier characteistics.pdf
 
diode connected NMOSdocx.pdf
diode connected NMOSdocx.pdfdiode connected NMOSdocx.pdf
diode connected NMOSdocx.pdf
 
current mirror cascode.pdf
current mirror cascode.pdfcurrent mirror cascode.pdf
current mirror cascode.pdf
 
Biased Current mirror variation with Vdd.pdf
Biased Current mirror variation with Vdd.pdfBiased Current mirror variation with Vdd.pdf
Biased Current mirror variation with Vdd.pdf
 
Current mirror variation with Vdd.pdf
Current mirror variation with Vdd.pdfCurrent mirror variation with Vdd.pdf
Current mirror variation with Vdd.pdf
 
Current mirror variation with Vo.pdf
Current mirror variation with Vo.pdfCurrent mirror variation with Vo.pdf
Current mirror variation with Vo.pdf
 
Lect1 rtos
Lect1 rtosLect1 rtos
Lect1 rtos
 
PYthon
PYthonPYthon
PYthon
 
Chap4 liu
Chap4 liuChap4 liu
Chap4 liu
 

Último

Clutches and brkesSelect any 3 position random motion out of real world and d...
Clutches and brkesSelect any 3 position random motion out of real world and d...Clutches and brkesSelect any 3 position random motion out of real world and d...
Clutches and brkesSelect any 3 position random motion out of real world and d...sahb78428
 
Nodal seismic construction requirements.pptx
Nodal seismic construction requirements.pptxNodal seismic construction requirements.pptx
Nodal seismic construction requirements.pptxwendy cai
 
sdfsadopkjpiosufoiasdoifjasldkjfl a asldkjflaskdjflkjsdsdf
sdfsadopkjpiosufoiasdoifjasldkjfl a asldkjflaskdjflkjsdsdfsdfsadopkjpiosufoiasdoifjasldkjfl a asldkjflaskdjflkjsdsdf
sdfsadopkjpiosufoiasdoifjasldkjfl a asldkjflaskdjflkjsdsdfJulia Kaye
 
Power System electrical and electronics .pptx
Power System electrical and electronics .pptxPower System electrical and electronics .pptx
Power System electrical and electronics .pptxMUKULKUMAR210
 
دليل تجارب الاسفلت المختبرية - Asphalt Experiments Guide Laboratory
دليل تجارب الاسفلت المختبرية - Asphalt Experiments Guide Laboratoryدليل تجارب الاسفلت المختبرية - Asphalt Experiments Guide Laboratory
دليل تجارب الاسفلت المختبرية - Asphalt Experiments Guide LaboratoryBahzad5
 
me3493 manufacturing technology unit 1 Part A
me3493 manufacturing technology unit 1 Part Ame3493 manufacturing technology unit 1 Part A
me3493 manufacturing technology unit 1 Part Akarthi keyan
 
Gender Bias in Engineer, Honors 203 Project
Gender Bias in Engineer, Honors 203 ProjectGender Bias in Engineer, Honors 203 Project
Gender Bias in Engineer, Honors 203 Projectreemakb03
 
Basic Principle of Electrochemical Sensor
Basic Principle of  Electrochemical SensorBasic Principle of  Electrochemical Sensor
Basic Principle of Electrochemical SensorTanvir Moin
 
Design of Clutches and Brakes in Design of Machine Elements.pptx
Design of Clutches and Brakes in Design of Machine Elements.pptxDesign of Clutches and Brakes in Design of Machine Elements.pptx
Design of Clutches and Brakes in Design of Machine Elements.pptxYogeshKumarKJMIT
 
How to Write a Good Scientific Paper.pdf
How to Write a Good Scientific Paper.pdfHow to Write a Good Scientific Paper.pdf
How to Write a Good Scientific Paper.pdfRedhwan Qasem Shaddad
 
Lecture 1: Basics of trigonometry (surveying)
Lecture 1: Basics of trigonometry (surveying)Lecture 1: Basics of trigonometry (surveying)
Lecture 1: Basics of trigonometry (surveying)Bahzad5
 
ASME BPVC 2023 Section I para leer y entender
ASME BPVC 2023 Section I para leer y entenderASME BPVC 2023 Section I para leer y entender
ASME BPVC 2023 Section I para leer y entenderjuancarlos286641
 
Guardians and Glitches: Navigating the Duality of Gen AI in AppSec
Guardians and Glitches: Navigating the Duality of Gen AI in AppSecGuardians and Glitches: Navigating the Duality of Gen AI in AppSec
Guardians and Glitches: Navigating the Duality of Gen AI in AppSecTrupti Shiralkar, CISSP
 
Test of Significance of Large Samples for Mean = µ.pptx
Test of Significance of Large Samples for Mean = µ.pptxTest of Significance of Large Samples for Mean = µ.pptx
Test of Significance of Large Samples for Mean = µ.pptxHome
 
cloud computing notes for anna university syllabus
cloud computing notes for anna university syllabuscloud computing notes for anna university syllabus
cloud computing notes for anna university syllabusViolet Violet
 
Mohs Scale of Hardness, Hardness Scale.pptx
Mohs Scale of Hardness, Hardness Scale.pptxMohs Scale of Hardness, Hardness Scale.pptx
Mohs Scale of Hardness, Hardness Scale.pptxKISHAN KUMAR
 

Último (20)

Clutches and brkesSelect any 3 position random motion out of real world and d...
Clutches and brkesSelect any 3 position random motion out of real world and d...Clutches and brkesSelect any 3 position random motion out of real world and d...
Clutches and brkesSelect any 3 position random motion out of real world and d...
 
Nodal seismic construction requirements.pptx
Nodal seismic construction requirements.pptxNodal seismic construction requirements.pptx
Nodal seismic construction requirements.pptx
 
Litature Review: Research Paper work for Engineering
Litature Review: Research Paper work for EngineeringLitature Review: Research Paper work for Engineering
Litature Review: Research Paper work for Engineering
 
Lecture 2 .pptx
Lecture 2                            .pptxLecture 2                            .pptx
Lecture 2 .pptx
 
sdfsadopkjpiosufoiasdoifjasldkjfl a asldkjflaskdjflkjsdsdf
sdfsadopkjpiosufoiasdoifjasldkjfl a asldkjflaskdjflkjsdsdfsdfsadopkjpiosufoiasdoifjasldkjfl a asldkjflaskdjflkjsdsdf
sdfsadopkjpiosufoiasdoifjasldkjfl a asldkjflaskdjflkjsdsdf
 
Power System electrical and electronics .pptx
Power System electrical and electronics .pptxPower System electrical and electronics .pptx
Power System electrical and electronics .pptx
 
دليل تجارب الاسفلت المختبرية - Asphalt Experiments Guide Laboratory
دليل تجارب الاسفلت المختبرية - Asphalt Experiments Guide Laboratoryدليل تجارب الاسفلت المختبرية - Asphalt Experiments Guide Laboratory
دليل تجارب الاسفلت المختبرية - Asphalt Experiments Guide Laboratory
 
Lecture 4 .pdf
Lecture 4                              .pdfLecture 4                              .pdf
Lecture 4 .pdf
 
me3493 manufacturing technology unit 1 Part A
me3493 manufacturing technology unit 1 Part Ame3493 manufacturing technology unit 1 Part A
me3493 manufacturing technology unit 1 Part A
 
Gender Bias in Engineer, Honors 203 Project
Gender Bias in Engineer, Honors 203 ProjectGender Bias in Engineer, Honors 203 Project
Gender Bias in Engineer, Honors 203 Project
 
Basic Principle of Electrochemical Sensor
Basic Principle of  Electrochemical SensorBasic Principle of  Electrochemical Sensor
Basic Principle of Electrochemical Sensor
 
Design of Clutches and Brakes in Design of Machine Elements.pptx
Design of Clutches and Brakes in Design of Machine Elements.pptxDesign of Clutches and Brakes in Design of Machine Elements.pptx
Design of Clutches and Brakes in Design of Machine Elements.pptx
 
How to Write a Good Scientific Paper.pdf
How to Write a Good Scientific Paper.pdfHow to Write a Good Scientific Paper.pdf
How to Write a Good Scientific Paper.pdf
 
Lecture 1: Basics of trigonometry (surveying)
Lecture 1: Basics of trigonometry (surveying)Lecture 1: Basics of trigonometry (surveying)
Lecture 1: Basics of trigonometry (surveying)
 
Présentation IIRB 2024 Chloe Dufrane.pdf
Présentation IIRB 2024 Chloe Dufrane.pdfPrésentation IIRB 2024 Chloe Dufrane.pdf
Présentation IIRB 2024 Chloe Dufrane.pdf
 
ASME BPVC 2023 Section I para leer y entender
ASME BPVC 2023 Section I para leer y entenderASME BPVC 2023 Section I para leer y entender
ASME BPVC 2023 Section I para leer y entender
 
Guardians and Glitches: Navigating the Duality of Gen AI in AppSec
Guardians and Glitches: Navigating the Duality of Gen AI in AppSecGuardians and Glitches: Navigating the Duality of Gen AI in AppSec
Guardians and Glitches: Navigating the Duality of Gen AI in AppSec
 
Test of Significance of Large Samples for Mean = µ.pptx
Test of Significance of Large Samples for Mean = µ.pptxTest of Significance of Large Samples for Mean = µ.pptx
Test of Significance of Large Samples for Mean = µ.pptx
 
cloud computing notes for anna university syllabus
cloud computing notes for anna university syllabuscloud computing notes for anna university syllabus
cloud computing notes for anna university syllabus
 
Mohs Scale of Hardness, Hardness Scale.pptx
Mohs Scale of Hardness, Hardness Scale.pptxMohs Scale of Hardness, Hardness Scale.pptx
Mohs Scale of Hardness, Hardness Scale.pptx
 

Power dissipation cmos

  • 2. Outline • Motivation to estimate power dissipation • Sources of power dissipation • Dynamic power dissipation • Static power dissipation • Metrics • Conclusion
  • 3. Need to estimate power dissipation Power dissipation affects • Performance • Reliability • Packaging • Cost • Portability
  • 4. Where Does Power Go in CMOS? • Dynamic Power Consumption Charging and Discharging Capacitors • Short Circuit Currents Short Circuit Path between Supply Rails during Switching • Leakage Leaking diodes and transistors
  • 5. Node Transition Activity and Power •Due to charging and discharging of capacitance Consider switching a CMOS gate for N clock cycles E N =  2  nN C L V dd EN : the energy consumed for N clock cycles n(N): the number o f 0->1 transition in N clock cycles P avg lim N  E N N -------- f clk =  nN N  lim ------------   C   N  L V dd  2 f clk =  = lim  0  1 nN ------------ N N   P avg =   C 0  1 L  2 f V dd clk 
  • 6. Activity factors of basic gates • AND • OR • XOR A B A B   (1 p p ) p p (1 )(1 )[1 (1 )(1 )] A B A B    p  p   p  p [1 ( 2 )]( 2 ) A B A B A B A B    p  p  p p p  p  p p
  • 7. Dynamic Power dissipation • Power reduced by reducing Vdd, f, C and also activity • A signal transition can be classified into two categories  a functional transition and  a glitch
  • 8. Glitch Power Dissipation • Glitches are temporary changes in the value of the output – unnecessary transitions • They are caused due to the skew in the input signals to a gate • Glitch power dissipation accounts for 15% – 20 % of the global power • Basic contributes of hazards to power dissipation are – Hazard generation – Hazard propagation
  • 9. Glitch Power Dissipation • P = 1/2 .CL.Vdd . (Vdd – Vmin) ; Vmin : min voltage swing at the output • Glitch power dissipation is dependent on – Output load – Input pattern – Input slope
  • 11. Glitch Power Dissipation • Hazard generation can be reduced by gate sizing and path balancing techniques • Hazard propagation can be reduced by using less number of inverters which tend to amplify and propagate glitches
  • 12. Short Circuit Power Dissipation • Short circuit current occurs during signal transitions when both the NMOS and PMOS are ON and there is a direct path between Vdd and GND • Also called crowbar current • Accounts for more than 20% of total power dissipation • As clock frequency increases transitions increase consequently short circuit power dissipation increases • Can be reduced : – faster input and slower output – Vdd <= Vtn + |Vtp| • So both NMOS and PMOS are not on at the same time
  • 14. Static Power Consumption Vin=5V Vout CL Vdd Istat Pstat = P(In=1).Vdd . Istat • Dominates over dynamic consumption Wasted energy … Should be avoided in almost all cases • Not a function of switching frequency
  • 15. Static Power Dissipation • Power dissipation occurring when device is in standby mode • As technology scales this becomes significant • Leakage power dissipation • Components: – Reverse biased p-n junction – Sub threshold leakage – DIBL leakage – Channel punch through – GIDL Leakage – Narrow width effect – Oxide leakage – Hot carrier tunneling effect
  • 19. New Problem: Gate Leakage „Now about 20-30% of all leakage, and growing „Gate oxide is so thin, electrons tunnel thru it… „NMOS is much worse than PMOS
  • 20. Principles for Power Reduction • Prime choice: Reduce voltage! – Recent years have seen an acceleration in supply voltage reduction – Design at very low voltages still open question (0.6 … 0.9 V by 2010!) • Reduce switching activity Logic synthesis Clock gating • Reduce physical capacitance – Proper Device Sizing – Good layout
  • 21. Factors affecting leakage power • Temperature – Sub-threshold current increases exponentially • Reduction in Vt • Increase in thermal voltage – BTBT increases due to band gap narrowing – Gate leakage is insensitive to temperature change
  • 22. Factors affecting leakage power • Gate oxide thickness – Sub-threshold current decreases in long channel transistors and increases in short channel – BTBT is insensitive – Gate leakage increases as thickness reduces
  • 23. Solutions • MTCMOS • Dual Vt • Dual Vt domino logic • Adaptive Body Bias • Transistor stacking
  • 24. Metrics • Power Delay product • Energy Delay Product – Average energy per instruction x average inter instruction delay • Cunit_area – Capacitance per unit area
  • 25. Summary „Power Dissipation is already a prime design constraint „Low-power design requires operation at lowest possible voltage and clock speed „Low-power design requires optimization at
  • 26. Conclusion • Power dissipation is unavoidable especially as technology scales down • Techniques must be devised to reduce power dissipation • Techniques must be devised to accurately estimate the power dissipation • Estimation and modeling of the sources of power dissipation for simulation purposes