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Reversible Logic Synthesis and RevKit

A talk on reversible logic synthesis and RevKit that I gave at the summer school which was co-organized with the Reversible Computation 2017 conference.

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Reversible Logic Synthesis and RevKit

  1. 1. Reversible logic synthesis and RevKit Mathias Soeken Integrated Systems Laboratory, EPFL, Switzerland mathias.soeken@epfl.ch msoeken.github.io msoeken/cirkit
  2. 2. ǚ ms | two Introduction and background Reversible logic synthesis Introduction into RevKit
  3. 3. ǚ ms | three Introduction and background Reversible logic synthesis Introduction into RevKit
  4. 4. ǚ ms | four Quantum computing is getting real 17-qubit quantum computer from IBM based on superconducting qubits (16-qubit version available via cloud service) 9-qubit quantum computer from Google based on superconducting circuits 5-qubit quantum computer at University of Maryland based on ion traps Microsoft is investigating topological quantum computers Intel is investigating silicon-based qubits
  5. 5. ǚ ms | four Quantum computing is getting real 17-qubit quantum computer from IBM based on superconducting qubits (16-qubit version available via cloud service) 9-qubit quantum computer from Google based on superconducting circuits 5-qubit quantum computer at University of Maryland based on ion traps Microsoft is investigating topological quantum computers Intel is investigating silicon-based qubits “Quantum supremacy” experiment may be possible with ≈50 qubits (45-qubit simulation has been performed classically) Smallest practical problems require ≈100 (logical) qubits
  6. 6. ǚ ms | five Challenges in logic synthesis for quantum computing 1. Quantum computers process qubits not bits Classical half-adder x y s c Quantum half-adder |x |y |0 |x |s |c
  7. 7. ǚ ms | five Challenges in logic synthesis for quantum computing 1. Quantum computers process qubits not bits Classical half-adder 0 1 1 0 Quantum half-adder 1/ √ 2(|0 + |1 ) 1/ √ 2(|0 + |1 ) |0 1/2(|000 + |010 + |110 + |101 )
  8. 8. ǚ ms | five Challenges in logic synthesis for quantum computing 1. Quantum computers process qubits not bits 2. All qubit operations, called quantum gates, must be reversible Classical half-adder x y s c Quantum half-adder |x |y |0 |x |s |c
  9. 9. ǚ ms | five Challenges in logic synthesis for quantum computing 1. Quantum computers process qubits not bits 2. All qubit operations, called quantum gates, must be reversible Classical half-adder x y s c Quantum half-adder |x |y |0 |x |s |c
  10. 10. ǚ ms | five Challenges in logic synthesis for quantum computing 1. Quantum computers process qubits not bits 2. All qubit operations, called quantum gates, must be reversible 3. Standard gate library for today’s physical quantum computers is non-trivial Classical half-adder x y s c Quantum half-adder |x |y |0 |x |s |c
  11. 11. ǚ ms | five Challenges in logic synthesis for quantum computing 1. Quantum computers process qubits not bits 2. All qubit operations, called quantum gates, must be reversible 3. Standard gate library for today’s physical quantum computers is non-trivial 4. Circuit is not allowed to produce intermediate results, called garbage qubits Classical half-adder x y s c Quantum half-adder |x |y |0 |x |s |c
  12. 12. ǚ ms | six Reversible gates x1 ¯x1 NOT x1 x2 x1 x1 ⊕ x2 CNOT x1 x2 x3 x1 x2 x3 ⊕ x1x2 Toffoli
  13. 13. ǚ ms | six Reversible gates x1 ¯x1 NOT x1 x2 x1 x1 ⊕ x2 CNOT x1 x2 x3 x1 x2 x3 ⊕ x1x2 Toffoli x1 x2 x3 f x1 x2 x3 ⊕ f (x1, x2) Single-target
  14. 14. ǚ ms | six Reversible gates x1 ¯x1 NOT x1 x2 x1 x1 ⊕ x2 CNOT x1 x2 x3 x1 x2 x3 ⊕ x1x2 Toffoli x1 x2 x3 f x1 x2 x3 ⊕ f (x1, x2) Single-target x1 x2 x3 x4 x5 x1 x2 x3 x4 x5 ⊕ x1 ¯x2x3 ¯x4 Multiple-controlled Toffoli
  15. 15. ǚ ms | six Reversible gates x1 ¯x1 NOT x1 x2 x1 x1 ⊕ x2 CNOT x1 x2 x3 x1 x2 x3 ⊕ x1x2 Toffoli x1 x2 x3 f x1 x2 x3 ⊕ f (x1, x2) Single-target x1 x2 x3 x4 x5 x1 x2 x3 x4 x5 ⊕ x1 ¯x2x3 ¯x4 Multiple-controlled Toffoli x1 x2 x3 0 x1 x2 x1 ⊕ x2 ⊕ x3 x1x2x3 Full adder
  16. 16. ǚ ms | seven Quantum gates Qubit is vector |ϕ = ( α β ) with |α2| + |β2| = 1. Classical 0 is |0 = ( 1 0 ); Classical 1 is |1 = ( 0 1 )
  17. 17. ǚ ms | seven Quantum gates Qubit is vector |ϕ = ( α β ) with |α2| + |β2| = 1. Classical 0 is |0 = ( 1 0 ); Classical 1 is |1 = ( 0 1 ) |ϕ1 |ϕ2 1 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 |ϕ1ϕ2 CNOT |ϕ H 1√ 2 1 1 1 −1 |ϕ Hadamard |ϕ T 1 0 0 e iπ 4 |ϕ T
  18. 18. ǚ ms | eight Composing quantum gates Applying a quantum gate to a quantum state (matrix-vector multiplication) |ϕ = ( α β ) U U|ϕ
  19. 19. ǚ ms | eight Composing quantum gates Applying a quantum gate to a quantum state (matrix-vector multiplication) |ϕ = ( α β ) U U|ϕ Applying quantum gates in sequence (matrix product) |ϕ = ( α β ) U1 U2 (U2U1)|ϕ
  20. 20. ǚ ms | eight Composing quantum gates Applying a quantum gate to a quantum state (matrix-vector multiplication) |ϕ = ( α β ) U U|ϕ Applying quantum gates in sequence (matrix product) |ϕ = ( α β ) U1 U2 (U2U1)|ϕ Applying quantum gates in parallel (Kronecker product) |ϕ1 = α1 β1 |ϕ2 = α2 β2 U1 U2 (U1 ⊗ U2)|ϕ1ϕ2
  21. 21. ǚ ms | nine Mapping Toffoli gates x1 x2 x3 = H T T T T† T† T† T H x1 x2 x3 ⊕ x1x2 Clifford+T circuit [Amy et al., TCAD 32, 2013]
  22. 22. ǚ ms | nine Mapping Toffoli gates x1 x2 x3 = H T T T T† T† T† T H x1 x2 x3 ⊕ x1x2 Clifford+T circuit [Amy et al., TCAD 32, 2013] x1 x2 x3 x4 w x5 = x1 x2 x3 x4 w x5 ⊕ x1x2x3x4
  23. 23. ǚ ms | nine Mapping Toffoli gates x1 x2 x3 = H T T T T† T† T† T H x1 x2 x3 ⊕ x1x2 Clifford+T circuit [Amy et al., TCAD 32, 2013] x1 x2 x3 x4 w x5 = x1 x2 x3 x4 w x5 ⊕ x1x2x3x4 Costs are number of qubits and number of T gates
  24. 24. ǚ ms | ten RevKit Open source C++ framework for reversible logic synthesis (since 2009)
  25. 25. ǚ ms | ten RevKit Open source C++ framework for reversible logic synthesis (since 2009) Implemented as add-on in CirKit, an open source C++ framework for logic synthesis
  26. 26. ǚ ms | ten RevKit Open source C++ framework for reversible logic synthesis (since 2009) Implemented as add-on in CirKit, an open source C++ framework for logic synthesis Provides command-line interface shell (CLI) and API
  27. 27. ǚ ms | ten RevKit Open source C++ framework for reversible logic synthesis (since 2009) Implemented as add-on in CirKit, an open source C++ framework for logic synthesis Provides command-line interface shell (CLI) and API CLI allows batch processing and can be used via Python API
  28. 28. ǚ ms | ten RevKit Open source C++ framework for reversible logic synthesis (since 2009) Implemented as add-on in CirKit, an open source C++ framework for logic synthesis Provides command-line interface shell (CLI) and API CLI allows batch processing and can be used via Python API No Python API for C++ API
  29. 29. ǚ ms | ten RevKit Open source C++ framework for reversible logic synthesis (since 2009) Implemented as add-on in CirKit, an open source C++ framework for logic synthesis Provides command-line interface shell (CLI) and API CLI allows batch processing and can be used via Python API No Python API for C++ API Implement core functionality in C++ and expose it via CLI commands
  30. 30. ǚ ms | eleven RevKit [Installation] Obtain from Github: github.com/msoeken/cirkit
  31. 31. ǚ ms | eleven RevKit [Installation] Obtain from Github: github.com/msoeken/cirkit Works smoothly on modern Mac OS and Linux distributions
  32. 32. ǚ ms | eleven RevKit [Installation] Obtain from Github: github.com/msoeken/cirkit Works smoothly on modern Mac OS and Linux distributions Works on Windows OS using Ubuntu subsystem
  33. 33. ǚ ms | eleven RevKit [Installation] Obtain from Github: github.com/msoeken/cirkit Works smoothly on modern Mac OS and Linux distributions Works on Windows OS using Ubuntu subsystem Install dependencies via package manager (in Mac OS, e.g., brew)
  34. 34. ǚ ms | eleven RevKit [Installation] Obtain from Github: github.com/msoeken/cirkit Works smoothly on modern Mac OS and Linux distributions Works on Windows OS using Ubuntu subsystem Install dependencies via package manager (in Mac OS, e.g., brew) More details: msoeken.github.io/revkit.html
  35. 35. ǚ ms | twelve RevKit [Generalities] RevKit is commands plus stores Stores for each relevant data structure: e.g., reversible circuits, reversible truth tables, AND-inverter graphs, binary decision diagrams, . . . Stores can contain several instances, commands work on current element revkit> read_real -s "t a b c, f b a c" revkit> store -c [i] circuits in store: * 0: 3 lines, 2 gates revkit> tof revkit> ps -c Lines: 3 Gates: 4 T-count: 14 Logic qubits: 4 revkit> write_liquid file.fs
  36. 36. ǚ ms | thirteen Introduction and background Reversible logic synthesis Introduction into RevKit
  37. 37. ǚ ms | fourteen Reversible logic synthesis Boolean function −−−−−−→ embedding Rev. function −−−−−−→ synthesis Rev. circuit What is the input representation? Is the input representation reversible or irreversible? Explicit vs. implicit embedding
  38. 38. ǚ ms | fourteen Reversible logic synthesis Boolean function optimum −−−−−−→ embedding Rev. function −−−−−−→ synthesis Rev. circuit What is the input representation? Is the input representation reversible or irreversible? Explicit vs. implicit embedding
  39. 39. ǚ ms | fourteen Reversible logic synthesis Boolean function optimum −−−−−−→ embedding Rev. function ancilla-free −−−−−−→ synthesis Rev. circuit What is the input representation? Is the input representation reversible or irreversible? Explicit vs. implicit embedding
  40. 40. ǚ ms | fifteen Embedding of irreversible functions c x y c s 0 0 0 0 0 1 0 1 1 0 0 1 1 1 1 0
  41. 41. ǚ ms | fifteen Embedding of irreversible functions c x y c s x 0 0 0 0 0 0 1 0 1 0 1 0 0 1 1 1 1 1 0 1 Add additional outputs to disambiguate duplicate output pattern, preferably inputs
  42. 42. ǚ ms | fifteen Embedding of irreversible functions c x y c s x 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 1 Add additional outputs to disambiguate duplicate output pattern, preferably inputs Add additional inputs to match number of outputs, preferably constants
  43. 43. ǚ ms | fifteen Embedding of irreversible functions c x y c s x 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 1 1 0 0 1 0 1 1 1 0 1 1 1 Add additional outputs to disambiguate duplicate output pattern, preferably inputs Add additional inputs to match number of outputs, preferably constants Optional: assign output pattern to new input pattern
  44. 44. ǚ ms | fifteen Embedding of irreversible functions c x y c s x 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 1 1 0 0 0 1 0 1 0 1 1 0 1 1 1 1 1 Add additional outputs to disambiguate duplicate output pattern, preferably inputs Add additional inputs to match number of outputs, preferably constants Optional: assign output pattern to new input pattern
  45. 45. ǚ ms | fifteen Embedding of irreversible functions c x y c s x 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 1 1 0 0 1 1 0 1 0 1 1 0 0 1 1 0 0 0 1 1 1 1 1 1 1 Add additional outputs to disambiguate duplicate output pattern, preferably inputs Add additional inputs to match number of outputs, preferably constants Optional: assign output pattern to new input pattern
  46. 46. ǚ ms | fifteen Embedding of irreversible functions c x y c s x 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 1 1 0 0 1 1 0 1 0 1 1 0 0 1 1 0 0 0 1 1 1 1 1 1 1 Add additional outputs to disambiguate duplicate output pattern, preferably inputs Add additional inputs to match number of outputs, preferably constants Optional: assign output pattern to new input pattern Upper bound: Number of original inputs + number of original outputs (all inputs are preserved)
  47. 47. ǚ ms | fifteen Embedding of irreversible functions c x y c s x 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 1 1 0 0 1 1 0 1 0 1 1 0 0 1 1 0 0 0 1 1 1 1 1 1 1 Add additional outputs to disambiguate duplicate output pattern, preferably inputs Add additional inputs to match number of outputs, preferably constants Optional: assign output pattern to new input pattern Upper bound: Number of original inputs + number of original outputs (all inputs are preserved) Computing whether optimum embedding is possible with additional lines is coNP-hard
  48. 48. ǚ ms | sixteen Reversible synthesis classification line opt. gate opt. nonreversible func. reversible func. SAT-based Enumerative Transformation-based Cycle-based Decomposition-based Metaheuristic Greedy ESOP-based Hierarchical Building block functionalstructural
  49. 49. ǚ ms | seventeen SAT-based exact synthesis Idea: Solve question “does there exist a reversible circuit realizing f with r gates?” as SAT problem
  50. 50. ǚ ms | seventeen SAT-based exact synthesis Idea: Solve question “does there exist a reversible circuit realizing f with r gates?” as SAT problem Try solving question starting from r = 0; increase r until solution is found
  51. 51. ǚ ms | seventeen SAT-based exact synthesis Idea: Solve question “does there exist a reversible circuit realizing f with r gates?” as SAT problem Try solving question starting from r = 0; increase r until solution is found Solution can be extracted from satisfying SAT assignment
  52. 52. ǚ ms | seventeen SAT-based exact synthesis Idea: Solve question “does there exist a reversible circuit realizing f with r gates?” as SAT problem Try solving question starting from r = 0; increase r until solution is found Solution can be extracted from satisfying SAT assignment Only applicable to functions with small number of variables (≈ 7) that require few gates
  53. 53. ǚ ms | seventeen SAT-based exact synthesis Idea: Solve question “does there exist a reversible circuit realizing f with r gates?” as SAT problem Try solving question starting from r = 0; increase r until solution is found Solution can be extracted from satisfying SAT assignment Only applicable to functions with small number of variables (≈ 7) that require few gates RevKit: exs
  54. 54. ǚ ms | eighteen Reversible synthesis classification line opt. gate opt. nonreversible func. reversible func. SAT-based Enumerative Transformation-based Cycle-based Decomposition-based Metaheuristic Greedy ESOP-based Hierarchical Building block functionalstructural
  55. 55. ǚ ms | nineteen Explicit transformation-based synthesis x1x2x3 y1y2y3 000 111 001 000 010 110 011 100 100 010 101 001 110 011 111 101 x1 y1 x2 y2 x3 y3 Apply gates adjust output pattern with input pattern By visiting input patterns in numeric order, and by only using positive controlled Toffoli gates, it is ensured that no previous patterns are modified RevKit: tbs D. Michael Miller, Dmitri Maslov, Gerhard W. Dueck: A transformation based algorithm for reversible logic synthesis, DAC 40 (2003), 318–323.
  56. 56. ǚ ms | nineteen Explicit transformation-based synthesis x1x2x3 y1y2y3 000 111 001 000 010 110 011 100 100 010 101 001 110 011 111 101 x1 y1 x2 y2 x3 y3 Apply gates adjust output pattern with input pattern By visiting input patterns in numeric order, and by only using positive controlled Toffoli gates, it is ensured that no previous patterns are modified RevKit: tbs D. Michael Miller, Dmitri Maslov, Gerhard W. Dueck: A transformation based algorithm for reversible logic synthesis, DAC 40 (2003), 318–323.
  57. 57. ǚ ms | nineteen Explicit transformation-based synthesis x1x2x3 y1y2y3 000 000 001 111 010 001 011 011 100 101 101 110 110 100 111 010 x1 y1 x2 y2 x3 y3 Apply gates adjust output pattern with input pattern By visiting input patterns in numeric order, and by only using positive controlled Toffoli gates, it is ensured that no previous patterns are modified RevKit: tbs D. Michael Miller, Dmitri Maslov, Gerhard W. Dueck: A transformation based algorithm for reversible logic synthesis, DAC 40 (2003), 318–323.
  58. 58. ǚ ms | nineteen Explicit transformation-based synthesis x1x2x3 y1y2y3 000 000 001 001 010 111 011 101 100 011 101 110 110 100 111 010 x1 y1 x2 y2 x3 y3 Apply gates adjust output pattern with input pattern By visiting input patterns in numeric order, and by only using positive controlled Toffoli gates, it is ensured that no previous patterns are modified RevKit: tbs D. Michael Miller, Dmitri Maslov, Gerhard W. Dueck: A transformation based algorithm for reversible logic synthesis, DAC 40 (2003), 318–323.
  59. 59. ǚ ms | nineteen Explicit transformation-based synthesis x1x2x3 y1y2y3 000 000 001 001 010 010 011 101 100 110 101 011 110 100 111 111 x1 y1 x2 y2 x3 y3 Apply gates adjust output pattern with input pattern By visiting input patterns in numeric order, and by only using positive controlled Toffoli gates, it is ensured that no previous patterns are modified RevKit: tbs D. Michael Miller, Dmitri Maslov, Gerhard W. Dueck: A transformation based algorithm for reversible logic synthesis, DAC 40 (2003), 318–323.
  60. 60. ǚ ms | nineteen Explicit transformation-based synthesis x1x2x3 y1y2y3 000 000 001 001 010 010 011 011 100 100 101 111 110 110 111 101 x1 y1 x2 y2 x3 y3 Apply gates adjust output pattern with input pattern By visiting input patterns in numeric order, and by only using positive controlled Toffoli gates, it is ensured that no previous patterns are modified RevKit: tbs D. Michael Miller, Dmitri Maslov, Gerhard W. Dueck: A transformation based algorithm for reversible logic synthesis, DAC 40 (2003), 318–323.
  61. 61. ǚ ms | nineteen Explicit transformation-based synthesis x1x2x3 y1y2y3 000 000 001 001 010 010 011 011 100 100 101 101 110 110 111 111 x1 y1 x2 y2 x3 y3 Apply gates adjust output pattern with input pattern By visiting input patterns in numeric order, and by only using positive controlled Toffoli gates, it is ensured that no previous patterns are modified RevKit: tbs D. Michael Miller, Dmitri Maslov, Gerhard W. Dueck: A transformation based algorithm for reversible logic synthesis, DAC 40 (2003), 318–323.
  62. 62. ǚ ms | twenty RevKit [Synthesis commands] line opt. gate opt. nonreversible func. reversible func. SAT-based exs Enumerative Transformation-based tbs, rms, qbs Cycle-based cyclebs Decomposition-based dbs Metaheuristic Greedy ESOP-based esopbs Hierarchical cbs, dxs, hdbs, lhrs Building block functionalstructural
  63. 63. ǚ ms | twenty-one RevKit [Synthesis and formats] BDDEXPR TTXMG CIRCUIT RCBDDAIG SPEC qbsrmsdxscbs dbstbslhrs esopbs exs hdbs
  64. 64. ǚ ms | twenty-two RevKit [File formats] tikz real aiger AIG aiger pla TT verilog numpy spec spec BDD bench XMG real RCBDDCIRCUIT projectq pla qc qcode qpic quipperliquid qcverilog SPEC
  65. 65. ǚ ms | twenty-three RevKit [Functional synthesis] revkit> revgen --hwb 6 revkit> tbs revkit> dbs -n revkit> store -c [i] circuits in store: 0: 6 lines, 141 gates * 1: 6 lines, 89 gates revkit> rec [i] circuits are equivalent revkit> reverse revkit> concat -n revkit> store -c [i] circuits in store: 0: 6 lines, 141 gates 1: 6 lines, 89 gates * 2: 6 lines, 230 gates revkit> is_identity [i] circuit represents the identity function
  66. 66. ǚ ms | twenty-four Decomposition-based synthesis: idea x1 x2 ... xn−1 xn F y1 y2 yn−1 yn = x1 x2 xn−1 xn f1 z x2 xn−1 xn F z y2 yn−1 yn f2 y1 y2 ... yn−1 yn Every reversible function can be decomposed into three reversible sub-functions Tf1 (X {xi }, xi ), F , Tf2 (X {xi }, xi ), where F is a reversible function that does not change in xi , for all i RevKit: dbs A. De Vos, Y. Van Rentergem: Young subgroups for reversible computers, Adv. in Math. of Comm. 2 (2008), 183–200.
  67. 67. ǚ ms | twenty-four Decomposition-based synthesis: idea x1 x2 ... xn−1 xn F y1 y2 yn−1 yn = x1 x2 xn−1 xn f1 z x2 xn−1 xn F z y2 yn−1 yn f2 y1 y2 ... yn−1 yn Every reversible function can be decomposed into three reversible sub-functions Tf1 (X {xi }, xi ), F , Tf2 (X {xi }, xi ), where F is a reversible function that does not change in xi , for all i Recursive application of this procedure on B in order i = 1, 2, . . . , n − 1, n, yields a reversible circuit with 2n − 1 gates, where the targets are aligned in a V-shape RevKit: dbs A. De Vos, Y. Van Rentergem: Young subgroups for reversible computers, Adv. in Math. of Comm. 2 (2008), 183–200.
  68. 68. ǚ ms | twenty-five Decomposition-based synthesis: example x1 x2 x3 y1 y2 y3 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 1 1 0 1 0 0 1 1 1 1 0 1 0 1 1 1 1 0 1 0 1 1 1 1 1 0 0 A. De Vos, Y. Van Rentergem: Young subgroups for reversible computers, Adv. in Math. of Comm. 2 (2008), 183–200.
  69. 69. ǚ ms | twenty-five Decomposition-based synthesis: example x1 x2 x3 y1 y2 y3 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 0 1 0 0 1 1 1 1 1 0 1 1 0 1 0 0 0 0 1 1 1 1 1 1 0 1 0 1 1 1 0 1 1 1 1 0 1 0 0 1 1 0 1 1 1 1 1 1 0 0 1 0 0 A. De Vos, Y. Van Rentergem: Young subgroups for reversible computers, Adv. in Math. of Comm. 2 (2008), 183–200.
  70. 70. ǚ ms | twenty-five Decomposition-based synthesis: example x1 x2 x3 y1 y2 y3 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 0 1 0 0 1 1 1 1 1 0 1 1 0 1 0 0 0 0 1 1 1 1 1 1 0 1 0 1 1 1 0 1 1 1 1 0 1 0 0 1 1 0 1 1 1 1 1 1 0 0 1 0 0 A. De Vos, Y. Van Rentergem: Young subgroups for reversible computers, Adv. in Math. of Comm. 2 (2008), 183–200.
  71. 71. ǚ ms | twenty-five Decomposition-based synthesis: example x1 x2 x3 y1 y2 y3 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 0 1 0 0 1 1 1 1 1 0 1 1 0 1 0 0 1 0 0 1 1 1 1 1 1 0 1 0 1 1 1 0 1 1 1 1 0 1 0 0 1 1 0 1 1 1 1 1 1 0 0 1 0 0 A. De Vos, Y. Van Rentergem: Young subgroups for reversible computers, Adv. in Math. of Comm. 2 (2008), 183–200.
  72. 72. ǚ ms | twenty-five Decomposition-based synthesis: example x1 x2 x3 y1 y2 y3 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 0 1 0 0 1 1 1 1 1 0 1 1 0 1 0 0 1 0 0 1 1 1 1 1 1 1 0 1 0 1 1 1 0 1 1 1 1 0 1 0 0 1 1 0 1 1 1 1 1 1 0 0 1 0 0 A. De Vos, Y. Van Rentergem: Young subgroups for reversible computers, Adv. in Math. of Comm. 2 (2008), 183–200.
  73. 73. ǚ ms | twenty-five Decomposition-based synthesis: example x1 x2 x3 y1 y2 y3 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 0 1 0 0 1 1 1 1 1 0 1 1 0 1 0 0 1 0 0 1 1 1 1 1 1 1 0 1 0 1 0 1 1 0 1 1 1 1 0 1 0 0 1 1 0 1 1 1 1 1 1 0 0 1 0 0 A. De Vos, Y. Van Rentergem: Young subgroups for reversible computers, Adv. in Math. of Comm. 2 (2008), 183–200.
  74. 74. ǚ ms | twenty-five Decomposition-based synthesis: example x1 x2 x3 y1 y2 y3 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 0 1 0 0 1 1 1 1 1 0 1 1 0 1 0 0 1 0 0 1 1 1 1 1 1 1 0 1 0 0 1 0 1 1 0 1 1 1 1 0 1 0 0 1 1 0 1 1 1 1 1 1 0 0 1 0 0 A. De Vos, Y. Van Rentergem: Young subgroups for reversible computers, Adv. in Math. of Comm. 2 (2008), 183–200.
  75. 75. ǚ ms | twenty-five Decomposition-based synthesis: example x1 x2 x3 y1 y2 y3 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 0 1 0 0 1 1 1 1 1 0 1 1 0 1 0 0 1 0 0 1 1 1 1 1 1 1 0 1 0 0 1 0 1 1 0 1 1 1 1 0 1 0 0 1 1 0 1 1 1 1 1 1 0 0 1 0 0 A. De Vos, Y. Van Rentergem: Young subgroups for reversible computers, Adv. in Math. of Comm. 2 (2008), 183–200.
  76. 76. ǚ ms | twenty-five Decomposition-based synthesis: example x1 x2 x3 y1 y2 y3 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 1 0 0 1 0 1 0 1 0 1 0 0 1 0 0 1 1 1 1 1 0 1 1 0 1 0 0 1 0 0 1 1 1 1 1 1 1 0 1 0 0 1 0 1 1 0 1 1 1 1 0 1 0 0 1 1 0 1 1 1 1 1 1 0 0 1 0 0 A. De Vos, Y. Van Rentergem: Young subgroups for reversible computers, Adv. in Math. of Comm. 2 (2008), 183–200.
  77. 77. ǚ ms | twenty-five Decomposition-based synthesis: example x1 x2 x3 y1 y2 y3 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 1 0 0 1 0 1 0 1 0 1 0 0 1 0 0 1 1 1 1 1 0 1 1 0 1 0 0 1 0 0 1 1 1 1 1 1 1 0 1 0 0 1 0 1 1 0 1 1 1 1 0 1 0 0 0 1 1 0 1 1 1 1 1 1 0 0 1 0 0 A. De Vos, Y. Van Rentergem: Young subgroups for reversible computers, Adv. in Math. of Comm. 2 (2008), 183–200.
  78. 78. ǚ ms | twenty-five Decomposition-based synthesis: example x1 x2 x3 y1 y2 y3 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 1 0 0 1 0 1 0 1 0 1 0 0 1 0 0 1 1 1 1 1 0 1 1 0 1 0 0 1 0 0 1 1 1 1 1 1 1 0 1 0 0 1 0 1 1 0 1 1 1 1 0 0 1 0 0 0 1 1 0 1 1 1 1 1 1 0 0 1 0 0 A. De Vos, Y. Van Rentergem: Young subgroups for reversible computers, Adv. in Math. of Comm. 2 (2008), 183–200.
  79. 79. ǚ ms | twenty-five Decomposition-based synthesis: example x1 x2 x3 y1 y2 y3 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 1 0 0 1 0 1 0 1 1 0 1 0 0 1 0 0 1 1 1 1 1 0 1 1 0 1 0 0 1 0 0 1 1 1 1 1 1 1 0 1 0 0 1 0 1 1 0 1 1 1 1 0 0 1 0 0 0 1 1 0 1 1 1 1 1 1 0 0 1 0 0 A. De Vos, Y. Van Rentergem: Young subgroups for reversible computers, Adv. in Math. of Comm. 2 (2008), 183–200.
  80. 80. ǚ ms | twenty-five Decomposition-based synthesis: example x1 x2 x3 y1 y2 y3 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 0 1 0 0 1 1 1 1 1 0 1 1 0 1 0 0 1 0 0 1 1 1 1 1 1 1 0 1 0 0 1 0 1 1 0 1 1 1 1 0 0 1 0 0 0 1 1 0 1 1 1 1 1 1 0 0 1 0 0 A. De Vos, Y. Van Rentergem: Young subgroups for reversible computers, Adv. in Math. of Comm. 2 (2008), 183–200.
  81. 81. ǚ ms | twenty-five Decomposition-based synthesis: example x1 x2 x3 y1 y2 y3 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 0 1 0 0 1 1 1 1 0 1 0 1 1 0 1 0 0 1 0 0 1 1 1 1 1 1 1 0 1 0 0 1 0 1 1 0 1 1 1 1 0 0 1 0 0 0 1 1 0 1 1 1 1 1 1 0 0 1 0 0 A. De Vos, Y. Van Rentergem: Young subgroups for reversible computers, Adv. in Math. of Comm. 2 (2008), 183–200.
  82. 82. ǚ ms | twenty-five Decomposition-based synthesis: example x1 x2 x3 y1 y2 y3 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 0 1 0 0 1 1 0 1 1 0 1 0 1 1 0 1 0 0 1 0 0 1 1 1 1 1 1 1 0 1 0 0 1 0 1 1 0 1 1 1 1 0 0 1 0 0 0 1 1 0 1 1 1 1 1 1 0 0 1 0 0 A. De Vos, Y. Van Rentergem: Young subgroups for reversible computers, Adv. in Math. of Comm. 2 (2008), 183–200.
  83. 83. ǚ ms | twenty-five Decomposition-based synthesis: example x1 x2 x3 y1 y2 y3 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 0 1 0 0 1 1 0 1 1 0 1 0 1 1 0 1 0 0 1 0 0 1 1 1 1 1 1 1 0 1 0 0 1 0 1 1 0 1 1 1 1 0 0 1 0 0 0 1 1 0 1 1 1 1 1 1 1 0 0 1 0 0 A. De Vos, Y. Van Rentergem: Young subgroups for reversible computers, Adv. in Math. of Comm. 2 (2008), 183–200.
  84. 84. ǚ ms | twenty-five Decomposition-based synthesis: example x1 x2 x3 y1 y2 y3 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 0 1 0 0 1 1 0 1 1 0 1 0 1 1 0 1 0 0 1 0 0 1 1 1 1 1 1 1 0 1 0 0 1 0 1 1 0 1 1 1 1 0 0 1 0 0 0 1 1 0 1 1 1 1 1 1 1 1 0 0 1 0 0 A. De Vos, Y. Van Rentergem: Young subgroups for reversible computers, Adv. in Math. of Comm. 2 (2008), 183–200.
  85. 85. ǚ ms | twenty-five Decomposition-based synthesis: example x1 x2 x3 y1 y2 y3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 0 1 0 0 1 1 0 1 1 0 1 0 1 1 0 1 0 0 1 0 0 1 1 1 1 1 1 1 0 1 0 0 1 0 1 1 0 1 1 1 1 0 0 1 0 0 0 1 1 0 1 1 1 1 1 1 1 1 0 0 1 0 0 A. De Vos, Y. Van Rentergem: Young subgroups for reversible computers, Adv. in Math. of Comm. 2 (2008), 183–200.
  86. 86. ǚ ms | twenty-five Decomposition-based synthesis: example x1 x2 x3 y1 y2 y3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 1 0 0 1 1 0 1 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 0 1 0 0 1 0 1 0 1 0 1 1 0 1 1 1 1 0 0 1 0 0 0 0 1 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 A. De Vos, Y. Van Rentergem: Young subgroups for reversible computers, Adv. in Math. of Comm. 2 (2008), 183–200.
  87. 87. ǚ ms | twenty-five Decomposition-based synthesis: example x1 x2 x3 y1 y2 y3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 1 0 0 1 1 0 1 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 0 1 0 0 1 0 1 0 1 0 1 1 0 1 1 1 1 0 0 1 0 0 0 0 1 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 A. De Vos, Y. Van Rentergem: Young subgroups for reversible computers, Adv. in Math. of Comm. 2 (2008), 183–200.
  88. 88. ǚ ms | twenty-five Decomposition-based synthesis: example x1 x2 x3 y1 y2 y3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 1 0 0 1 1 0 1 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 0 1 0 0 1 0 1 0 1 0 1 1 0 1 1 1 1 0 0 1 0 0 1 0 0 1 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 A. De Vos, Y. Van Rentergem: Young subgroups for reversible computers, Adv. in Math. of Comm. 2 (2008), 183–200.
  89. 89. ǚ ms | twenty-five Decomposition-based synthesis: example x1 x2 x3 y1 y2 y3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 1 0 0 1 1 0 1 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 0 1 0 0 1 0 1 0 1 0 1 1 0 1 1 1 1 0 0 1 0 0 1 0 0 1 1 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 A. De Vos, Y. Van Rentergem: Young subgroups for reversible computers, Adv. in Math. of Comm. 2 (2008), 183–200.
  90. 90. ǚ ms | twenty-five Decomposition-based synthesis: example x1 x2 x3 y1 y2 y3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 1 0 0 1 1 0 1 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 0 1 0 0 1 0 1 0 0 1 0 1 1 0 1 1 1 1 0 0 1 0 0 1 0 0 1 1 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 A. De Vos, Y. Van Rentergem: Young subgroups for reversible computers, Adv. in Math. of Comm. 2 (2008), 183–200.
  91. 91. ǚ ms | twenty-five Decomposition-based synthesis: example x1 x2 x3 y1 y2 y3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 1 0 0 1 1 0 1 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 1 0 0 1 0 1 1 0 1 1 1 1 0 0 1 0 0 1 0 0 1 1 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 A. De Vos, Y. Van Rentergem: Young subgroups for reversible computers, Adv. in Math. of Comm. 2 (2008), 183–200.
  92. 92. ǚ ms | twenty-five Decomposition-based synthesis: example x1 x2 x3 y1 y2 y3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 1 0 0 1 1 0 1 1 0 1 1 0 0 0 1 0 1 1 0 1 0 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 1 0 0 1 0 1 1 0 1 1 1 1 0 0 1 0 0 1 0 0 1 1 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 A. De Vos, Y. Van Rentergem: Young subgroups for reversible computers, Adv. in Math. of Comm. 2 (2008), 183–200.
  93. 93. ǚ ms | twenty-five Decomposition-based synthesis: example x1 x2 x3 y1 y2 y3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 1 0 0 1 1 0 1 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 1 0 0 1 0 1 1 0 1 1 1 1 0 0 1 0 0 1 0 0 1 1 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 A. De Vos, Y. Van Rentergem: Young subgroups for reversible computers, Adv. in Math. of Comm. 2 (2008), 183–200.
  94. 94. ǚ ms | twenty-five Decomposition-based synthesis: example x1 x2 x3 y1 y2 y3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 1 0 0 1 1 0 1 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 1 0 0 1 0 1 1 0 1 1 1 1 0 0 1 0 0 1 0 0 1 1 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 A. De Vos, Y. Van Rentergem: Young subgroups for reversible computers, Adv. in Math. of Comm. 2 (2008), 183–200.
  95. 95. ǚ ms | twenty-five Decomposition-based synthesis: example x1 x2 x3 y1 y2 y3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 1 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 1 0 0 1 1 0 1 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 1 0 0 1 0 1 1 0 1 1 1 1 0 0 1 0 0 1 0 0 1 1 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 A. De Vos, Y. Van Rentergem: Young subgroups for reversible computers, Adv. in Math. of Comm. 2 (2008), 183–200.
  96. 96. ǚ ms | twenty-five Decomposition-based synthesis: example x1 x2 x3 y1 y2 y3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 1 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 1 0 0 1 1 0 1 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 1 0 0 1 0 1 1 0 1 1 1 1 0 0 1 0 0 1 0 0 1 1 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 A. De Vos, Y. Van Rentergem: Young subgroups for reversible computers, Adv. in Math. of Comm. 2 (2008), 183–200.
  97. 97. ǚ ms | twenty-five Decomposition-based synthesis: example x1 x2 x3 y1 y2 y3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 1 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 1 0 0 1 1 0 1 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 1 0 0 1 0 1 1 0 1 1 1 1 0 0 1 0 0 1 0 0 1 1 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 A. De Vos, Y. Van Rentergem: Young subgroups for reversible computers, Adv. in Math. of Comm. 2 (2008), 183–200.
  98. 98. ǚ ms | twenty-five Decomposition-based synthesis: example x1 x2 x3 y1 y2 y3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 1 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 0 0 1 1 0 0 1 0 0 1 1 0 1 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 1 0 0 1 0 1 1 0 1 1 1 1 0 0 1 0 0 1 0 0 1 1 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 A. De Vos, Y. Van Rentergem: Young subgroups for reversible computers, Adv. in Math. of Comm. 2 (2008), 183–200.
  99. 99. ǚ ms | twenty-five Decomposition-based synthesis: example x1 x2 x3 y1 y2 y3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 1 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 0 0 1 0 0 1 1 0 0 1 0 0 1 1 0 1 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 1 0 0 1 0 1 1 0 1 1 1 1 0 0 1 0 0 1 0 0 1 1 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 A. De Vos, Y. Van Rentergem: Young subgroups for reversible computers, Adv. in Math. of Comm. 2 (2008), 183–200.
  100. 100. ǚ ms | twenty-five Decomposition-based synthesis: example x1 x2 x3 y1 y2 y3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 1 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 0 0 1 0 0 1 1 0 0 1 0 0 1 1 0 1 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 1 0 0 1 1 0 1 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 1 0 0 1 0 1 1 0 1 1 1 1 0 0 1 0 0 1 0 0 1 1 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 A. De Vos, Y. Van Rentergem: Young subgroups for reversible computers, Adv. in Math. of Comm. 2 (2008), 183–200.
  101. 101. ǚ ms | twenty-five Decomposition-based synthesis: example x1 x2 x3 y1 y2 y3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 1 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 0 0 1 0 0 1 1 0 0 1 0 0 1 1 0 1 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 1 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 1 0 0 1 0 1 1 0 1 1 1 1 0 0 1 0 0 1 0 0 1 1 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 A. De Vos, Y. Van Rentergem: Young subgroups for reversible computers, Adv. in Math. of Comm. 2 (2008), 183–200.
  102. 102. ǚ ms | twenty-five Decomposition-based synthesis: example x1 x2 x3 y1 y2 y3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 1 1 0 1 1 0 1 0 0 1 0 1 0 1 1 0 1 0 0 1 0 0 1 1 0 0 1 0 0 1 1 0 1 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 1 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 1 0 0 1 0 1 1 0 1 1 1 1 0 0 1 0 0 1 0 0 1 1 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 A. De Vos, Y. Van Rentergem: Young subgroups for reversible computers, Adv. in Math. of Comm. 2 (2008), 183–200.
  103. 103. ǚ ms | twenty-five Decomposition-based synthesis: example x1 x2 x3 y1 y2 y3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 1 1 0 1 1 0 1 0 0 1 0 1 0 1 1 0 1 0 0 1 0 0 1 1 0 0 1 0 0 1 1 0 1 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 1 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 1 0 0 1 0 1 1 0 1 1 1 1 0 0 1 0 0 1 0 0 1 1 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 x1 x2 x3 x2⊕x3 x1⊕x3 x2⊕x3 = y1 y2 y3 A. De Vos, Y. Van Rentergem: Young subgroups for reversible computers, Adv. in Math. of Comm. 2 (2008), 183–200.
  104. 104. ǚ ms | twenty-six Reversible synthesis classification line opt. gate opt. nonreversible func. reversible func. SAT-based Enumerative Transformation-based Cycle-based Decomposition-based Metaheuristic Greedy ESOP-based Hierarchical Building block functionalstructural
  105. 105. ǚ ms | twenty-seven ESOP-based synthesis f (x1, x2, x3, x4) = [(x4x3x2x1)2 is prime] = ¯x4 ¯x3x2 ∨ ¯x4x3x1 ∨ x4 ¯x3x2x1 ∨ x4x3 ¯x2x1 RevKit: esopbs K. Fazel, M.A. Thornton, and J.E. Rice: ESOP-based Toffoli Gate Cascade Generation, PACRIM (2007)
  106. 106. ǚ ms | twenty-seven ESOP-based synthesis f (x1, x2, x3, x4) = [(x4x3x2x1)2 is prime] = ¯x4 ¯x3x2 ∨ ¯x4x3x1 ∨ x4 ¯x3x2x1 ∨ x4x3 ¯x2x1 = x4x2x1 ⊕ x3x1 ⊕ ¯x4 ¯x3x2 RevKit: esopbs K. Fazel, M.A. Thornton, and J.E. Rice: ESOP-based Toffoli Gate Cascade Generation, PACRIM (2007)
  107. 107. ǚ ms | twenty-seven ESOP-based synthesis f (x1, x2, x3, x4) = [(x4x3x2x1)2 is prime] = ¯x4 ¯x3x2 ∨ ¯x4x3x1 ∨ x4 ¯x3x2x1 ∨ x4x3 ¯x2x1 = x4x2x1 ⊕ x3x1 ⊕ ¯x4 ¯x3x2 x1 x2 x3 x4 0 x1 x2 x3 x4 f (x1, x2, x3, x4) RevKit: esopbs K. Fazel, M.A. Thornton, and J.E. Rice: ESOP-based Toffoli Gate Cascade Generation, PACRIM (2007)
  108. 108. ǚ ms | twenty-seven ESOP-based synthesis f (x1, x2, x3, x4) = [(x4x3x2x1)2 is prime] = ¯x4 ¯x3x2 ∨ ¯x4x3x1 ∨ x4 ¯x3x2x1 ∨ x4x3 ¯x2x1 = x4x2x1 ⊕ x3x1 ⊕ ¯x4 ¯x3x2 x1 x2 x3 x4 0 x1 x2 x3 x4 f (x1, x2, x3, x4) RevKit: esopbs f1 = [3 | (x4x3x2x1)2] = ¯x1 ¯x2x3 ⊕ ¯x1 ¯x4 ⊕ x1 ¯x3x4 ⊕ x1x2x4 ⊕ x2 ¯x3 ¯x4 f2 = [(x4x3x2x1)2 is prime] K. Fazel, M.A. Thornton, and J.E. Rice: ESOP-based Toffoli Gate Cascade Generation, PACRIM (2007)
  109. 109. ǚ ms | twenty-seven ESOP-based synthesis f (x1, x2, x3, x4) = [(x4x3x2x1)2 is prime] = ¯x4 ¯x3x2 ∨ ¯x4x3x1 ∨ x4 ¯x3x2x1 ∨ x4x3 ¯x2x1 = x4x2x1 ⊕ x3x1 ⊕ ¯x4 ¯x3x2 x1 x2 x3 x4 0 x1 x2 x3 x4 f (x1, x2, x3, x4) RevKit: esopbs f1 = [3 | (x4x3x2x1)2] = ¯x1 ¯x2x3 ⊕ ¯x1 ¯x4 ⊕ x1 ¯x3x4 ⊕ x1x2x4 ⊕ x2 ¯x3 ¯x4 f2 = [(x4x3x2x1)2 is prime] x1 x2 x3 x4 0 0 x1 x2 x3 x4 f1(x1, x2, x3, x4) f2(x1, x2, x3, x4) K. Fazel, M.A. Thornton, and J.E. Rice: ESOP-based Toffoli Gate Cascade Generation, PACRIM (2007)
  110. 110. ǚ ms | twenty-eight RevKit [General commands] alias — creates an alias convert — converts one store element into another current — changes current store element help — shows all commands print — prints current store element as ASCII ps — prints statistics about current store element quit — quits RevKit set — sets global (settings) variable show — generates visual representation of current store element (as DOT file) store — interact with the store
  111. 111. ǚ ms | twenty-nine Reversible synthesis classification line opt. gate opt. nonreversible func. reversible func. SAT-based Enumerative Transformation-based Cycle-based Decomposition-based Metaheuristic Greedy ESOP-based Hierarchical Building block functionalstructural
  112. 112. ǚ ms | thirty XMG-based synthesis XMG consists of XOR gates with 2 inputs and MAJ gates with 3 inputs MAJ gates with constant input can represent AND and OR gates Edges can be complemented (dashed lines in graph) MAJ XOR OR ANDMAJ XOR AND XOR MAJ x2 x3 x4x1 y2y1 RevKit: dxs
  113. 113. ǚ ms | thirty-one XMG-based synthesis x1 x2 0 x1 x2 x1 ⊕ x2 XOR x1 x2 x1 x1 ⊕ x2 XOR (in-place) x1 x2 x3 0 x1 x2 x3 x1x2x3 MAJ x1 x2 x3 x1 ⊕ x3 x1 ⊕ x2 x1x2x3 MAJ (in-place) x1 x2 0 x1 x2 0x1x2 = x1 ∧ x2 AND x1 x2 1 x1 x2 1x1x2 = x1 ∨ x2 OR x2 x4 x3 x1 0 0 0 0 0 x2 x4 x3 x1 0 0 0 y2 y1
  114. 114. ǚ ms | thirty-two LUT-based hierarchical reversible synthesis Goal: Automatically synthesizing large Boolean functions into Clifford+T networks of reasonable quality (qubits and T-count) Soeken, Roetteler, Wiebe, De Micheli: Hierarchical reversible logic synthesis using LUTs, DAC (2017), arXiv:1706.02721
  115. 115. ǚ ms | thirty-two LUT-based hierarchical reversible synthesis Goal: Automatically synthesizing large Boolean functions into Clifford+T networks of reasonable quality (qubits and T-count) Algorithm: LUT-based hierarchical reversible synthesis (LHRS) 1. Represent input function as classical logic network and optimize it RevKit: lhrs Soeken, Roetteler, Wiebe, De Micheli: Hierarchical reversible logic synthesis using LUTs, DAC (2017), arXiv:1706.02721
  116. 116. ǚ ms | thirty-two LUT-based hierarchical reversible synthesis Goal: Automatically synthesizing large Boolean functions into Clifford+T networks of reasonable quality (qubits and T-count) Algorithm: LUT-based hierarchical reversible synthesis (LHRS) 1. Represent input function as classical logic network and optimize it 2. Map network into k-LUT network RevKit: lhrs Soeken, Roetteler, Wiebe, De Micheli: Hierarchical reversible logic synthesis using LUTs, DAC (2017), arXiv:1706.02721
  117. 117. ǚ ms | thirty-two LUT-based hierarchical reversible synthesis Goal: Automatically synthesizing large Boolean functions into Clifford+T networks of reasonable quality (qubits and T-count) Algorithm: LUT-based hierarchical reversible synthesis (LHRS) 1. Represent input function as classical logic network and optimize it 2. Map network into k-LUT network 3. Translate k-LUT network into reversible network with k-input single-target gates RevKit: lhrs Soeken, Roetteler, Wiebe, De Micheli: Hierarchical reversible logic synthesis using LUTs, DAC (2017), arXiv:1706.02721
  118. 118. ǚ ms | thirty-two LUT-based hierarchical reversible synthesis Goal: Automatically synthesizing large Boolean functions into Clifford+T networks of reasonable quality (qubits and T-count) Algorithm: LUT-based hierarchical reversible synthesis (LHRS) 1. Represent input function as classical logic network and optimize it 2. Map network into k-LUT network 3. Translate k-LUT network into reversible network with k-input single-target gates 4. Map single-target gates into Clifford+T networks RevKit: lhrs Soeken, Roetteler, Wiebe, De Micheli: Hierarchical reversible logic synthesis using LUTs, DAC (2017), arXiv:1706.02721
  119. 119. ǚ ms | thirty-two LUT-based hierarchical reversible synthesis Goal: Automatically synthesizing large Boolean functions into Clifford+T networks of reasonable quality (qubits and T-count) Algorithm: LUT-based hierarchical reversible synthesis (LHRS) 1. Represent input function as classical logic network and optimize it 2. Map network into k-LUT network 3. Translate k-LUT network into reversible network with k-input single-target gates 4. Map single-target gates into Clifford+T networks conv.alg. RevKit: lhrs Soeken, Roetteler, Wiebe, De Micheli: Hierarchical reversible logic synthesis using LUTs, DAC (2017), arXiv:1706.02721
  120. 120. ǚ ms | thirty-two LUT-based hierarchical reversible synthesis Goal: Automatically synthesizing large Boolean functions into Clifford+T networks of reasonable quality (qubits and T-count) Algorithm: LUT-based hierarchical reversible synthesis (LHRS) 1. Represent input function as classical logic network and optimize it 2. Map network into k-LUT network 3. Translate k-LUT network into reversible network with k-input single-target gates 4. Map single-target gates into Clifford+T networks conv.alg.newalg. RevKit: lhrs Soeken, Roetteler, Wiebe, De Micheli: Hierarchical reversible logic synthesis using LUTs, DAC (2017), arXiv:1706.02721
  121. 121. ǚ ms | thirty-two LUT-based hierarchical reversible synthesis Goal: Automatically synthesizing large Boolean functions into Clifford+T networks of reasonable quality (qubits and T-count) Algorithm: LUT-based hierarchical reversible synthesis (LHRS) 1. Represent input function as classical logic network and optimize it 2. Map network into k-LUT network 3. Translate k-LUT network into reversible network with k-input single-target gates 4. Map single-target gates into Clifford+T networks conv.alg.newalg. affects#qubits RevKit: lhrs Soeken, Roetteler, Wiebe, De Micheli: Hierarchical reversible logic synthesis using LUTs, DAC (2017), arXiv:1706.02721
  122. 122. ǚ ms | thirty-two LUT-based hierarchical reversible synthesis Goal: Automatically synthesizing large Boolean functions into Clifford+T networks of reasonable quality (qubits and T-count) Algorithm: LUT-based hierarchical reversible synthesis (LHRS) 1. Represent input function as classical logic network and optimize it 2. Map network into k-LUT network 3. Translate k-LUT network into reversible network with k-input single-target gates 4. Map single-target gates into Clifford+T networks conv.alg.newalg. affects#qubits affects#Tgates RevKit: lhrs Soeken, Roetteler, Wiebe, De Micheli: Hierarchical reversible logic synthesis using LUTs, DAC (2017), arXiv:1706.02721
  123. 123. ǚ ms | thirty-three LUT mapping Realizing a logic function or logic circuit in terms of a k-LUT logic network A k-LUT is any Boolean function with at most k inputs One of the most effective methods used in logic synthesis Soeken, Roetteler, Wiebe, De Micheli: Hierarchical reversible logic synthesis using LUTs, DAC (2017), arXiv:1706.02721
  124. 124. ǚ ms | thirty-three LUT mapping Realizing a logic function or logic circuit in terms of a k-LUT logic network A k-LUT is any Boolean function with at most k inputs One of the most effective methods used in logic synthesis Typical objective functions are size (number of LUTs) and depth (longest path from inputs to outputs) Open source software ABC can generate industrial-scale mappings Soeken, Roetteler, Wiebe, De Micheli: Hierarchical reversible logic synthesis using LUTs, DAC (2017), arXiv:1706.02721
  125. 125. ǚ ms | thirty-three LUT mapping Realizing a logic function or logic circuit in terms of a k-LUT logic network A k-LUT is any Boolean function with at most k inputs One of the most effective methods used in logic synthesis Typical objective functions are size (number of LUTs) and depth (longest path from inputs to outputs) Open source software ABC can generate industrial-scale mappings Can be used as technology mapper for FPGAs (e.g., when k ≤ 7) Soeken, Roetteler, Wiebe, De Micheli: Hierarchical reversible logic synthesis using LUTs, DAC (2017), arXiv:1706.02721
  126. 126. ǚ ms | thirty-four k-LUT network to reversible network y2y1 x3x2x1 x4 x5 1 2 3 4 5 x1 x2 x3 x4 x5 x1 x2 x3 x4 x5 Soeken, Roetteler, Wiebe, De Micheli: Hierarchical reversible logic synthesis using LUTs, DAC (2017), arXiv:1706.02721
  127. 127. ǚ ms | thirty-four k-LUT network to reversible network y2y1 x3x2x1 x4 x5 1 2 3 4 5 x1 x2 x3 x4 x5 0 1 x1 x2 x3 x4 x5 k-LUT corresponds to k-controlled single-target gate Soeken, Roetteler, Wiebe, De Micheli: Hierarchical reversible logic synthesis using LUTs, DAC (2017), arXiv:1706.02721
  128. 128. ǚ ms | thirty-four k-LUT network to reversible network y2y1 x3x2x1 x4 x5 1 2 3 4 5 x1 x2 x3 x4 x5 0 0 1 2 x1 x2 x3 x4 x5 k-LUT corresponds to k-controlled single-target gate Soeken, Roetteler, Wiebe, De Micheli: Hierarchical reversible logic synthesis using LUTs, DAC (2017), arXiv:1706.02721
  129. 129. ǚ ms | thirty-four k-LUT network to reversible network y2y1 x3x2x1 x4 x5 1 2 3 4 5 x1 x2 x3 x4 x5 0 0 0 1 2 3 x1 x2 x3 x4 x5 y1 k-LUT corresponds to k-controlled single-target gate Soeken, Roetteler, Wiebe, De Micheli: Hierarchical reversible logic synthesis using LUTs, DAC (2017), arXiv:1706.02721
  130. 130. ǚ ms | thirty-four k-LUT network to reversible network y2y1 x3x2x1 x4 x5 1 2 3 4 5 x1 x2 x3 x4 x5 0 0 0 0 1 2 3 4 x1 x2 x3 x4 x5 y1 k-LUT corresponds to k-controlled single-target gate Soeken, Roetteler, Wiebe, De Micheli: Hierarchical reversible logic synthesis using LUTs, DAC (2017), arXiv:1706.02721
  131. 131. ǚ ms | thirty-four k-LUT network to reversible network y2y1 x3x2x1 x4 x5 1 2 3 4 5 x1 x2 x3 x4 x5 0 0 0 0 0 1 2 3 4 5 x1 x2 x3 x4 x5 y1 y2 k-LUT corresponds to k-controlled single-target gate Soeken, Roetteler, Wiebe, De Micheli: Hierarchical reversible logic synthesis using LUTs, DAC (2017), arXiv:1706.02721
  132. 132. ǚ ms | thirty-four k-LUT network to reversible network y2y1 x3x2x1 x4 x5 1 2 3 4 5 x1 x2 x3 x4 x5 0 0 0 0 0 1 2 3 4 5 4 x1 x2 x3 x4 x5 y1 0 y2 k-LUT corresponds to k-controlled single-target gate non-output LUTs need to be uncomputed Soeken, Roetteler, Wiebe, De Micheli: Hierarchical reversible logic synthesis using LUTs, DAC (2017), arXiv:1706.02721
  133. 133. ǚ ms | thirty-four k-LUT network to reversible network y2y1 x3x2x1 x4 x5 1 2 3 4 5 x1 x2 x3 x4 x5 0 0 0 0 0 1 2 3 4 5 4 2 x1 x2 x3 x4 x5 0 y1 0 y2 k-LUT corresponds to k-controlled single-target gate non-output LUTs need to be uncomputed Soeken, Roetteler, Wiebe, De Micheli: Hierarchical reversible logic synthesis using LUTs, DAC (2017), arXiv:1706.02721
  134. 134. ǚ ms | thirty-four k-LUT network to reversible network y2y1 x3x2x1 x4 x5 1 2 3 4 5 x1 x2 x3 x4 x5 0 0 0 0 0 1 2 3 4 5 4 2 1 x1 x2 x3 x4 x5 0 0 y1 0 y2 k-LUT corresponds to k-controlled single-target gate non-output LUTs need to be uncomputed Soeken, Roetteler, Wiebe, De Micheli: Hierarchical reversible logic synthesis using LUTs, DAC (2017), arXiv:1706.02721
  135. 135. ǚ ms | thirty-four k-LUT network to reversible network y2y1 x3x2x1 x4 x5 1 2 3 4 5 x1 x2 x3 x4 x5 0 0 0 0 1 2 4 5 4 2 3 1 x1 x2 x3 x4 x5 0 y1 0 y2 k-LUT corresponds to k-controlled single-target gate non-output LUTs need to be uncomputed order of LUT traversal determines number of ancillas Soeken, Roetteler, Wiebe, De Micheli: Hierarchical reversible logic synthesis using LUTs, DAC (2017), arXiv:1706.02721
  136. 136. ǚ ms | thirty-four k-LUT network to reversible network y2y1 x3x2x1 x4 x5 1 2 3 4 5 x1 x2 x3 x4 x5 0 0 0 0 1 2 4 5 4 2 3 1 x1 x2 x3 x4 x5 0 y1 0 y2 k-LUT corresponds to k-controlled single-target gate non-output LUTs need to be uncomputed order of LUT traversal determines number of ancillas maximum output cone determines minimum number of ancillas Soeken, Roetteler, Wiebe, De Micheli: Hierarchical reversible logic synthesis using LUTs, DAC (2017), arXiv:1706.02721
  137. 137. ǚ ms | thirty-four k-LUT network to reversible network y2y1 x3x2x1 x4 x5 1 2 3 4 5 x1 x2 x3 x4 x5 0 0 0 0 1 2 4 5 4 2 3 1 x1 x2 x3 x4 x5 0 y1 0 y2 k-LUT corresponds to k-controlled single-target gate non-output LUTs need to be uncomputed order of LUT traversal determines number of ancillas maximum output cone determines minimum number of ancillas fast mapping that generates a fixed-space skeleton for subnetwork synthesis Soeken, Roetteler, Wiebe, De Micheli: Hierarchical reversible logic synthesis using LUTs, DAC (2017), arXiv:1706.02721
  138. 138. ǚ ms | thirty-five Single-target gate LUT mapping x1 x2 x3 x4 x5 0 0 0 0 0 1 2 3 4 5 4 2 1 x1 x2 x3 x4 x5 0 0 y1 0 y2 Mapping problem: Given a single-target gate Tf (X, xt) (with control function f , control lines X, and target line xt), a set of clean ancillas Xc, and a set of dirty ancillas Xd, find the best mapping into a Clifford+T network, such that all ancillas are restored to their original value. Soeken, Roetteler, Wiebe, De Micheli: Hierarchical reversible logic synthesis using LUTs, DAC (2017), arXiv:1706.02721
  139. 139. ǚ ms | thirty-six Single-target gate mapping algorithms Direct Soeken, Roetteler, Wiebe, De Micheli: Hierarchical reversible logic synthesis using LUTs, DAC (2017), arXiv:1706.02721
  140. 140. ǚ ms | thirty-six Single-target gate mapping algorithms Direct Map each control function using ESOP based synthesis Soeken, Roetteler, Wiebe, De Micheli: Hierarchical reversible logic synthesis using LUTs, DAC (2017), arXiv:1706.02721
  141. 141. ǚ ms | thirty-six Single-target gate mapping algorithms Direct Map each control function using ESOP based synthesis Does not use ancillae Soeken, Roetteler, Wiebe, De Micheli: Hierarchical reversible logic synthesis using LUTs, DAC (2017), arXiv:1706.02721
  142. 142. ǚ ms | thirty-six Single-target gate mapping algorithms Direct Map each control function using ESOP based synthesis Does not use ancillae LUT-based Soeken, Roetteler, Wiebe, De Micheli: Hierarchical reversible logic synthesis using LUTs, DAC (2017), arXiv:1706.02721
  143. 143. ǚ ms | thirty-six Single-target gate mapping algorithms Direct Map each control function using ESOP based synthesis Does not use ancillae LUT-based Map control function into smaller LUT network Soeken, Roetteler, Wiebe, De Micheli: Hierarchical reversible logic synthesis using LUTs, DAC (2017), arXiv:1706.02721
  144. 144. ǚ ms | thirty-six Single-target gate mapping algorithms Direct Map each control function using ESOP based synthesis Does not use ancillae LUT-based Map control function into smaller LUT network Map small LUTs into pre-computed optimum quantum circuits Soeken, Roetteler, Wiebe, De Micheli: Hierarchical reversible logic synthesis using LUTs, DAC (2017), arXiv:1706.02721
  145. 145. ǚ ms | thirty-seven Direct mapping f (x1, x2, x3, x4) = [(x4x3x2x1)2 is prime] = ¯x4 ¯x3x2 ∨ ¯x4x3x1 ∨ x4 ¯x3x2x1 ∨ x4x3 ¯x2x1 x1 x2 x3 x4 0 f Soeken, Roetteler, Wiebe, De Micheli: Hierarchical reversible logic synthesis using LUTs, DAC (2017), arXiv:1706.02721
  146. 146. ǚ ms | thirty-seven Direct mapping f (x1, x2, x3, x4) = [(x4x3x2x1)2 is prime] = ¯x4 ¯x3x2 ∨ ¯x4x3x1 ∨ x4 ¯x3x2x1 ∨ x4x3 ¯x2x1 = x4x2x1 ⊕ x3x1 ⊕ ¯x4 ¯x3x2 x1 x2 x3 x4 0 f = x1 x2 x3 x4 f (x1, x2, x3, x4) Soeken, Roetteler, Wiebe, De Micheli: Hierarchical reversible logic synthesis using LUTs, DAC (2017), arXiv:1706.02721
  147. 147. ǚ ms | thirty-seven Direct mapping f (x1, x2, x3, x4) = [(x4x3x2x1)2 is prime] = ¯x4 ¯x3x2 ∨ ¯x4x3x1 ∨ x4 ¯x3x2x1 ∨ x4x3 ¯x2x1 = x4x2x1 ⊕ x3x1 ⊕ ¯x4 ¯x3x2 x1 x2 x3 x4 0 f = x1 x2 x3 x4 f (x1, x2, x3, x4) Each multiple-controlled Toffoli gate is mapped to Clifford+T Soeken, Roetteler, Wiebe, De Micheli: Hierarchical reversible logic synthesis using LUTs, DAC (2017), arXiv:1706.02721
  148. 148. ǚ ms | thirty-seven Direct mapping f (x1, x2, x3, x4) = [(x4x3x2x1)2 is prime] = ¯x4 ¯x3x2 ∨ ¯x4x3x1 ∨ x4 ¯x3x2x1 ∨ x4x3 ¯x2x1 = x4x2x1 ⊕ x3x1 ⊕ ¯x4 ¯x3x2 x1 x2 x3 x4 0 f = x1 x2 x3 x4 f (x1, x2, x3, x4) Each multiple-controlled Toffoli gate is mapped to Clifford+T ESOP minimization tools (e.g., exorcism) optimize for cube count Soeken, Roetteler, Wiebe, De Micheli: Hierarchical reversible logic synthesis using LUTs, DAC (2017), arXiv:1706.02721
  149. 149. ǚ ms | thirty-eight LUT-based single-target gate mapping x1 x2 x3 x4 0 w 0 0 0 f x1 x2 x3 x4 f w 0 0 0 Soeken, Roetteler, Wiebe, De Micheli: Hierarchical reversible logic synthesis using LUTs, DAC (2017), arXiv:1706.02721
  150. 150. ǚ ms | thirty-eight LUT-based single-target gate mapping x1 x2 x3 x4 0 w 0 0 0 f x1 x2 x3 x4 f w 0 0 0 3 4 1 2 x2 x3 x1x4 f Soeken, Roetteler, Wiebe, De Micheli: Hierarchical reversible logic synthesis using LUTs, DAC (2017), arXiv:1706.02721
  151. 151. ǚ ms | thirty-eight LUT-based single-target gate mapping x1 x2 x3 x4 0 w 0 0 0 f = 1 2 3 4 3 2 1 x1 x2 x3 x4 f w 0 0 0 3 4 1 2 x2 x3 x1x4 f Soeken, Roetteler, Wiebe, De Micheli: Hierarchical reversible logic synthesis using LUTs, DAC (2017), arXiv:1706.02721
  152. 152. ǚ ms | thirty-nine Affine transformations x 0 f x f (x) Soeken, Roetteler, Wiebe, De Micheli: Hierarchical reversible logic synthesis using LUTs, DAC (2017), arXiv:1706.02721
  153. 153. ǚ ms | thirty-nine Affine transformations x 0 f x f (x) x 0 C1 f C† 1 C2 x f (x) Let C1 and C2 be circuits that only consist of NOT and CNOT gates Soeken, Roetteler, Wiebe, De Micheli: Hierarchical reversible logic synthesis using LUTs, DAC (2017), arXiv:1706.02721
  154. 154. ǚ ms | thirty-nine Affine transformations x 0 f x f (x) x 0 C1 f C† 1 C2 x f (x) Let C1 and C2 be circuits that only consist of NOT and CNOT gates Both circuits have the same number of T gates Soeken, Roetteler, Wiebe, De Micheli: Hierarchical reversible logic synthesis using LUTs, DAC (2017), arXiv:1706.02721
  155. 155. ǚ ms | thirty-nine Affine transformations x 0 f x f (x) x 0 C1 f C† 1 C2 x f (x) Let C1 and C2 be circuits that only consist of NOT and CNOT gates Both circuits have the same number of T gates Instead of 65 536 4-input functions we only need to consider 18 Soeken, Roetteler, Wiebe, De Micheli: Hierarchical reversible logic synthesis using LUTs, DAC (2017), arXiv:1706.02721
  156. 156. ǚ ms | thirty-nine Affine transformations x 0 f x f (x) x 0 C1 f C† 1 C2 x f (x) Let C1 and C2 be circuits that only consist of NOT and CNOT gates Both circuits have the same number of T gates Instead of 65 536 4-input functions we only need to consider 18 Instead of 4 294 967 296 5-input functions we only need to consider 206 Soeken, Roetteler, Wiebe, De Micheli: Hierarchical reversible logic synthesis using LUTs, DAC (2017), arXiv:1706.02721
  157. 157. ǚ ms | forty Circuits for affine equivalence classes 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 # 035f 23 # 0357 61 # 0356 12 # 033f 7 # 017f 140 # 013f 48 # 011f 27 # 0117 79 # 00ff 0 # 007f 40 # 003f 16 # 001f 43 # 0017 23 # 000f 7 # 0007 47 # 0003 15 # 0001 40 # 17 7 # 0f 0 # 07 16 # 03 7 # 01 15 # 3 0 # 1 7 28724 469866 22825 3604 221674 13356 228190 10161 187541 133 10090 841 9786 92480 2941 85 209461 9655 563675 91108 3536 257890 23407 130461 quantumlib.stationq.com Soeken, Roetteler, Wiebe, De Micheli: Hierarchical reversible logic synthesis using LUTs, DAC (2017), arXiv:1706.02721
  158. 158. ǚ ms | forty-one The LHRS ecosystem  arxiv.org/abs/1706.02721 Mapping into LUTs Aligning LUTs as single-target gates Mapping single-target gates LHRS Soeken, Roetteler, Wiebe, De Micheli: Hierarchical reversible logic synthesis using LUTs, DAC (2017), arXiv:1706.02721
  159. 159. ǚ ms | forty-one The LHRS ecosystem  arxiv.org/abs/1706.02721 Mapping into LUTs Aligning LUTs as single-target gates Mapping single-target gates LHRS let gaussian a b c d x = let den = (x - b) * (x - b) let nom = -2.0f * c * c a * exp (den / nom) program Soeken, Roetteler, Wiebe, De Micheli: Hierarchical reversible logic synthesis using LUTs, DAC (2017), arXiv:1706.02721
  160. 160. ǚ ms | forty-one The LHRS ecosystem  arxiv.org/abs/1706.02721 Mapping into LUTs Aligning LUTs as single-target gates Mapping single-target gates LHRS let gaussian a b c d x = let den = (x - b) * (x - b) let nom = -2.0f * c * c a * exp (den / nom) program LIQUi| ProjectQ Quipper Soeken, Roetteler, Wiebe, De Micheli: Hierarchical reversible logic synthesis using LUTs, DAC (2017), arXiv:1706.02721
  161. 161. ǚ ms | forty-two Circuit rewriting = M. Soeken, M.K. Thomsen: White dots do matter: rewriting reversible logic circuits, RC 5, (2013), 196–208
  162. 162. ǚ ms | forty-two Circuit rewriting = = = M. Soeken, M.K. Thomsen: White dots do matter: rewriting reversible logic circuits, RC 5, (2013), 196–208
  163. 163. ǚ ms | forty-two Circuit rewriting = = = = = M. Soeken, M.K. Thomsen: White dots do matter: rewriting reversible logic circuits, RC 5, (2013), 196–208
  164. 164. ǚ ms | forty-two Circuit rewriting = = = = = = M. Soeken, M.K. Thomsen: White dots do matter: rewriting reversible logic circuits, RC 5, (2013), 196–208
  165. 165. ǚ ms | forty-two Circuit rewriting = = = = = = = M. Soeken, M.K. Thomsen: White dots do matter: rewriting reversible logic circuits, RC 5, (2013), 196–208
  166. 166. ǚ ms | forty-two Circuit rewriting = = = = = = = = M. Soeken, M.K. Thomsen: White dots do matter: rewriting reversible logic circuits, RC 5, (2013), 196–208
  167. 167. ǚ ms | forty-two Circuit rewriting = = = = = = = = ? Open problem: These six rules (plus SWAP rule) are complete, i.e., one can rewrite any circuit realizing some function into any other circuit realizing the same function M. Soeken, M.K. Thomsen: White dots do matter: rewriting reversible logic circuits, RC 5, (2013), 196–208
  168. 168. ǚ ms | forty-two Circuit rewriting = = = = = = = = ? Open problem: These six rules (plus SWAP rule) are complete, i.e., one can rewrite any circuit realizing some function into any other circuit realizing the same function Rule set has been extended to consider ancillae M. Soeken, M.K. Thomsen: White dots do matter: rewriting reversible logic circuits, RC 5, (2013), 196–208
  169. 169. ǚ ms | forty-three Circuit rewriting: example Circuit G1 Circuit G2 M. Soeken, M.K. Thomsen: White dots do matter: rewriting reversible logic circuits, RC 5, (2013), 196–208
  170. 170. ǚ ms | forty-three Circuit rewriting: example Circuit G1 Circuit G2 Can be used for equivalence checking to check G1 ≡ G2 Construct circuit G = G−1 2 ◦ G1 Rewrite G to identity M. Soeken, M.K. Thomsen: White dots do matter: rewriting reversible logic circuits, RC 5, (2013), 196–208
  171. 171. ǚ ms | forty-three Circuit rewriting: example Circuit G1 Circuit G2 Can be used for equivalence checking to check G1 ≡ G2 Construct circuit G = G−1 2 ◦ G1 Rewrite G to identity = = = M. Soeken, M.K. Thomsen: White dots do matter: rewriting reversible logic circuits, RC 5, (2013), 196–208
  172. 172. ǚ ms | forty-four Equivalence checking of reversible circuits Conventional approach 1 G1 G2 Exploiting reversibility L.G. Amarù, P.-E. Gaillardon, R. Wille, and G. De Micheli: DATE 19 (2016)
  173. 173. ǚ ms | forty-four Equivalence checking of reversible circuits Conventional approach 1 G1 G2 Exploiting reversibility 1G1 G−1 2 RevKit: rec L.G. Amarù, P.-E. Gaillardon, R. Wille, and G. De Micheli: DATE 19 (2016)
  174. 174. ǚ ms | forty-four Equivalence checking of reversible circuits Conventional approach 1 G1 G2 Exploiting reversibility 1G1 G−1 2 RevKit: rec Circuit is translated into a SAT formula and solved with a SAT solver A satisfying solution is witnessing a counter-example Solvers with support for XOR clauses allow for more natural encoding and better runtimes L.G. Amarù, P.-E. Gaillardon, R. Wille, and G. De Micheli: DATE 19 (2016)
  175. 175. ǚ ms | forty-five Introduction and background Reversible logic synthesis Introduction into RevKit
  176. 176. Reversible logic synthesis and RevKit Mathias Soeken Integrated Systems Laboratory, EPFL, Switzerland mathias.soeken@epfl.ch msoeken.github.io msoeken/cirkit

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