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Using Formal Methods to Create Instruction Set Architectures
1. Using Formal Methods to
Create Instruction Set
Architectures
Steve Wright
Bristol University
Department of
COMPUTER SCIENCE
2. Steve Wright
• Chartered Software Engineer.
• 8 years at Rolls-Royce.
• 2 years at STMicroelectronics.
• 7 years at Airbus.
• Now at University of Bristol.
6. Failure Conditions
“Open the pod bay doors, HAL.”
“I'm sorry Dave, I'm afraid
I can't do that.”
Harder to identify.
7. Formal Methods
• Define “events”: “actions” predicated by
“guards”.
• Use set theory to prove that one or more
events is subset of a single more abstract
event.
• “Model Checking” needed to prove that
refined events fully implement abstract.
8. ISA Common Properties
• Binary image in contiguous memory.
• Instructions selected by “Program
Counter”.
• All operations as bit-manipulations
between registers.
• Register data stored across multiple
contiguous memory locations.
10. First Refinement
Loading
REFINES Iterate
WHEN
grd1: status = LOADING
THEN
act1: inst :∈ Inst
act2: status :∈ { LOADING, RUNNING}
END
Running
REFINES Iterate
WHEN
grd1: status = RUNNING
THEN
act1: inst :∈ Inst // Instruction is updated
act3: status :∈ { RUNNING, HALTED, FAILED}
END
Halted // Explicit deadlock achieved
REFINES Iterate
WHEN
grd1: status = HALTED
THEN
skip
END
Failed // Explicit deadlock achieved
REFINES Iterate
WHEN
grd1: status = FAILED
THEN
skip
END
Create state machine to switch states RUNNING/FAILED/HALTED:
=
11. 32nd(!) Refinement
NopOk
REFINES NopOk
ANY
op
opVal
nextInstPtr
WHERE
grd6: op : DataByte
grd7: op = mem(instPtr)
grd5: opVal : 0..255
grd2: opVal = DataByte2Int(op)
grd1: opVal = 16
grd3: instPtr <= 99992
grd4: statusCode = 2
grd8: nextInstPtr : -2147483647.. 2147483647
grd9: nextInstPtr = instPtr + 1
THEN
act1: instPtr := nextInstPtr
END
For example, the humble NOP:
15. RODIN
• Integrated Development Environment for Event-B.
• Eclipse-based.
• Windows, Linux and Mac.
• Free, open-source.
• Extensible via Java plug-ins.
16. “MIDAS” Example Machines
• Stack and register machines.
• 35 instructions.
• “Modified Harvard” memory
architecture.
• Stack and Register Variants