MSP430 Presentation made in 2005 Arrow Israel MSP430 Day

1. 1

2. 2
1000 and 1 Uses
MSP430 Ultra-Low-Power MCUs

3. 3
• What is the MSP430?
• The Ultra-low Power Concept
• Device Derivatives
• Development Support
• Future Products
Agenda MSP430 Day 2005

4. 4
MSP430MSP430
 Ultra-low Power
MSP430MSP430
 Ultra-low Power
8-bit
Performance
MeasurementMeasurement
 Utility Metering
 Portable Instrumentation
TMS470TMS470
 ARM7TDMI
September ‘05September ‘05
TMS470TMS470
 ARM7TDMI
September ‘05September ‘05
C2000C2000
 150 MIPS
C2000C2000
 150 MIPS
Industry StandardIndustry Standard
 Industrial
 General Purpose
High-PerformanceHigh-Performance
 Motor Control
 Digital Power Supply
TI Catalog Microcontroller Portfolio
16/32-bit
DSP

5. 5
MSP430 Portfolio
FE43x
F15x/16x
1xx Catalog20PIN
DAC12,
ADC12, DMA
(2005)
$0.49
16MIPS
38PIN
80PIN
2xx
F22x0
F21x1
F21x1
F1xx2
x11x1
x13x/14x
4xx w/LCD
FE41x
x41x
F43x/44x
F42x0
F461x
FG43x
128KB
8MIPS
Sigma Delta SD16
LCD_A, DAC12
In Characterization !
F42x
FE42x
FW42x
3x Operational Amplifiers
DAC12, DMA
USB
F12x
F48x
64PIN
14 Pin
MemorySize
Integration
F161x 64KB
BOR On chip
F201x
F271x
F23x/24
x
LCD_A, USCI,
DAC12, DMA
Migration Path
8MIPS

6. 6
Utility Metering
– Water, heat, energy, gas meters
– Thermostats, heating regulators
Portable Instrumentation
– Handheld measurement devices
– Personal / home medical products
Intelligent Sensing
– Smoke detectors
– Alarms / intrusion detectors
– Industrial sensors
Consumer
– Feature watches / wireless accessories
– Home appliances
Typical MSP430 Applications

7. 7
FLASHClock
Digital
Peripheral
RISC
CPU
16-bit
MAB 16
MDB 16
RAM
Analog
Peripheral
. . .
. . .
ACLK
SMCLK
JTAG/Debug
Ultra-low Power
– 0.1uA power down
– 0.8uA standby mode
– 250uA / 1MIPS @ 3V
– <6us clock start-up
– <50nA port leakage
– Zero-power BOR
– 1.8-3.6V operation
– -40 - +85C temp range
High-Performance
– Modern 16-bit RISC
– Signal Chain-on Chip integration
Easy To Use IDE
– Get to market faster
What Is The MSP430?

8. 8
Power Down
All
clocks off
0.1uA
Power Down
All
clocks off
0.1uA
Stand-by
DCO off
ACLK on
0.8uA
Stand-by
DCO off
ACLK on
0.8uA
Active Mode
DCO on
ACLK on
250uA
Active Mode
DCO on
ACLK on
250uA
“LPM3”
RTC function
LCD driver
RAM/SFRs retained
CPU Off
DCO on
ACLK on
35uA
CPU Off
DCO on
ACLK on
35uA
“LPM4”
RAM/SFRs retained
<1/6us
<1/6us
Ultra-low Power Clock Control
“LPM0”
•1us->2xx

9. 9
015
16
16-bit ALU
R8
R9
R10
R11
R12
R13
R14
R15
R4
R5
R6
R7
R3/CG
R2/SR
R1/SP
R0/PC
16
015
16
16-bit ALU
R8
R9
R10
R11
R12
R13
R14
R15
R4
R5
R6
R7
R3/CG
R2/SR
R1/SP
R0/PC
16
Modern 16-bit CPU
Deep Register File
– 4 dedicated
– 12 general purpose
Fifty-one Instructions
– 27 core
– 24 emulated
Three Instruction Formats
– Source, Destination
– Destination
– Jumping
Seven Addressing Modes
Word, Byte, Bit Processing

10. 10
0x0000
Memory Map
Word/Byte
Word Only
Byte Only
0xFFFF
Unified Memory Map
– Absolutely no paging
– Consistent instructions
– Byte access - even/odd
– Word access - even only
FLASH
(x) 512B
Segments
8-bit Peripherals
Bootstrap Loader
RAM
(2) 128B
16-bit Peripherals
Interrupt Vectors

11. 11
Flash Facts
– Main: (x) 512B segments
– Info: 2x 128B [4x 64B] segments
– 1.8 - 3.6V operation
– 2.7V [2.2V] - 3.6V prog./erase
– 100k erase/program cycles
– 100 year data retention
Flash Programming
– In System Programmable
– JTAG
– Bootstrap Loader
Flash
Segment 0
with Int Vectors
Segment 1
Segment x
Segment A
Segment B
FLASH
(x) 512B
Segments
8-bit Peripherals
Bootstrap Loader
RAM
(2) 128B
16-bit Peripherals
Interrupt Vectors
[…] = MSP430x2xx derivative

12. 12
Modern CPU
Minimum cycles per task
Multiple operating modes
Instant-on stable high-speed clock
Zero-power BOR
Intelligent peripherals
50nA pin leakage
0.1uA power down
0.8uA standby mode
250uA / 1MIPS @ 3V
Ultra-Low Power Architecture

13. 13
• Standby as long
as possible
• Interrupt-driven
activity
<6us<6us
Ultra-low Power Activity Profile
Always-on
On demand

14. 14
Interrupt
DCO
DCO Allows Fast Reaction To Events
• Ultra fast start-up (max. 6us/1us{2xx})
• Stable clock from first clock pulse

15. 15
0.80uA0.80uA Standby
+ 0.03 RTC
+ 0.80 LCD
+ 0.30 ADC
---------
2uA2uA
MSP430F413
32768
Heat
Cool
Set
Hold
LoBatt
MSP430F413
32768
Heat
Cool
Set
Hold
LoBatt
10-year Battery Life

16. 16
MSP430F2xx – New for 2005
• 2X speed Zero-16MIPS / 1us
• ½ power 1uA real-time clock
• Failsafe oscillator
• Zero-power BOR
• Pull-up/down pins
• + 2.5% oscillator
• Hack proof bootloader
• 2.2V Flash ISP
• 17us/byte Flash ISP
8KB Flash
16-bit
RISC
CPU
Port
Timer_A3
256B
RAM
Watchdog
DCO
Oscillator
Emulation
8KB Flash
16-bit
RISC
CPU
Port
Timer_A3
256B
RAM
Watchdog
DCO
Oscillator
Emulation

17. 17
What has been improved?
Basic Clock System
Plus
Improved Oscillators
FLASH
BOR
WDT+
Improved Robustness
XIN XOUT
FLASH
1-8 KB
RAM
256B
Power-On
Reset
12MHz
Basic
Clock
Plus
Watchdog
Plus
15-bit
RISC CPU
16-bit
ACLK
SMCLK
MAB
MDB
Timer_A3
16-bit
Comp_A
Mux Input
Port 1
with IRQ
Port 2
with IRQ
MCLK
TEST
JTAG/DeBUG
Brown-Out
Protection
Programmable
Pull-Ups / - Downs
Programmable
Pull-Ups / - Downs
Comparator_A
+ Sample & Hold
Multiplexer
Higher Speed
16MHz

18. 18
BOR
VCC
V
t
VB,IT
VSTART
VCCMIN
POR
Power On Reset (POR) vs Brownout Reset (BOR)
Brown-out!
Battery Insertion
 Power Consumption of
BOR (Brownout Reset)
included in specified
supply values in the
datasheet.
E.g. LPM4 100nA!
POR = Power On Reset
BOR = Brownout Reset
POR: VCC rise time
dV/dt ≥ 1V/ms.

19. 19
Ultra-low power
Fully automatic
4/3/2 mux or static
44x = 160-bit display
D is p la y
M e m o r y
2 0 x
8 - b it s
S e g m e n t
O u t p u t
C o n t r o l
M u x
A n a lo g
V o lt a g e
M u lt ip le x e r
T im in g G e n e r a t o r
R 2 3
R 1 3
R 0 3
C O M 0
C O M 2
C O M 1
R 3 3
C O M 3
S 0
S 1
C o m m o n
O u t p u t
C o n t r o l
S 3 9
S 3 8
S E G 0
S E G 1
S E G 3 8
S E G 3 9
M u x
M u x
M u x
L C D M 7
L C D M 6
L C D M 5
L C D M 4
L C D M 3
L C D M 2
L C D M 1
L C D M 0
f L C D
O s c O f f
MSP430x4xx LCD Driver

20. 20
USART
The USART supports 2 or 3 operating modes:
 Asynchronous RS232 Mode
 Synchronous SPI Mode
(3-Wire & 4 Wire)
 I2C interface – MSP430F15x/16x/16xx
(Master & Slave)

21. 21
New Modules - Universal Serial Communication Interface
USCI
UART/USART
SPI, LIN,
IrDA
I2
C, SPI
 New Universal Communication Interface Module
Supporting
UART/USART
SPI
LIN
I2
C
IrDA
 Two serial communications can be setup at the
same time
- 1st
channel UART,SPI, LIN or IrDA
- 2nd
channel SPI or I2
C

22. 22
Programmable Pull-Ups / Pull-Downs
Port 1
with IRQ
Port 2
with IRQ
Programmable
Pull-Ups / - Downs
 All Port Pins offer selectable Pull-Up
or Pull-Down resistors
 The resistors are activated by the PxREN bits
 The determination whether a Pull-up or Pull-down
is active, determines the PxOUT bit
DVSS
DVCC
1
0
PxREN.x
PxOUT.x
1
0
Direction
0: Input
1: Output
Bus
Keeper
EN
Pull-Up / Pull-Down
selection

23. 23
EEM = Enhanced Emulation Module
 MCU emulates itself in
application
 Breakpoint, single step,
full speed and trace
 Access fuse protection
ICE Functionality is Embedded

24. 24
MSP-FET430
USB PC port FET solution:
JTAG Interface
Target Board
Part Number Product Family Price
MSP-FET430U28 MSP430x11x1A, MSP430x12x/x1xx2 $149.0
0
MSP-FET430U64 MSP430x13x/x14x/x15x/x16x $149.0
0
MSP-FET430U80 MSP430x41x, MSP430FE42x,
MSP430FW42x
$149.0
0
MSP-
FET430U100
MSP430FG43x, MSP430x43x $149.0
0Part Number Product Family Price
MSP-FET430UIF MSP430 $99.00
USB PC port users with existing parallel FET solution:

25. 25
Eclipse Product Example: CCE
Platform Runtime
Workspace
Help
Team
Workbench
JFace
SWT
Eclipse Project
Java
Development
Tools
(SDK Only)
GDB430
CDT
TI
Extensions
Plug-in
Development
Environment
(SDK Only)
Eclipse Platform
Debug
Code Composer Essentials For MSP430
CG
Tools

26. 26
Features Leveraged From Eclipse & CDT
C/C++
Editor w/
Content
Assist
Outline
View

27. 27
Boot Loader
• Erase, Program, Verify ~6kB/sec
• No JTAG security fuse programming
• 9600 / 38400 “auto baud” UART
• No or any XTAL can be in place
• 256-bit password
• App reports SLAA089, SLAA086
• Ready to use Hard- + Software Solutions from
Third Parties (Gessler Electronic, Softbaugh)
Boot Loader
Starts
FLASH
(x) 512B
Segments
8-bit Peripherals
Bootstrap Loader
RAM
(2) 128B
16-bit Peripherals
Interrupt Vectors
RST/NMI
TCK

28. 28
SCoC – Signal Chain on Chip
3-Channel
DMA
Sensor
Signal
Input
Analog
Output
Analog to Digital
Converter
MSP430F169
16 x 16
MACS
16-bit RISC
CPU
IrDA
Serial COM
I2C
Readout
Digital to Analog
Converter
• Complete Signal Chain On a Chip SCoC
• High performance-to-cost benefits
• Embedded emulation allows real-time authentic debugging
• High performance A/D converter can eliminate the need for
signal amplification
• Integrated D/A converters complete the signal chain
• DMA enabled peripherals eliminate Peripheral Interface
Control

29. 29
SCoC – Signal Chain on Chip
Typical solution
100% loaded with only
serial transfer
SCoC solution
automatic data handling
Softwar
e

30. 30
MSP430F169 Functional Block Diagram

31. 31
Signal Flow
ADC12 DMA Flash
Timer_B MSP430F169Record
Flash DMA DAC
Timer_BMSP430F169 Playback
Amp
Amp

32. 32
Example Application
MSP430F169
Playback
Button
LEDs
Mic.
Amplifier
32768Hz
Crystal
Active
Speaker
Output
Microphone
3V Battery
Board: SoftBaugh DIr169
http://www.SoftBaugh.com
JTAG
connector
Record
Button

33. 33
EEM General Features
 Breakpoints: 2 to 8 available in hardware
 Complex breakpoints available
 Break if read/write at specified address
 Protection of read/write areas within Memory
 All timers & counters can be stopped (LCD is NOT stopped)
 USART can be stopped: clock source-dependent
 Single step/step into & over/run in real-time
 Full support of all low power modes
 Support for DCO dependencies such as temperature and voltage

34. 34
 Example: The CPU
should stop if a value
not equal to 0xA0A0
is written into a
variable. The variable
wSetBreakpointOn
is statically located in
RAM.
Break on Write to Address

35. 35
 Example: The
CPU should stop if
a write access into
Flash memory
occurs (0xE000 to
0xFFDE in this
case).
Break on Write to Flash

36. 36
 Example: CPU halts
if an attempt to fetch
an instruction out of
the allowed memory
range occurs
(outside of main
memory in this
case).
Break on Instruction Fetch out of Range

37. 37
 Highly flexible trace buffer
 Trace on instructions
 Trace on triggers
 Trace cycles / CPU clocks
 Buffer wrap-around enable/disable
 Buffer can store up to 8 events
Configurable Trace Buffer

38. 38
 Trace on triggers set to
variable read and/or write
creates a real-time watch
system
 Limitation: With more than
one variable watch, a
variable which is addressed
infrequently may not be
captured
State Storage: Real-Time Watch

39. 39
 Can create a linear program
sequence before a trigger is
accepted for a break or state
storage event
 Useful if an event occurs only after
a given sequence in the program
has taken place
Trigger Sequencer

40. 40
 Allows a trigger on complex
system sequences
 Restart and reset conditions for
the sequencer can also be
defined
Complex Trigger Sequencer

41. 41
Planned MSP430F2xx for 2005/2006

42. 42
– It includes:
– MSP430F149 flash processor
– Texas Instruments USB interface
using the TUSB3410
– Texas Instruments RS232
interface
using the MAX3221
– TPS3619 Battery-Backup
Supervisor allows uninterrupted
power switching between USB
and batteries
– One-cell power supply based
on the TPS60310 (3.3v from
one AA or AAA battery)
– More Information on this
Web link :
http://www.softbaugh.com/
ProductPage.cfm?strPartNo=USB430
USB430

43. 43
Where to find MSP430 Information
Support
• Asherman@arrowil.com
• 03-9203465
• 052-2240811
MSP430 Web Page
• http://www.msp430.com
• Product List
• Free Tools/Downloads
• Application Reports
• User Guides
• Code Examples
• Third Party Tools
Your Hard Disk
• Shortcut to
“FET Documentation”
• IAR Documents
• FET User’s Guides
• Shortcut to
“FET Examples”
Knowledge Base
• http://www.ti.com
 KnowledgeBase
 Microcontrollers
• Find FAQs
• Find Documentation

44. 44
•Amir Sherman
•Field Application Eng.
•Asherman@arrowil.com

45. 45
Thank You
ForYourTime!