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Fpga &;cpld(by alok singh)

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iNTRODUCTION OF FPGA AND CPLD

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Fpga &;cpld(by alok singh)

  1. 1. Introduction to FPGA & CPLD Devices BY(ALOK SINGH kanpur) alok.lpu@yahoo.com 04/20/18 1
  2. 2. Hierarchy of Logic Implementations Acronyms SPLD = Simple Prog. Logic Device PAL = Prog. Array of Logic CPLD = Complex PLD FPGA = Field Prog. Gate Array ASIC = Application Specific IC Common Resources Configurable Logic Blocks (CLB) • Memory Look-Up Table (LUT) • AND-OR planes • Simple gates Input / Output Blocks (IOB) • Bidirectional, latches, inverters, pullup/pulldowns Interconnect or Routing • Local, internal feedback, and global Logic Standard Logic ASIC Programmable Logic Devices (FPLDs) Gate Arrays Cell-Based ICs Full Custom ICs CPLDsSPLDs (e.g., PALs) FPGAs
  3. 3. • designs must be sent for expensive and time consuming fabrication in semiconductor foundry • bought off the shelf (ready to use) and reconfigured by designers themselves Two competing implementation approaches ASIC Application Specific Integrated Circuit FPGA Field Programmable Gate Array • designed all the way from behavioral description to physical layout • no physical layout design; design ends with a bitstream used to configure a device 04/20/18 3
  4. 4. BlockRAMs BlockRAMs Configurable Logic Blocks I/O Blocks What is an FPGA? Block RAMs 04/20/18 4
  5. 5. Which Way to Go? Off-the-shelf Low development cost Short time to market Reconfigurability High performance ASICs FPGAs Low power Low cost in high volumes (ready-to-use) 04/20/18 5
  6. 6. Other FPGA Advantages • Manufacturing cycle for ASIC is very costly, lengthy and engages lots of manpower • Mistakes not detected at design time have large impact on development time and cost • FPGAs are perfect for rapid prototyping of digital circuits • Easy upgrades like in case of software • Unique applications • reconfigurable computing 04/20/18 6
  7. 7. Major FPGA Vendors SRAM-based FPGAs • Xilinx, Inc. • Altera Corp. • Atmel • Lattice Semiconductor Flash & antifuse FPGAs • Actel Corp. • Quick Logic Corp. Share over 60% of the market 04/20/18 7
  8. 8. Xilinx FPGA Families • Old families • XC3000, XC4000, XC5200 • Old 0.5µm, 0.35µm and 0.25µm technology. Not recommended for modern designs. • High-performance families • Virtex (0.22µm) • Virtex-E, Virtex-EM (0.18µm) • Virtex-II, Virtex-II PRO (0.13µm) • Virtex-4 (0.09µm) • Low Cost Family • Spartan/XL – derived from XC4000 • Spartan-II – derived from Virtex • Spartan-IIE – derived from Virtex-E • Spartan-3 04/20/18 8
  9. 9.  CPLD  Complex Programmable Logic Devices (CPLD)  SPLDs (PLA, PAL) are limited in size due to the small number of input and output pins and the limited number of product terms  Combined number of inputs + outputs < 32 or so  CPLDs contain multiple circuit blocks on a single chip  Each block is like a PAL: PAL-like block  Connections are provided between PAL-like blocks via an interconnection network that is programmable  Each block is connected to an I/O block as well
  10. 10.  Structure of a CPLD PAL-like block (MACRO CELL) I/Oblock I/Oblock I/Oblock I/Oblock Interconnection wires PAL-like block PAL-like blockPAL-like block (MACRO CELL)(MACRO CELL) (MACRO CELL)
  11. 11. Examples of CPLDs and high pin count package types Examples of CPLDsExamples of CPLDs
  12. 12.  Internal Structure of a PAL-like Block  Includes macrocells  Usually about 16 each  Fixed OR planes  OR gates have fan-in between 5-20  XOR gates provide negation ability  XOR has a control input D Q D Q D Q PAL-like block PAL-like block
  13. 13.  More on PAL-like Blocks  CPLD pins are provided to control XOR, MUX, and tri-state gates  When tri-state gate is disabled, the corresponding output pin can be used as an input pin  The associated PAL-like block is then useless  The AND plane and interconnection network are programmable  Commercial CPLDs have between 2-100 PAL-like blocks
  14. 14.  Programming a CPLD  CPLDs have many pins – large ones have > 200  Removal of CPLD from a PCB is difficult without breaking the pins  Use ISP (in system programming) to program the CPLD  JTAG (Joint Test Action Group) port used to connect the CPLD to a computer
  15. 15.  Example CPLD  Use a CPLD to implement the function  f = x1x3x6' + x1x4x5x6' + x2x3x7 + x2x4x5x7 D Q PAL-like block (from interconnection wires) x1 x2 x3 x4 x5 x6 x7 unused 0 0 1 f
  16. 16.  FPGA  SPLDs and CPLDs are relatively small and useful for simple logic devices  Up to about 20000 gates  Field Programmable Gate Arrays (FPGA) can handle larger circuits  No AND/OR planes  Provide logic blocks, I/O blocks, and interconnection wires and switches  Logic blocks provide functionality  Interconnection switches allow logic blocks to be connected to each other and to the I/O pins
  17. 17.  Structure of an FPGA I/O block I/O block I/Oblock I/Oblock logic block interconnection switch
  18. 18.  LUTs  Logic blocks are implemented using a lookup table (LUT)  Small number of inputs, one output  Contains storage cells that can be loaded with the desired values  A 2 input LUT uses 3 MUXes to implement any desired function of 2 variables  Shannon's expansion at work! f 0/1 0/1 0/1 0/1 x1 x2
  19. 19.  Example 2 Input LUT x1 x2 f 0 0 1 0 1 0 1 0 0 1 1 1 f = x1'x2' + x1x2, or using Shannon's expansion: f = x1'(x2') + x1(x2) = x1'(x2'(1) + x2(0)) + x1(x2'(0) + x2(1)) f 1 0 0 1 x 1 x 2
  20. 20.  3 Input LUT  7 2x1 MUXes and 8 storage cells are required  Commercial LUTs have 4-5 inputs, and 16-32 storage cells f 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 x 2 x 3 x 1
  21. 21.  Example FPGA  Use an FPGA with 2 input LUTS to implement the function f = x1x2 + x2'x3  f1 = x1x2  f2 = x2'x3  f = f1 + f2 0 1 0 0 0 1 1 1 0 0 0 1 x1 x2 x2 x3 f 1 f 2 f 1 f 2 f x1 x2 x3 f
  22. 22.  Another Example FPGA  Use an FPGA with 2 input LUTS to implement the function f = x1x3x6' + x1x4x5x6' + x2x3x7 + x2x4x5x7  Fan-in of expression is too large for FPGA (this was simple to do in a CPLD)  Factor f to get sub-expressions with max fan-in = 2  f = x1x6'(x3 + x4x5) + x2x7(x3 + x4x5) = (x1x6' + x2x7)(x3 + x4x5)  Could use Shannon's expansion instead  Goal is to build expressions out of 2-input LUTs
  23. 23. 0 0 0 1 0 1 1 1 x4 x5 A B C D x1 x6 x4 f 0 1 1 1 0 0 0 1 x3 C D E E f x2 x7 x5 x3 0 0 0 1 x2 x7 B 0 0 1 0 x1 x6 A  FPGA Implementation  f = (x1x6' + x2x7)(x3 + x4x5)
  24. 24. Xilinx9500 series CPLD Features: • High-performance • 5 ns pin-to-pin logic delays on all pins • Freq fCNT to 125 MHz • Large density range: 36 to 288 macrocells with 800 to 6,400 usable gates • 5V in-system programmable • 90 product terms drive any or all of 18 macrocells • Global and product term clocks, output enables, set and reset signals • Extensive IEEE Std 1149.1 boundary-scan (JTAG) support • Programmable power reduction mode in each macrocell • Slew rate control on individual outputs • User programmable ground pin capability • Extended pattern security features for design protection • High-drive 24 mA outputs 04/20/18 24
  25. 25. 25 XilinxXilinx Product XC7000 Series XC7200 Series – Each block has 9 macrocells – Each macrocells includes two OR-gates – Each OR-gates is input to a two-bit ALU XC7300 Series : Enhanced version of 7200 XC9500 Series In-system programmability
  26. 26. 26 XC9536 XC9572 XC95108 XC95144 XC95216 XC95288 Macrocells 36 72 108 144 216 288 Usable Gates 800 1,600 2,400 3,200 4,800 6,400 Registers 36 72 108 144 216 288 t PD (ns) 5 7.5 7.5 7.5 10 10 t SU (ns) 3.5 4.5 4.5 4.5 6.0 6.0 t CO (ns) 4.0 4.5 4.5 4.5 6.0 6.0 f CNT (MHz) 100 125 125 125 111.1 111.1 f SYSTEM (MHz) 100 83.3 83.3 83.3 66.7 66.7 Note: f CNT = Operating frequency for 16-bit counters f SYSTEM = Internal operating frequency for general purpose system designs spanning multiple FBs. Xilinx: XC9500 Device FamilyXilinx: XC9500 Device Family
  27. 27. 27 (a) CPLDinaQuadFlat Pack (QFP) package Printed circuit board To computer (b) JTAGprogramming CPLD Packaging and Programming (a) a CPLD in a Quad Flat Pack (QFP) IC package (b) Set up for programming the PCB-mounted CPLD using JTAG (a) (b)
  28. 28. 28 XSA-100 BoardXSA-100 Board logic density of 100,000logic density of 100,000 gates with Spartan-IIgates with Spartan-II FPGAFPGA 16-Mbyte synchronous16-Mbyte synchronous DRAMDRAM XC9572 interface CPLDXC9572 interface CPLD
  29. 29. 29 XSA-100 BoardXSA-100 Board External connections to the XSAExternal connections to the XSA board.board. Parallel port for programmingParallel port for programming External power supplyExternal power supply VGA port to display signalsVGA port to display signals PS/2 port for pointing operationsPS/2 port for pointing operations
  30. 30. 30 XilinxXilinx Architecture of Xilinx 9500 CPLDsArchitecture of Xilinx 9500 CPLDs
  31. 31. 31 Xilinx: XC9500 Device FamilyXilinx: XC9500 Device Family Proprietary systems are beginning to give way to a standard from the Joint Test Action Group (JTAG)
  32. 32. 32 Xilinx: XC9500 Device FamilyXilinx: XC9500 Device Family Each XC9500 device is a subsystem consisting of multiple Function Blocks (FBs) and I/O Blocks (IOBs) fully interconnected by the FastCONNECT switch matrix. The IOB provides buffering for device inputs and outputs. Each FB provides programmable logic capability with 36 inputs and 18 outputs. The FastCONNECT switch matrix connects all FB outputs and input signals to the FB inputs. For each FB, 12 to 18 outputs (depending on package pin-count) and associated output enable signals drive directly to the IOBs.
  33. 33. 33 Each Function Block is comprised of 18 independent macrocells, each capable of a combinatorial or registered function. The FB also receives global clock, output enable, and set/reset signals. The FB generates 18 outputs that drive the FastCONNECT switch matrix. These 18 outputs and their corresponding output enable signals also drive the IOB. Logic within the FB is implemented using a sum-of-products representation. Thirty-six inputs provide 72 true and complement signals into the programmable AND-array to form 90 product terms. Any number of these product terms, up to the 90 available, can be allocated to each macrocell by the product term allocator. Xilinx: XC9500 Device FamilyXilinx: XC9500 Device Family
  34. 34. 34 Each FB (except for the XC9536) supports local feedback paths that allow any number of FB outputs to drive into its own programmable AND-array without going outside the FB. These paths are used for creating very fast counters and state machines where all state registers are within the same FB. Xilinx: XC9500 Device FamilyXilinx: XC9500 Device Family
  35. 35. 35 Xilinx: XC9500 Device FamilyXilinx: XC9500 Device Family Each XC9500 macrocell may be individually configured for a combinatorial or registered function. The macrocell and associated FB logic is shown in Figure. Five direct product terms from the AND-array are available for use as primary data inputs (to the OR and XOR gates) to implement combinatorial functions, or as control inputs including clock, set/reset, and output enable. The product term allocator associated with each macrocell selects how the five direct terms are used. The macrocell register can be configured as a D-type or T-type flip-flop, or it may be bypassed for combinatorial operation. Each register supports both asynchronous set and reset operations. During power-up, all user registers are initialized to the user- defined preload state (default to 0 if unspecified).
  36. 36. 36 MacrocellMacrocell f 1 back to AND plane D Q Clock Select Enable Flip-flop OR gate from PAL 0 1
  37. 37. 37 Xilinx: XC9500 Device FamilyXilinx: XC9500 Device Family
  38. 38. 38 All global control signals are available to each individual macrocell, including clock, set/reset, and output enable signals. As shown in Figure 4, the macrocell register clock originates from either of three global clocks or a product term clock. Both true and complement polarities of a GCK pin can be used within the device. A GSR input is also provided to allow user registers to be set to a user-defined state. Xilinx: XC9500 Device FamilyXilinx: XC9500 Device Family
  39. 39. 39 Xilinx: XC9500 Device FamilyXilinx: XC9500 Device Family The FastCONNECT switch matrix connects signals to the FB inputs, as shown in Figure. All IOB outputs (corresponding to user pin inputs) and all FB outputs drive the FastCONNECT matrix. Any of these (up to a FB fan-in limit of 36) may be selected, through user programming, to drive each FB with a uniform delay. The FastCONNECT switch matrix is capable of combining multiple internal connections into a single wired-AND output before driving the destination FB. This provides additional logic capability and increases the effective logic fan-in of the destination FB without any additional timing delay. This capability is available for internal connections originating from FB outputs only. It is automatically invoked by the development software where applicable.
  40. 40. 40 Xilinx: XC9500 Device FamilyXilinx: XC9500 Device Family
  41. 41. 41 Xilinx: XC9500 Device FamilyXilinx: XC9500 Device Family The I/O Block (IOB) interfaces between the internal logic and the device user I/O pins. Each IOB includes an input buffer, output driver, output enable selection multiplexer, and user programmable ground control. See Figure 10 for details. The input buffer is compatible with standard 5 V CMOS, 5 V TTL and 3.3 V signal levels. The input buffer uses the internal 5 V voltage supply (V CCINT ) to ensure that the input thresholds are constant and do not vary with the V CCIO voltage.
  42. 42. 42 Xilinx: XC9500 Device FamilyXilinx: XC9500 Device Family XC9500 devices are programmed in-system via a standard 4-pin JTAG protocol. In-system programming offers quick and efficient design iterations and eliminates package handling. The Xilinx development system provides the programming data sequence using a Xilinx download cable, a third-party JTAG development system, JTAG-compatible board tester, or a simple micro- processor interface that emulates the JTAG instruction sequence.
  43. 43. 43 Xilinx: XC9500 Device FamilyXilinx: XC9500 Device Family XC9500 devices incorporate advanced data security features which fully protect the programming data against unauthorized reading or inadvertent device erasure/reprogramming. Table 3 shows the four different security settings available. The read security bits can be set by the user to prevent the internal programming pattern from being read or copied. When set, they also inhibit further program operations but allow device erase. Erasing the entire device is the only way to reset the read security bit. The write security bits provide added protection against accidental device erasure or reprogramming when the JTAG pins are subject to noise, such as during system power-up. Once set, the write-protection may be deactivated when the device needs to be reprogrammed with a valid pattern.
  44. 44. 44 Xilinx: XC9500 Device FamilyXilinx: XC9500 Device Family Basic Timing Model
  45. 45. XC9500 Product term allocator and macrocell 04/20/18 45
  46. 46. Xilinx 3000 04/20/18 46
  47. 47. (Not having a fine texture) 04/20/18 47
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