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AMD Heterogeneous Uniform Memory Access
- 1. AMD heterogeneous Uniform Memory Access PHIL ROGERS, CORPORATE FELLOW JOE MACRI, CORPORATE VICE PRESIDENT & PRODUCT CTO SASA MARINKOVIC, SENIOR MANAGER, PRODUCT MARKETING AMD Confidential, under embargo until Apr 30, 12:01 AM EST
- 2. ABOUT HSA
- 3. 3AMD Confidential, under embargo until Apr 30, 12:01 AM EST 10 YEARS AGO… Memory Controller on the chip HyperTransport64-bit extensions AMD Opteron
- 4. 4AMD Confidential, under embargo until Apr 30, 12:01 AM EST 0 500 1000 1500 2000 2500 3000 3500 4000 4500 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012CPU GFLOPS GPU GFLOPS HOW DO WE UNLOCK THIS PERFORMANCE? GPU COMPUTE CAPABILITY IS MORE THAN THAT OF THE CPU See slide 24 for details 10X
- 5. 5AMD Confidential, under embargo until Apr 30, 12:01 AM EST WHAT IS HSA? SERIAL WORKLOADS PARALLEL WORKLOADS hUMA (MEMORY) APU ACCELERATED PROCESSING UNIT An intelligent computing architecture that enables CPU, GPU and other processors to work in harmony on a single piece of silicon by seamlessly moving the right tasks to the best suited processing element
- 6. 6AMD Confidential, under embargo until Apr 30, 12:01 AM EST HSA EVOLUTION Uniform memory access for CPU and GPU GPU can access CPU memory Integrate CPU and GPU in silicon Capabilities Simplified data sharing Improved compute efficiency Unified power efficiency Benefits
- 7. 7AMD Confidential, under embargo until Apr 30, 12:01 AM EST WHAT IS hUMA? heterogeneous UNIFORM MEMORY ACCESS
- 8. 8AMD Confidential, under embargo until Apr 30, 12:01 AM EST UNDERSTANDING UMA Original meaning of UMA is Uniform Memory Access • Refers to how processing cores in a system view and access memory • All processing cores in a true UMA system share a single memory address space Introduction of GPU compute created systems with Non-Uniform Memory Access (NUMA) • Require data to be managed across multiple heaps with different address spaces • Add programming complexity due to frequent copies, synchronization, and address translation HSA restores the GPU to Uniform memory Access • Heterogeneous computing replaces GPU Computing
- 9. 9AMD Confidential, under embargo until Apr 30, 12:01 AM EST INTRODUCING hUMA CPU APU APU with HSA Memory CPU CPU CPU CPU UMA CPU Memory CPU CPU CPU CPU NUMA GPU GPUGPU GPU GPU Memory Memory CPU CPU CPU CPU hUMA GPU GPU GPU GPU
- 10. 10AMD Confidential, under embargo until Apr 30, 12:01 AM EST hUMA KEY FEATURES BI-DIRECTIONAL COHERENT MEMORY Any updates made by one processing element will be seen by all other processing elements - GPU or CPU PAGEABLE MEMORY GPU can take page faults, and is no longer restricted to page locked memory ENTIRE MEMORY SPACE CPU and GPU processes can dynamically allocate memory from the entire memory space
- 11. 11AMD Confidential, under embargo until Apr 30, 12:01 AM EST hUMA KEY FEATURES Physical Memory GPU HW Coherency Virtual Memory CPU Entire memory space: Both CPU and GPU can access and allocate any location in the system’s virtual memory space CacheCache Coherent Memory: Ensures CPU and GPU caches both see an up-to-date view of data Pageable memory: The GPU can seamlessly access virtual memory addresses that are not (yet) present in physical memory
- 12. 12AMD Confidential, under embargo until Apr 30, 12:01 AM EST WITHOUT POINTERS* AND DATA SHARING *A Pointer is a named variable that holds a memory address. It makes it easy to reference data or code segments by a name and eliminates the need for the developer to know the actual address in memory. Pointers can be manipulated by the same expressions used to operate on any other variable GPUCPU CPU Memory GPU Memory | | | | || | | | | | | | | || | | | | Without hUMA: • CPU explicitly copies data to GPU memory • GPU completes computation • CPU explicitly copies result back to CPU memory Only the data array can be copied since GPU cannot follow embedded data-structure links
- 13. 13AMD Confidential, under embargo until Apr 30, 12:01 AM EST GPU With hUMA: • CPU simply passes a pointer to GPU • GPU completes computation • CPU can read the result directly – no copying needed! CPU CPU / GPU Uniform Memory | | | | || | | | | *A Pointer is a named variable that holds a memory address. It makes it easy to reference data or code segments by a name and eliminates the need for the developer to know the actual address in memory. Pointers can be manipulated by the same expressions used to operate on any other variable CPU can pass a pointer to entire data structure since the GPU can now follow embedded links WITH POINTERS* AND DATA SHARING
- 14. 14AMD Confidential, under embargo until Apr 30, 12:01 AM EST TOP 10 REASONS TO GO FULLY HARDWARE COHERENT ON GPU/APU 1. Much easier for programmers 2. No need for special APIs 3. Move CPU multi-core algorithms to the GPU without recoding for absence of coherency 4. Allow finer grained data sharing than software coherency 5. Implement coherency once in hardware, rather than N times in different software stacks 6. Prevent hard to debug errors in application software 7. Operating systems prefer hardware coherency – they do not want the bug reports to the platform 8. Probe filters and directories will maintain power efficiency 9. Full coherency opens the doors to single source, native and managed code programming for heterogeneous platforms 10. Optimal architecture for heterogeneous computing on APUs and SOCs AMD Confidential, under embargo until Apr 30, 12:01 AM EST
- 15. 15AMD Confidential, under embargo until Apr 30, 12:01 AM EST hUMA FEATURES Access to Entire Memory Space Pageable memory Bi-directional Coherency Fast GPU access to system memory Dynamic Memory Allocation
- 16. hUMA BENEFITS
- 17. 17AMD Confidential, under embargo until Apr 30, 12:01 AM EST BENEFITS OF HSA
- 18. 18AMD Confidential, under embargo until Apr 30, 12:01 AM EST UNIFORM MEMORY BENEFITS TO DEVELOPERS EASE AND SIMPLICITY OF PROGRAMMING Single, standard computing environments LOWER DEVELOPMENT COST More efficient architecture enables less people to do the same work SUPPORT FOR MAINSTREAM PROGRAMING LANGUAGES Python, C++, Java
- 19. 19AMD Confidential, under embargo until Apr 30, 12:01 AM EST BETTER EXPERIENCES Radically different user experiences LONGER BATTERY LIFE Less power at the same performance MORE PERFORMANCE Getting more performance from the same form factor BENEFITS TO CONSUMERS
- 20. 20AMD Confidential, under embargo until Apr 30, 12:01 AM EST SUPPORT FROM MAJOR INDUSTRY PLAYERS For more information go to: http://hsafoundation.com/ Source http://pinterest.com/pin/193021534001931884/
- 21. 21AMD Confidential, under embargo until Apr 30, 12:01 AM EST HSA Nov 11 – 14, 2013 San Jose McEnery Convention Center 14 Different Tracks with over 140 Individual Presentations
- 22. THANK YOU
- 23. 23AMD Confidential, under embargo until Apr 30, 12:01 AM EST GFLOPS Year CPU CPU GFLOPS GPU (RADEON) GPU GFLOPS 2002 Pentium 4 (Northwood) 12.24 9700 Pro 31.2 2003 Pentium 4 (Northwood) 12.8 9800 XT 36.48 2004 Pentium 4 (Prescott 15.2 X850 XT 103.68 2005 15.2 X1800 XT 134.4 2006 Core 2 Duo 23.44 X1950 375 2007 Core 2 Quad 48 HD 2900 XT 473.6 2008 Q9650 96 HD 4870 1200 2009 Core i7 960 102.4 HD 5870 2720 2010 Core i7 970 153.6 HD 6970 2703 2011 Core i7 3960X 316.8 HD7970 3789 2012 Core i7 3970X 336 HD 7970 GHz Edition 4301
- 24. 24AMD Confidential, under embargo until Apr 30, 12:01 AM EST POTENTIAL MARKET IS HUGE Notebooks Servers Desktops Embedded Game Consoles Tablets
- 25. 25AMD Confidential, under embargo until Apr 30, 12:01 AM EST DISCLAIMER The information presented in this document is for informational purposes only and may contain technical inaccuracies, omissions and typographical errors. The information contained herein is subject to change and may be rendered inaccurate for many reasons, including but not limited to product and roadmap changes, component and motherboard version changes, new model and/or product releases, product differences between differing manufacturers, software changes, BIOS flashes, firmware upgrades, or the like. AMD assumes no obligation to update or otherwise correct or revise this information. However, AMD reserves the right to revise this information and to make changes from time to time to the content hereof without obligation of AMD to notify any person of such revisions or changes. AMD MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE CONTENTS HEREOF AND ASSUMES NO RESPONSIBILITY FOR ANY INACCURACIES, ERRORS OR OMISSIONS THAT MAY APPEAR IN THIS INFORMATION. AMD SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. IN NO EVENT WILL AMD BE LIABLE TO ANY PERSON FOR ANY DIRECT, INDIRECT, SPECIAL OR OTHER CONSEQUENTIAL DAMAGES ARISING FROM THE USE OF ANY INFORMATION CONTAINED HEREIN, EVEN IF AMD IS EXPRESSLY ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. ATTRIBUTION © 2013 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD Arrow logo, Radeon, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Other names and logos are used for informational purposes only and may be trademarks of their respective owners.
Notas do Editor
- Instead, it fell to AMD to take the logical step and simply extend the x86 architecture to include 64-bit instructions, resulting in what the firm called AMD64.At a stroke, AMD was offering businesses the chance to give a performance boost to existing applications, with a seamless upgrade path to 64-bit software when this became available.Until that point, multiple processor chips simply shared a bus connection with the rest of the system. This arrangement created a memorybandwidth bottleneck that effectively made PC servers with more than four sockets impractical without a specialist chipset.AMD solved this problem by giving each Opteron chip its own directly connected pool of memory, and introduced a high-speed point-to-point interconnect called HyperTransport to link the chips to each other and the rest of the system in a switched fabric."By moving the memory controller onto the processor die, it runs at core frequency, and each processor added [to the system] adds another memory controller, so memory bandwidth scales with the number of processors," explained Mark Tellez, then AMD's server/workstation marketing manager.
- HSA will empower software developers to easily innovate and unleash new levels of performance and functionality on all your modern devices and lead to powerful new experiences such as visually rich, intuitive, human-like interactivity.
- Power efficient – running parallel code on the GPU; eliminate copiesEasy to program – High level languages, task parallel runtimesReady for tomorrow’s workloads, increasingly dominated by parallel processingBuilt from established technology and operating principles. We take the architecture that has worked for SMP and multicore systems and extend it to the GPUHSA is open. This is so important. Multivendor architectures spawn large ecosystemsBroadly supported across multiple vendors. HSA is an architecture that spans from the smart phone to the super computer. Phones, tablets, fanless notebooks, desktops, all in ones, workstations, cloud servers, HPC. Go to hsafoundation.com to see the list of industry leaders who have joined us already.
- In 2012, there was 2012 billion smart connected devices. HSA Foundation members made up approx. 800 million of those, Intel about 300 million and nvidia around 100 or less. If you assume similar mamber share by these companies in 2016, HSA Foundation member companies will be in over 1.6 billion devices
- $37 Billion for existing PC markets and 10 Billion for new markets. (Game consoles represent $1 billion)Profit pool analysis highlights market attractiveness by contrasting processor revenue TAM with near term estimated market growth rates. In the near term, existing profit pool markets are estimated at 2X as large as the that of new entrants but caution should be exercised as the new market entrants are enjoying fast adoption and growth highlighting the need to investigate strategic choices and enhancements. Question: Even though ARM-based SOCs for tablets/smartphones are BSOs, should we make a trade-off of core market investments to deliver one? Why?If we had $50M-100M incremental R&D dollars, what would the next priority SOC be? ARM? Client-X86? Server?