this is the system diagram for AMD PGA 452 Processor VIA KT333/ VT8233A-CE Chipset Winbond 8369 HF-VF LPC I/O

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MS-6380E ATX Title Page
AMD PGA 462 Processor Cover Sheet 1 HISTORY 47
VIA KT333 / VT8233A-CE Chipset
D D
Block Diagram 2
Winbond 83697HF-VF LPC I/O GPIO SPEC 3
AMD 462 PGA Socket 4,5
Clock Synthesizer 6
KT333 7,8,9
System Memory 10,11,12
DDR Terminations 13,14
AGP PRO SLOT 15
VT8233-CE 16,17,18
PCI Connectors 19,20,21
CNR RISER / DLED 22
C C
AC'97 Codec 23
Audio SPDIF / 6 Channel connector 24,25
IDE RAID Controller / Connectors 26,27
ATA 66/100 Connectors 28
USB 2.0 Host Controller 29
Front USB Port 30
Rear USB Port 31
LPC I/O 32
MS-6380E ver:0B
Standard BOM (without IDE RAID /
Hardware monitor 33
USB2.0 HC)
System ROM 34
SMT 861
B B
Keyboard/Mouse Connectors 35 DIP 78
LPT/COM Port 36 Total 939
Game Port 37 Option A BOM (with IDE RAID /
HIP6301 / 6302 38 without USB2.0 HC)
CPU Ratio / Vcore / LED Setting 39 SMT 934
AMD CPU Thermal Protection 40 DIP 80
Total 1014
MS-5 ACPI POWER 41
Power Mangement 42 Option B BOM (with IDE RAID /
USB2.0 HC)
PowerOK Circuit 43
A
Front Panel 44 SMT 992 A
DIP 85
Pull-up Resistors 45
Total 1077
BULK / Decoupling 46
Micro Star Restricted Secret
Title Rev
Cover Sheet
Document Number 0B
MS-6380E
MICRO-STAR INT'L Last Revision Date:
CO.,LTD. Wednesday, March 13, 2002
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan Sheet
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2. 5 4 3 2 1
Block Diagram
AMD Socket 462
D D
FSB
A DDR
AGP 4X /Fast Write
G
C
P KT333 C
P
R
5 PCI Slots
O
VLINK
Dual ATA
PCI-33 100/133
VT8235
B B
USB 2.0 USB 2.0 Host LPC BUS
PORT X4 Controller
IDE RAID
Controller
IEEE 802.3MAC( MII)
SUPER I/O ROM
C
USB
N
R
AC-LINK
X BUS
AC'97 Codec
A A
Dual USB 1.1 OHCI
/2.0 EHCI 6 Ports
Micro Star Restricted Secret
Title Rev
Block Diagram
Document Number 0B
MS-6380E
MICRO-STAR INT'L Last Revision Date:
CO.,LTD. Monday, March 11, 2002
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan Sheet
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3. 5 4 3 2 1
GPIO FUNCTION
VT8233 GPIO Function Define
PIN NAME Function define PIN NAME Function define
D D
GPO0 (VSUS33) GPO0 GPI0 GPI0
GPO1/SUSA#(VSUS33) SUSA# GPI1 ATADET0=>Detect IDE1 ATA100/66
GPO2/SUSB#(VSUS33) SUSB# GPI2/EXTSMI# EXTSMI#
GPO3/SUSST1#(VSUS33) SUSST1# GPI3/RING# RING#
GPO4/SUSCLK(VSUS33) SUSCLK GPI4/LID# ATADET1=>Detect IDE2 ATA100/66
GPO5/CPUSTP# CPUSTP# GPI5/BATLOW# Exteranl Pull up to 3VDUAL
GPO6/PCISTP# PCISTP# GPI6/PME# PME#
GPO7/SLP# SLP# GPI7/SMBALRT# Exteranl Pull up to 3VDUAL PCI
GPO8/GPI8/IPBIN0 Exteranl Pull up to VCC3 GPI16/INTRUDER# Exteranl Pull down DEVICES INT# IDSEL REQ#/GNT# CLOCK
GPO9/GPI9/IPBIN1 Exteranl Pull up to VCC3 GPI17/CPUMISS Exteranl Pull up to 3VDUAL INT#A PREQ#0
C PCI SLOT 1 INT#B AD16 PCICLK1 C
INT#C PGNT#0
GPO10/GPI10/IPBRDFR GPI10(PRI_DOWN) GPI18/AOLGP1/THRM# THRM# INT#D
GPO11/GPI11/IPBRDCK GPI19/IORDY Exteranl Pull up to VCC3 INT#B PREQ#1
PCI SLOT 2 INT#C AD17 PCICLK2
INT#D PGNT#1
GPO12/GPI12/IPBOUT0 GPO12 INT#A
DDR Voltage SET1 SET2
GPO13/GPI13/IPBOUT1 GPO13 INT#C PREQ#2
PCI SLOT 3 INT#D AD18 PCICLK3
2.5V 1 1 INT#A PGNT#2
GPO14/GPI14/IPBTDFR GPO14 INT#B
2.6V 0 1
GPO15/GPI15/IPBTDCK GPO15 2.7V 1 0 INT#D PCIREQ#3
PCI SLOT 4 INT#A AD19 PCICLK4
2.8V 0 0 INT#B PCIGNT#3
GPO16/SA16/STRAP CPU FID0 Strapping INT#C
GPO17/SA17/STRAP CPU FID1 Strapping INT#B PCIREQ#4
PCI SLOT 5 INT#C AD21 PCICLK5
INT#D PCIGNT#4
GPO18/SA18/STRAP CPU FID2 Strapping INT#A
B GPO19/SA19/STRAP CPU FID3 Strapping PCIREQ#6 B
INT#C USB_PCLK
GPO20/GPI20 USB 2.0 HC INT#D AD22 PCIGNT#6
/ACSDIN2/PCS0#/EI GPO20 INT#A
GPO21/GPI21/ACSDIN3
/PCS1#/SLPBTN# GPO21 PCIGNT#7
IDE RAID HC INT#D AD23 ATAPCLK
PCIREQ#7
GPO22/GPI22/IOR# GPO22
GPO23/GPI23/IOW# GPO23
GPO24/GPI24/GPIOA
GPO25/GPI25/GPIOC
GPO26/GPI26/SMBDT2
(VSUS33) SMBDATA2/Slave SMBUS
GPO27/GPI27/SMBCK2
(VSUS33) SMBCLK2/Slave SMBUS
GPO28/GPI28/
APICD0/APICCS#
GPO29/GPI29/
A APICD1/APICACK# A
GPO30/GPI30/GPIOD
Micro Star Restricted Secret
GPO31/GPI31/GPIOE Title Rev
GPIO Spec.
Document Number 0B
MS-6380E
MICRO-STAR INT'L Last Revision Date:
CO.,LTD. Monday, March 11, 2002
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan Sheet
http://www.msi.com.tw 3 of 48
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4. 5 4 3 2 1
SOCKET 462 Part 1
**All CPU interface are 2.5V tolerant**
VCORE
VCC3
CPU1A
SDATA#[0..63] SDATA#0 AA35 AE1 A20M# CPURST# VCORE DBREQ# R33 510
7 SDATA#[0..63] SDATA0 A20M A20M# 16
SDATA#1 W37 AG1 FERR
SDATA#2 SDATA1 FERR CPUINIT#
W35 SDATA2 INIT AJ3 CPUINIT# 16 R47
SDATA#3 Y35 AL1 INTR C37 4.7K
SDATA#4 SDATA3 INTR IGNNE# INTR 16 PLLTEST# R37 510
U35 SDATA4 IGNNE AJ1 X_100P R57
SDATA#5 NMI IGNNE# 16
U33 SDATA5 NMI AN3 680
SDATA#6 CPURST# NMI 16 RN2
S37 SDATA6 RESET AG3
SDATA#7 SMI# CPURST# 41 FERR# CPU_TCK
D
S33 SDATA7 SMI AN5 SMI# 16 FERR# 16 1 2 D
SDATA#8 AA33 AC1 STPCLK# CPU_TMS 3 4
SDATA#9 SDATA8 STPCLK STPCLK# 16 Q19 CPU_TRST#
AE37 SDATA9 5 6
SDATA#10 AC33 AE3 FERR CPU_TDI 7 8
SDATA#11 SDATA10 PWROK K7PWRGD 41
AC37 2N3904S
SDATA#12 SDATA11 8P4R-510
Y37 SDATA12
SDATA#13 AA37 N1 APICCLK_CPU
SDATA#14 SDATA13 PICCLK APICCLK_CPU 6 VCORE
AC35 N3 APICD0#
SDATA#15 SDATA14 PICD0/BYPASSCLK APICD1# APICD0# 16
S35 SDATA15 PICD1/BYPASSCLK N5 APICD1# 16
SDATA#16 Q37
SDATA#17 SDATA16 COREFB#
Q35 SDATA17 COREFB- AG13 COREFB# 38
SDATA#18 N37 AG11 COREFB R68
SDATA#19 SDATA18 COREFB+ COREFB 38
J33 SDATA19 100
SDATA#20 G33 AN17 CPUCLK_R for test only 0.6 * VCORE
SDATA#21 SDATA20 CLKIN CPUCLK#_R VCC2_5
G37 SDATA21 CLKIN AL17
SDATA#22
SDATA#23
E37 SDATA22 Pull to 2.5V VREF_SYS
G35 SDATA23 RSTCLK AN19
SDATA#24 Q33 AL19
SDATA#25 SDATA24 RSTCLK APICD0# R66 330
N33 SDATA25 C46 C45 R69
SDATA#26 L33 AL21 CLKOUT APICD1# R62 330 103P 104P 100
SDATA#27 SDATA26 K7CLKOUT CLKOUT#
N35 SDATA27 K7CLKOUT AN21
SDATA#28 L37
SDATA#29 SDATA28 VCORE
J37 SDATA29 C32
SDATA#30 A37 AJ13 X_39P
SDATA#31 SDATA30 ANALOG
E35 SDATA31
SDATA#32 E31 AA5 VREFMODE
SDATA#33 SDATA32 SYSVREFMODE VREF_SYS
E29 SDATA33 VREF_SYS W5
SDATA#34 A27 R78 R81 VCORE
SDATA34 6 CPUCLK
SDATA#35 A25 AC5 ZN 100 100
SDATA#36 SDATA35 ZN ZP C66
E21 SDATA36 ZP AE5
C SDATA#37 C23 CPUCLK_R R82 60.4RST C
SDATA#38 SDATA37 PLLBP#
C27 SDATA38 PLLBYPASS AJ25
SDATA#39 A23 AN15 680P
SDATA#40 SDATA39 PLLBYPASSCLK
A35 SDATA40 PLLBYPASSCLK AL15
SDATA#41 C35 R85
SDATA#42 SDATA41 PLLMON1 VCORE
C33 SDATA42 PLLMON1 AN13 301RST
SDATA#43 C31 AL13 PLLMON2
SDATA#44 SDATA43 PLLMON2 PLLTEST#
A29 SDATA44 PLLTEST AC3 R77 R80
SDATA#45 C29 100 100 C39 VCORE C72
SDATA#46 SDATA45 CPUCLK#_R R87 60.4RST
E23 SDATA46 X_225P/0805
SDATA#47 C25 S1 SCANCLK1
SDATA#48 SDATA47 SCANCLK1
SDATA#49
E17 SDATA48 SCANCLK2 S5 SCANCLK2
SINTVAL
COREFB R64 10K 680P close Socket 462
E13 SDATA49 SCANINTEVAL S3 6 CPUCLK#
SDATA#50 E11 Q5 SSHIFTEN C40
SDATA#51 SDATA50 SCANSHIFTEN
C15 SDATA51 X_106P/0805
SDATA#52 E9 AA1
SDATA#53 SDATA52 DBRDY DBREQ# COREFB# R67 10K VCORE
A13 SDATA53 DBREQ AA3
SDATA#54 C9 AL3 FLUSH#
SDATA#55 SDATA54 FLUSH
A9 SDATA55 C43
SDATA#56 C21 Q1 CPU_TCK
SDATA#57 SDATA56 TCK CPU_TDI X_105P
A21 SDATA57 TDI U1 R34
SDATA#58 E19 U5 for internal
SDATA#59 SDATA58 TDO CPU_TMS X_1K
C19 SDATA59 TMS Q3 VREFSYS
SDATA#60 C17 U3 CPU_TRST#
SDATA#61 SDATA60 TRST VREFMODE
A11 SDATA61
SDATA#62 A17
SDATA#63 SDATA62 VID0 VCORE
A15 SDATA63 VID0 L1 VID0 39
L3 VID1 RN9 R30
VID1 VID1 39
L5 VID2 CPUINIT# 1 2 270
VID2 VID2 39
DICLK#[0..3] DICLK#0 W33 L7 VID3 IGNNE# 3 4
B 7 DICLK#[0..3] DICLK#1 SDATAINCLK0 VID3 VID3 39 B
J35 J7 VID4 CPURST# 5 6
DICLK#2 SDATAINCLK1 VID4 VID4 39
E27 A20M# 7 8
DICLK#3 SDATAINCLK2
E15 SDATAINCLK3
DIVAL# FID0 W1 FID0
FID1 FID0 39
8P4R-680 VREFMODE=Low=No voltage scaling
7 DIVAL# AN33 SDATAINVAL FID1 W3 FID1 39
Y1 FID2 RN10
DOCLK#0 FID2 FID2 39
7 DOCLK#[0..3] DOCLK#[0..3] AE35 Y3 FID3 STPCLK# 1 2
DOCLK#1 SDATAOUTCLK0 FID3 FID3 39 VCORE
C37 NMI 3 4
DOCLK#2 SDATAOUTCLK1 SMI#
A33 SDATAOUTCLK2 5 6
DOCLK#3 C11 U37 INTR 7 8 ZN R38 40.2RST
SDATAOUTCLK3 SCHECK0
SCHECK1 Y33
DOVAL# AL31 L35 8P4R-680 ZP R39 56.2RST
SDTATOUTVAL SCHECK2
SCHECK3 E33
AIN#0 AJ29 E25 FLUSH# R56 680
AIN#1 SADDIN0 SCHECK4 PLLBP#
AL29 SADDIN1 SCHECK5 A31 R99 680 match the transmission line
7 AIN#[2..14] AIN#[2..14] AIN#2
AIN#3
AG33 SADDIN2 SCHECK6 C13
PLLMON1 R72 56
Push-pull compensation circuit
AJ37 SADDIN3 SCHECK7 A19
AIN#4 AL35 PLLMON2 R70 56
AIN#5 SADDIN4
AE33 SADDIN5 SADDOUT0 J1
AIN#6 AJ35 J3 VCORE
AIN#7 SADDIN6 SADDOUT1 AOUT#2 AOUT#[2..14] RN24
AG37 SADDIN7 SADDOUT2 C7 AOUT#[2..14] 7
AIN#8 AL33 A7 AOUT#3 1 2
AIN#9 SADDIN8 SADDOUT3 AOUT#4 RN30 CLKOUT
AN37 SADDIN9 SADDOUT4 E5 3 4
AIN#10 AL37 A5 AOUT#5 AIN#0 1 2 CLKOUT# 5 6
AIN#11 SADDIN10 SADDOUT5 AOUT#6 AIN#1
AG35 SADDIN11 SADDOUT6 E7 3 4 7 8
AIN#12 AN29 C1 AOUT#7 DOVAL# 5 6
AIN#13 SADDIN12 SADDOUT7 AOUT#8 FILVAL# 8P4R-100
AN35 SADDIN13 SADDOUT8 C5 7 8
AIN#14 AN31 C3 AOUT#9
SADDIN14 SADDOUT9 AOUT#10 8P4R-270
SADDOUT10 G1
AOUT#11
* Trace lengths of CLKOUT
A 7 AICLK# AJ33 E1 A
SADDINCLK SADDOUT11
A3 AOUT#12 and -CLKOUT are between
SADDOUT12
7 CFWDRST
CFWDRST
CONNECT
AJ21 CLKFWDRST SADDOUT13 G5 AOUT#13 2" and 3"
AL23 G3 AOUT#14
7 CONNECT CONNECT SADDOUT14
7 PROCDRY
PROCDRY
FILVAL#
AN23 PROCRDY RN1
Micro Star Restricted Secret
AJ31 SFILLVAL SADDOUTCLK E3 AOCLK# 7
SSHIFTEN 1 2 Title Rev
N12-4620011-F02 SCANCLK1 3 4 SOCKET 462 Part 1
SINTVAL 5 6 Document Number 0B
SCANCLK2 7 8 MS-6380E
MICRO-STAR INT'L Last Revision Date:
8P4R-10K CO.,LTD. Monday, March 11, 2002
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan Sheet
http://www.msi.com.tw 4 of 48
5 4 3 2 1