IEEE_RFIC 2007

RMO3C-2 RFIC, 3-5 June 2007, Honolulu, Hawaii Frequency Synthesizer & FSK Modulator for IEEE 802.15.4 Based Applications W. Rahajandraibe , L. Zaïd, V. Cheynet de Beaupré and G. Bas L2MP – University of Provence / STMicroelectronics FRANCE

Outline ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

FSK modulation with Fractionnal PLL FSK Modulation ,[object Object],[object Object],[object Object],[object Object],[object Object],Two points  FSK modulation ,[object Object],[object Object],[object Object],[object Object],[object Object],High Frequency DATA +

FSK Modulation 2 Combined PLL with mixer ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],I – Q Modulator

[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

[object Object],[object Object],[object Object],Proposed FSK Modulation ,[object Object],[object Object],[object Object],[object Object],[object Object],Tx0 Rx Tx1 2 MHz 2 MHz 8MHz 10 transmission channels 2.406 GHz 2.478 GHz 8 MHz Channel

[object Object],[object Object],[object Object],[object Object],[object Object],Proposed FSK Modulation ,[object Object],[object Object],[object Object]

Proposed FSK Modulation ,[object Object],[object Object],[object Object],[object Object],10pF 10pF 1 1 2 2 ,[object Object],[object Object],[object Object],Data : 1Mbits/s Transmission cycle ≤ 10 ms Tx0 Rx Tx1 2 MHz 2 MHz

VCO Design constraints Single VCO for lower cost ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],80 MHz BAND Required VCO input voltage (V) Output frequency (GHz) VCON VCO3 VCO2 VCO1 Single VCO ( 0 V to 2.5 V )

VCO Design ,[object Object],[object Object],[object Object],[object Object],[object Object],2.4 GHz Buffer 2.4 GHz VCO Delay #1 Delay #2

VCO - Performances -12dBm -98dBc/Hz 73ppm/°C 0.13-µm CMOS VDD = 2.5 V Vctrl = 1.25 V F vco = 2.487 GHz 1291ppm/°C VCO TEST CHIP VDD OFF CTRL OUTN OUTP C1 C2 C3 C4

VCO - Performances ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],90MHz/V 30MHz/V 55MHz/V

[object Object],[object Object],[object Object],[object Object],[object Object],PLL - Performances lock signal Vctrl ,[object Object],[object Object],[object Object],RX TX Tx0 Tx1 Rx Lock ,[object Object],[object Object],[object Object],[object Object],PLL + MOD CIRC PLL MOD CIRCUIT RX TX

Experimental results : Synthesizer ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Measured Synthesized Frequency 8MHz step Frequency synthesizer & FSK modulator 980µm 220µm BUF& FILTER Digital CAPACITOR (Loop Filter) VCO + CP MOD CIRC

0V  Sleep Mode 2.5V  Synthesizer Mode Channel 10 Channel 5 Locking Time from sleep mode Max Locking Time from sleep mode 100µs PLL Measurements : Lock Time ,[object Object],[object Object],[object Object],[object Object],Synthesizer Mode Isupply = 34-mA Sleep Mode Isupply = 300-µA Sleep Mode Sleep Mode Synthesizer RX lock 215µs

PLL Measurements : Lock Time ,[object Object],[object Object],[object Object],Lock time from channel 1 to 2  36 µs 36µs Worst case: ch1 to ch10 Channel 1 Channel 2 ,[object Object],[object Object]

Conclusion & Perspectives ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

IEEE_RFIC 2007

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