This presentation was made as a part of the VLSI II (senior) course at BUET.

1. 4 bit Comparator

2. Fariah Hayee
Lecturer,
Faculty of EEE,
BUET
Maruf Ahmed
Lecturer,
Faculty of EEE,
BUET

3. Ashik Amin Mohammad Wahiduzzaman Khan
Std ID #0806098 Std ID #0806144
Group 27

4. • Specification, Architectural Design and Functional
Verification
• Gate Level Schematic Design
• Transistor Level Design and Cell Layout
• Layout Placement and Routing
• Layout of Full Chip, DRC & LVS Log

5. Input Output
Ai Bi Di+1 Ci+1 Ci Di
x x 1 0 1 0
x x 0 1 0 1
0 0 0 0 0 0
0 1 0 0 0 1
1 0 0 0 1 0
1 1 0 0 0 0
X signifies “don’t care”

6. This type of cascade-able connection lessens the number of not gates reqd (2
for each block). Thus reducing the area of layout significantly.
COMPCELLA COMPCELLB
Inverted I/P True I/P
True O/P Inverted O/P

7. A B Cou
t
Dou
t
4 4 0 0
2 4 0 1
2 1 1 0
7 1 1 0

15. 50.8497-50.75=0.0997ns

16. 1.324E-6