1. VLSI DESIGN
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TRANSISTOR
1

2. The MOS Transistor
How old is the idea?
The first experimental observation of the surface
and its impact on the electric current was
disclosed in the paper “The action of light on
Selenium” by W. G. Adams and R. E. Day in the
Proceeding of Royal Society in 1876.
2

3. 1928
Field effect control device proposed by J. Lilienfield
3

4. About MOSFET
The surface controlled transistor has a very bad drift
problem. We have been fooling with this problem for a
long time and have no hope of an early solution. In fact,
I am not sure I have a strong hope of an eventual solution.
Gordon Moore
Fairchild Progress Report, February 15, 1962
Although the MOS devices are still at the research stage
because of fabrication problems and incomplete physical
understanding, their impact on microelectronics is
expected to be significant.
George Warfield, RCA
Electron Device Meeting, October, 1962
4

5. RCA Announcement of MOS transistor (February 11, 1963)
5

6. MOS Field-Effect Transistors (MOSFETs)

Compared to BJTs, MOSFETs can be made quite small (i.e., requiring
a small area on the silicon IC chip).
Their manufacturing process is relatively simple.

Their operation requires comparatively little power.


Ways to implement digital and analog functions utilizing MOSFETs
almost exclusively (i.e., with very few or no resistors).
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
Possible to pack large numbers of MOSFETs (>200 million!) on a
single IC chip to implement very sophisticated, very-Iarge-scale-
integrated (VLSI) circuits such as those for memory and micro-
processors.

Analog circuits such as amplifiers and filters are also implemented in
MOS Technology.
6

7. Physical structure of the enhancement-type NMOS transistor
7

8. 3D Perspective
8

9. L = 0.1 to 3 m cross-section.
Typically, W = 0.2 to 100 m, and the
thickness of the oxide layer (tox) is in
the range of 2 to 50 nm.
9

10. Creating a Channel for Current
Flow
N-channel MOSFET is formed in a p-type Gate voltage at which a sufficient
substrate: Channel created by inverting the number of mobile electrons
substrate surface from p type to n type. accumulate---- Threshold voltage Vt
Hence the induced channel is also called
an inversion layer.
10

11. Applying a Small VDS
..
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VDS causes a current lD to flow through source and drain.Conductance
of the channel is proportional to the excess gate voltage VGS above Vt
11

12. The iD–vDS characteristics of the MOSFET when the
voltage applied between drain and source, vDS, is kept
small. The device operates as a linear resistor whose
value is controlled by vGS.
12

13. Operation as VDS Is
Increased

Channel depth depends on this voltage

Channel is no longer of uniform depth;

Channel will take the tapered form shown:

Deepest at the source end and shallowest at the drain end.

As VDS is increased, the channel becomes more tapered
. and its resistance increases correspondingly
13

14. 14

15. Derivation of the iD-VDS Relationship .
15

16. Cox =
ox/tox =3.9 x 8.854 x 10-12 = 3.45
ox
= 3.9 o
x 10-11F/ m
dq = -Cox(W dx)[vGS – v(x) - V t ]
_ dv(x)
E(x) =
dx
Electrtric field E(x) causes the
electron charge dq to drift toward
the drain with a velocity dx/dt
dx dv(x)
= -n E(x) = n
dt dx
i = dq/dt = dq dx
dx dt
i = - nCox W [ VGS – v(x) – Vt ]
dv(x)
dx
16

17. iDdx = nCoxW [VGS- Vt- v(x)] dv(x)
Integrating both sides of this equation from x= 0 to x=L
and, correspondingly, for v(0) = 0 and v(L)=vDS
v DS
∫
L
∫ iDdx = nCoxW [VGS- Vt- v(x)]
0dv(x) 0
iD = (nCox)
W [ (VGS- Vt)VDS – 1/2 V2DS
L 
At the beginning of the saturation region substituting VDS = VGS - V t
,
1 W 
i = (µ C ) ( v )2
D n ox GS −V t
2 L
17

18. nCox is a constant determined by the process
technology used to fabricate the n-channel MOSFET. It is
known as the process transconductance parameter.
Denoted k'n and has the dimensions of A/V2
k'n =
nCox Aspect Ratio of the MOSFET
(Triode region)
(Saturation region)
Different notations: Kn, K'n n; C"ox Tox ; VT0,VTN,VTP;
18

19. Consider a process technology for which Lmin =0.4 m, tox = 8 nm,
n = 450 cm2/V- s, and Vt = 0.7 V.
(a) Find Cox and k'n .
(b) For a MOSFET with W /L = 8 m/0.8 m, calculate the values of VGS
and VDSmin needed to operate the transistor in the saturation region
with a dc current ID = 100 A.
(c) For the device in (b), find the value of VGS reguired to cause the
device to operate as a l000- resistor for very small VDS .
19

20. (b) For operation in the saturation region,
(c) For the MOSFET in the triode region with VDS very
small,
20

21. 21

22. The p-Channel

MOSFET
Fabricated on an n-type substrate

p + regions for the drain and source

Has holes as charge carriers

VGS and VDS are negative and the threshold voltage
Vt is negative
.
It is important to be familiar with the PMOS transistor
for two reasons:
1.PMOS devices are still available for discrete-circuit design
2. Both PMOS and NMOS transistors are utilized in complementary
. MOS or CMOS circuits, which is currently the dominant
MOS . . technology.
………
22

23. Cross-section of a CMOS integrated circuit
Note that the PMOS transistor is formed in a separate n-
type region, known as an n well. Another arrangement is
also possible in which an n-type body is used and the n
device is formed in a p well. Not shown are the connections
made to the p-type body and to the n well; the latter
functions as the body terminal for the p-channel device.
23

24. Operating the MOS Transistor in the Subthreshold
Region .
It has been found that for values of VGS smaller than but
close to Vt a small drain current flows.
In this subthreshold region of operation
Drain current is exponentially related to VGS.
There are special, but a growing number of applications that
make use of subthreshold operation.
24

25. Circuit symbol for the n-channel enhancement-type MOSFET
25

26. CURRENT-VOLTAGE CHARACTERIST!CS
n-channel enhancement-
mode MOSFET operates in
the triode region when
VGS is greater than Vt
and the drain voltage is
lower than the gate
voltage by at least Vt volts.
26

27. In the triode region
Near the origin
.
b st
Su
The boundary between the triode region and the saturation region is
characterized by
VDS = VGS- Vt (Boundary)
27

28. Gate-to-source overdrive Vov=VGS-
Vt
To operate the MOSFET in the saturation region,
VGS   V t (Induced channel)
Pinched off at the drain Raising G-to-D Volt. below V t ,
VDS
VGD < = V t (Pinched-off channel)
In terms of VDS : VDS = > VGS - Vt (Pinched-off channel)
28

29. The iD–vGS characteristic for an enhancement-
type NMOS transistor in saturation
29

30. Large-signal equivalent-circuit model of an n-channel
MOSFET operating in the saturation region
30

31. The relative levels of the terminal voltages of the
enhancement NMOS transistor for operation in the triode
region and in the saturation region.
31

32. Finite Output Resistance in
Saturation G
+5V
S D
0V 4.5V
0.1V
2.0V
3.0V
Vt =
0.5V
Ideal : Once the channel is pinched off at the drain
end, further increases in VDS have no effect on
the channel's shape.
32

33. 4.5V
G
+5V
S D
0V
6.0V
Vt =

Practice 0.5V
: Increasing VDS beyond VDSsat does affect the
channel. Channel pinch-off point is moved slightly away from the
drain, toward the source. The voltage across the channel remains
constant at VGS - Vt = VDSsat. Additional voltage applied to the
drain appears as a voltage drop across the narrow depletion
region between the end of the channel and the drain region. This
voltage accelerates the electrons that reach the drain end of the
channel. The channel length is in effect reduced, from L to L – ΔL.
Phenomenon known as channel-length modulation . iD
is inversely proportional to the channel length. iD increases with
VDS 33

34. 34

35. ΔL = '
vDS
' is a process-technology parameter with the dimensions of
m/V
35

36. Effect of VDS on iD in the saturation region
The MOSFET parameter VA depends on the process
technology and, for a given process, is proportional to
the channel length L.
36

37. Drain current without channel-length modulation
37

38. Large-signal equivalent circuit model of the n-channel
MOSFET
Large-signal equivalent circuit model of the n-channel
MOSFET in saturation, incorporating the output
resistance ro. The output resistance models the linear
dependence of iD on vDS
38

39. p-Channel MOSFET
39

40. Characteristics of the p-Channel MOSFET
(a) Circuit symbol for the p-channel enhancement-type MOSFET. (b) Modified
symbol with an arrowhead on the source lead. (c) Simplified circuit symbol for the
case where the source is connected to the body. (d) The MOSFET with voltages
applied and the directions of current flow indicated. Note that vGS and vDS are
negative and iD flows out of the drain terminal.
40

41. VGS < = Vt (Induced channel)
VSG  = |Vt| 0.25 to 0.5n
VDs > = VGS - Vt (Continuous channel)
Drain voltage must be higher than the gate voltage by at least |Vt|
To operate in saturation, VDS < = VGS - Vt (Pinched-off channel)
Drain voltage must be lower than (gate voltage + I Vtl)
Negative.
41

42. The relative levels of the terminal voltages of the
enhancement-type PMOS transistor for operation in
the triode region and in the saturation region.
42

43. The Role of the Substrate - The Body Effect
 No
Source terminal connected to the substrate (or body) terminal B ,
 Problem n
r
In ICs, the substrate is usually commonfo many MOS transistors.
to ns
itio ctio

Substrate connected to the most negativeo nd jun power supply
. in an NMOS circuit (most tof an in
f c nel a PMOS circuit).
upositive
e c to-c h
Resulting reverse-biasth te-
voltage between source and body
ain tra

int bs
. (VSB) wIll haveaan effect on device operation.
u
o m he s
T t
all
43

44. The reverse bias voltage will widen the depletion region .This
in turn reduces the channel depth. To return the channel to its
former state, VGS has to be increased. The effect of VSB on
the channel can be represented as a change in the threshold
voltage Vt . Increasing the reverse substrate bias voltage VSB
results in an increase in Vt .
Vto Threshold voltage for VSB = 0
f Physical parameter with (2 f ) typically 0.6 V
 Fabrication-process parameter
44

45. q Electron charge (1.6 x 10-19 C)
NA Doping concentration of the p-type substrate
s Permittivity of silicon (11.70 = 11.7 x 8.854 x 10-14 = 1.04 X 10-12
F/cm)
The parameter  has the dimension of  V and is typically 0.4 V½
p-Channel Devices
VSB by I VSBI
NA by ND ,
2f is typically 0.75 V
 is typically -0.5 V½ (Negative)
45

46. Review
Transistor Structure
P o lys ilico n G a te
S iO 2
I ns ula to r L D D
W
S o urce D ra in
G SB G
n+ n+
channel
p substrate S S
sub strate connected
n transistor to GND
P o lys ilico n G a te
S iO 2
I ns ula to r L D
W
S o urce D ra in
G SB G
p+ p+
channel
n substrate S sub strate connected
to VDD
p transistor
46

47. Review……
N Transistor Operation - Cutoff
•
Vgs << Vt : Transistor OFF
−
Majority carrier in channel (holes)
−
No current from source to drain
V S =0 V GS =0 V DS =0
source channel drain
Some Values for
Vtn:
Book (0.5µm) : 0.7V
AMI (1.5µm): 0.61V
47

48. Review……
N Transistor Operation - Subthreshold
 0 < Vgs < Vt : Depletion region
 Electric field repels majority carriers (holes)
 Depletion region forms - no carriers in channel
 No current flows (except for leakage current)
VS =0 0<VGS<VT VDS =0
source drain
de p le tionre gion
48

49. Review……
N Transistor Operation - ON
 Vgs > Vt , VDS=0: Transistor ON
 Electric field attracts minority carriers (electrons)
 Inversion region forms in channel
 Depletion region insulates channel from substrate
 Current can now flow from drain to source!
V S =0 V GS >V T V DS =0
source drain
inv e rsion lay e r - channe l
49

50. Review……
N Transistor Operation - Linear
 Vgs > Vt , VDS < VGS - Vt : Linear (Active) mode
 Combined electric fields shift channel and depletion region
 Current flow dependent on VGS, VDS
V S =0 V GS >V T V DS <V GS -V T
source drain
50

51. Review……
N Transistor Operation - Saturation
 Vgs > Vt , VDS >VGS -Vt : Saturated mode
 Channel “pinched off”
 Current still flows due to electron drift
 Current flow dependent on VGS
V S =0 V GS >V T V DS >V GS -V T
source drain
p inch-off p oint
51

52. Review……
P Transistor Operation
 Opposite of N-Transistor
 Vgs >> Vt : Transistor OFF
• Majority carrier in channel (electrons)
• No current from source to drain
 0 > Vgs > Vt : Depletion region
• Electric field repels majority carriers (electrons)
• Depletion region forms - no carriers in channel
• No current flows (except for leakage current)
 Vgs < Vt , VDS=0: Transistor ON
• Electric field attracts minority carriers (holes)
• Inversion region forms in channel
• Depletion layer insulates channel from substrate
• Current can now flow from source to drain!
52

53. Review……
P Transistor Modes of Operation
 Vgs < Vt , VDS > VGS - VT : Linear (Active) mode
 Combined electric fields shift channel and depletion region
 Current flow dependent on VGS, VDS
 Vgs < Vt , VDS < VGS - VT : Saturation mode
 Channel “pinched off”
 Current still flows due to hole drift
 Current flow dependent on VGS
Some Values for
Vtp:
Book (0.5µm) : -0.8V
AMI (1.5µm): -1.02V
53

54. I-V Characteristics of MOS Transistors
VD S
linear saturation
ID
V GS =5V V GS =-1.5V
V GS =2.5V V GS =-2.5V
V GS =1.5V V GS =-5V
ID
saturation linear
VD S
n transistor p transistor
54

55. Transistors as Switches

We can view MOS transistors as electrically controlled
switches

Voltage at gate controls path from source to drain
g=0 g=1
d d d
nMOS g OFF
ON
s s s
d d d
pMOS g OFF
ON
s s s
55

56. CMOS Inverter
A Y VDD
0
1
A Y
A Y
GND
56

57. CMOS Inverter
A Y VDD
0
1 0 OFF
A=1 Y=0
ON
A Y
GND
57

58. CMOS Inverter
A Y VDD
0 1
1 0 ON
A=0 Y=1
OFF
A Y
GND
58

59. CMOS Fabrication

CMOS transistors are fabricated on silicon wafer

Lithography process similar to printing press

On each step, different materials are deposited or
etched

Easiest to understand by viewing both top and cross-
section of wafer in a simplified manufacturing process
59

60. Inverter Cross-section

Typically use p-type substrate for nMOS transistors

Requires n-well for body of pMOS transistors
A
GND VDD
Y SiO2
n+ diffusion
p+ diffusion
n+ n+ p+ p+
polysilicon
n well
p substrate
metal1
nMOS transistor pMOS transistor
60

61. Well and Substrate Taps

Substrate must be tied to GND and n-well to VDD

Metal to lightly-doped semiconductor forms poor
connection called Shottky Diode

Use heavily doped well and substrate contacts / taps
A
GND VDD
Y
p+ n+ n+ p+ p+ n+
n well
p substrate
substrate tap well tap
61

62. Inverter Mask Set

Transistors and wires are defined by masks

Cross-section taken along dashed line
A
Y
GND VDD
nMOS transistor pMOS transistor
substrate tap well tap
62

63. Detailed Mask Views

Six masks n well

n-well
Polysilicon
Polysilicon


n+ diffusion n+ Diffusion

p+ diffusion p+ Diffusion

Contact Contact

Metal
Metal
0: Introduction Slide 63

64. Fabrication Steps

Start with blank wafer

Build inverter from the bottom up

First step will be to form the n-well

Cover wafer with protective layer of SiO2 (oxide)

Remove layer where n-well should be built

Implant or diffuse n dopants into exposed wafer

Strip off SiO2
p substrate
64

65. Oxidation

Grow SiO2 on top of Si wafer

900 – 1200 C with H2O or O2 in oxidation furnace
SiO2
p substrate
65

66. Photoresist

Spin on photoresist

Photoresist is a light-sensitive organic polymer

Softens where exposed to light
Photoresist
SiO2
p substrate
66

67. Lithography

Expose photoresist through n-well mask

Strip off exposed photoresist
Photoresist
SiO2
p substrate
67

68. Etch

Etch oxide with hydrofluoric acid (HF)

Seeps through skin and eats bone; nasty stuff!!!

Only attacks oxide where resist has been exposed
Photoresist
SiO2
p substrate
0: Introduction Slide 68

69. Strip Photoresist

Strip off remaining photoresist

Use mixture of acids called piranah etch

Necessary so resist doesn’t melt in next step
SiO2
p substrate
69

70. n-well

n-well is formed with diffusion or ion implantation

Diffusion

Place wafer in furnace with arsenic gas

Heat until As atoms diffuse into exposed Si

Ion Implantation

Blast wafer with beam of As ions

Ions blocked by SiO2, only enter exposed Si
SiO2
n well
70

71. Strip Oxide

Strip off the remaining oxide using HF

Back to bare wafer with n-well

Subsequent steps involve similar series of steps
n well
p substrate
71

72. Polysilicon

Deposit very thin layer of gate oxide

< 20 Å (6-7 atomic layers)

Chemical Vapor Deposition (CVD) of silicon layer

Place wafer in furnace with Silane gas (SiH4)

Forms many small crystals called polysilicon

Heavily doped to be good conductor
Polysilicon
Thin gate oxide
n well
p substrate

73. Polysilicon Patterning

Use same lithography process to pattern polysilicon
Polysilicon
Polysilicon
Thin gate oxide
n well
p substrate
73

74. Self-Aligned Process

Use oxide and masking to expose where n+ dopants
should be diffused or implanted

N-diffusion forms nMOS source, drain, and n-well
contact
n well
p substrate
74

75. N-diffusion

Pattern oxide and form n+ regions

Self-aligned process where gate blocks diffusion

Polysilicon is better than metal for self-aligned gates
because it doesn’t melt during later processing
n+ Diffusion
n well
p substrate
75

76. N-diffusion cont…

Historically dopants were diffused

Usually ion implantation today

But regions are still called diffusion
n+ n+ n+
n well
p substrate
76

77. N-diffusion cont.

Strip off oxide to complete patterning step
n+ n+ n+
n well
p substrate
77

78. P-Diffusion

Similar set of steps form p+ diffusion regions for pMOS
source and drain and substrate contact
p+ Diffusion
p+ n+ n+ p+ p+ n+
n well
p substrate
78

79. Contacts

Now we need to wire together the devices

Cover chip with thick field oxide

Etch oxide where contact cuts are needed
Contact
Thick field oxide
p+ n+ n+ p+ p+ n+
n well
p substrate
79

80. Metalization

Sputter on aluminum over whole wafer

Pattern to remove excess metal, leaving wires
Metal
Metal
Thick field oxide
p+ n+ n+ p+ p+ n+
n well
p substrate
80

81. Layout

Chips are specified with set of masks

Minimum dimensions of masks determine transistor size
(and hence speed, cost, and power)

Feature size f = distance between source and drain

Set by minimum width of polysilicon

Feature size improves 30% every 3 years or so

Normalize for feature size when describing design rules

Express rules in terms of  = f/2

E.g.  = 0.3 m in 0.6 m process
81

82. Simplified Design Rules

Conservative rules to get you started
82

83. Inverter Layout

Transistor dimensions specified as Width / Length

Minimum size is 4 / 2, sometimes called 1 unit

In f = 0.6 m process, this is 1.2 m wide, 0.6 mm
long
83

84. Summary

MOS Transistors are stack of gate, oxide, silicon

Can be viewed as electrically controlled switches

Build logic gates out of switches

Draw masks to specify layout of transistors

Now you know everything necessary to start designing
schematics and layout for a simple chip!
84

85. LOCOS Fabrication Process
85

86. LOCOS Defined
LOCOS = LOCal Oxidation of Silicon
Defines a set of fabrication technologies where
the wafer is masked to cover all active regions
thick field oxide (FOX) is grown in all non-active regions
Used for electrical isolation of CMOS devices
Relatively simple to understand so often used to
introduce/describe CMOS fabrication flows
Not commonly used in modern fabrication
other techniques, such as Shallow Trench Isolation (STI) are
currently more common than LOCOS
86

87. LOCOS –step 1
Form N-Well regions NWELL mask
•
Grow oxide
•
Deposit photoresist
oxide photoresis
t
p-type
substrate
Cross section view
NWELL mask
Layout view
87

88. LOCOS –step 1
Form N-Well regions NWELL mask
•
Grow oxide
•
Deposit photoresist
•
Pattern photoresist oxide photoresis
−
NWELL Mask t
p-type
−
expose only n-well substrate
areas
Cross section view
NWELL mask
Layout view
88

89. LOCOS –step 1
Form N-Well regions
•
Grow oxide
•
Deposit photoresist
•
Pattern photoresist oxide
•
NWELL Mask
p-type
•
expose only n-well substrate
areas Cross section view
•
Etch oxide
•
Remove photresist
Layout view
89

90. LOCOS –step 1
Form N-Well regions
•
Grow oxide
•
Deposit photoresist
n-well
•
Pattern photoresist
−
NWELL Mask
p-type
−
expose only n-well substrate
areas
Cross section view
•
Etch oxide
•
Remove photoresist
•
Diffuse n-type dopants
through oxide mask
layer
Layout view
90

91. LOCOS –step 2
Form Active Regions ACTIVE
•
Deposit SiN over wafer mask
•
Deposit photoresist over
SiN layer n-well
SiN photoresis
t
p-type
substrate
ACTIVE
mask
91

92. LOCOS –step 2
Form Active Regions ACTIVE
•
Deposit SiN over wafer mask
•
Deposit photoresist over
SiN layer n-well
SiN photoresis
•
Pattern photoresist t
−
*ACTIVE MASK p-type
substrate
ACTIVE
mask
92

93. LOCOS –step 2
Form Active Regions
•
Deposit SiN over wafer
•
Deposit photoresist over
SiN layer n-well
SiN photoresis
•
Pattern photoresist t
−
*ACTIVE MASK p-type
substrate
•
Etch SiN in exposed
areas
−
leaves SiN mask which
blocks oxide growth
ACTIVE
mask
93

94. LOCOS –step 2
Form Active Regions
•
Deposit SiN over wafer
•
Deposit photoresist over
SiN layer n-well
•
Pattern photoresist FOX
−
*ACTIVE MASK p-type
substrate
•
Etch SiN in exposed
areas
−
leaves SiN mask which
blocks oxide growth
•
Remove photoresist
•
Grow Field Oxide (FOX)
−
thermal oxidation ACTIVE
mask
94

95. LOCOS –step 2
Form Active Regions
•
Deposit SiN over wafer
•
Deposit photoresist over
SiN layer n-well
•
Pattern photoresist FOX
−
*ACTIVE MASK p-type
substrate
•
Etch SiN in exposed
areas
−
leaves SiN mask which
blocks oxide growth
•
Remove photoresist
•
Grow Field Oxide (FOX)
−
thermal oxidation ACTIVE
mask
•
Remove SiN
95

96. LOCOS –step 3
Form Gate (Poly layer)
•
Grow thin Gate Oxide
−
over entire wafer
−
negligible effect on gate
FOX regions oxide
96

97. LOCOS –step 3
Form Gate (Poly layer) POLY mask
•
Grow thin Gate Oxide
−
over entire wafer
−
negligible effect on polysilicon
gate
FOX regions oxide
•
Deposit Polysilicon
•
Deposit Photoresist
POLY mask
97

98. LOCOS –step 3
Form Gate (Poly layer) POLY mask
•
Grow thin Gate Oxide
−
over entire wafer
−
negligible effect on gate
FOX regions oxide
•
Deposit Polysilicon
•
Deposit Photoresist
•
Pattern Photoresist
−
*POLY MASK
•
Etch Poly in exposed
areas
•
Etch/remove Oxide
−
gate protected by poly
POLY mask
98

99. LOCOS –step 3
Form Gate (Poly layer)
•
Grow thin Gate Oxide
−
over entire wafer
−
negligible effect on gate
FOX regions oxide
•
Deposit Polysilicon
•
Deposit Photoresist
•
Pattern Photoresist
−
*POLY MASK
•
Etch Poly in exposed
areas
•
Etch/remove Oxide
−
gate protected by poly
99

100. LOCOS –step 4
Form pmos S/D PSELECT
mask
•
Cover with photoresist
PSELECT
mask
100

101. LOCOS –step 4
Form pmos S/D PSELECT
mask
•
Cover with photoresist
•
Pattern photoresist
−
*PSELECT MASK
POLY mask
101

102. LOCOS –step 4
Form pmos S/D
•
Cover with photoresist
•
Pattern photoresist
−
*PSELECT MASK
•
Implant p-type dopants p+ dopant p+ dopant
•
Remove photoresist
POLY mask
102

103. LOCOS –step 5
Form nmos S/D NSELECT
mask
•
Cover with photoresist
p+ p+ p+
n
POLY mask
103

104. LOCOS –step 5
Form nmos S/D NSELECT
mask
•
Cover with photoresist
•
Pattern photoresist p+ p+ p+
−
*NSELECT MASK n
POLY mask
104

105. LOCOS –step 5
Form nmos S/D
•
Cover with photoresist
•
Pattern photoresist n+ p+ p+ n+ n+ p+
−
*NSELECT MASK n
•
Implant n-type dopants n+ dopant n+ dopant
•
Remove photoresist
POLY mask
105

106. LOCOS –step 6
CONTACT
Form Contacts mask
•
Deposit oxide
•
Deposit photoresist n+ p+ p+ n+ n+ p+
n
CONTACT
mask
106

107. LOCOS –step 6
CONTACT
Form Contacts mask
•
Deposit oxide
•
Deposit photoresist n+ p+ p+ n+ n+ p+
•
Pattern photoresist n
−
*CONTACT Mask
−
One mask for both
active and poly
contact shown
CONTACT
mask
107

108. LOCOS –step 6
Form Contacts
•
Deposit oxide
•
Deposit photoresist n+ p+ p+ n+ n+ p+
•
Pattern photoresist n
−
*CONTACT Mask
−
One mask for both
active and poly
contact shown
•
Etch oxide
108

109. LOCOS –step 6
Form Contacts
•
Deposit oxide
•
Deposit photoresist n+ p+ p+ n+ n+ p+
•
Pattern photoresist n
−
*CONTACT Mask
−
One mask for both
active and poly
contact shown
•
Etch oxide
•
Remove photoresist
•
Deposit metal1
−
immediately after
opening contacts so
no native oxide grows
in contacts
•
Planerize
−
make top level 109

110. LOCOS –step 7
METAL1 mask
Form Metal 1 Traces
•
Deposit photoresist
n+ n+ n+
p+ p+ p+
n
METAL1 mask
110

111. LOCOS –step 7
METAL1 mask
Form Metal 1 Traces
•
Deposit photoresist
•
Pattern photoresist n+ p+ p+ n+ n+ p+
−
*METAL1 Mask n
METAL1 mask
111

112. LOCOS –step 7
Form Metal 1 Traces
•
Deposit photoresist
•
Pattern photoresist n+ p+ p+ n+ n+ p+
−
*METAL1 Mask n
•
Etch metal
metal over poly outside of cross
section
112

113. LOCOS –step 7
Form Metal 1 Traces
•
Deposit photoresist
•
Pattern photoresist n+ p+ p+ n+ n+ p+
−
*METAL1 Mask n
•
Etch metal
•
Remove photoresist
113

114. LOCOS –step 8
VIA mask
Form Vias to Metal1
•
Deposit oxide
•
Planerize oxide n+ p+ p+ n+ n+ p+
•
Deposit photoresist n
VIA mask
114

115. LOCOS –step 8
VIA mask
Form Vias to Metal1
•
Deposit oxide
•
Planerize n+ p+ p+ n+ n+ p+
•
Deposit photoresist n
•
Pattern photoresist
−
*VIA Mask
VIA mask
115

116. LOCOS –step 8
Form Vias to Metal1
•
Deposit oxide
•
Planerize n+ p+ p+ n+ n+ p+
•
Deposit photoresist n
•
Pattern photoresist
−
*VIA Mask
•
Etch oxide
•
Remove photoresist
116

117. LOCOS –step 8
Form Vias to Metal1
•
Deposit oxide
•
Planerize n+ p+ p+ n+ n+ p+
•
Deposit photoresist n
•
Pattern photoresist
−
*VIA Mask
•
Etch oxide
•
Remove photoresist
•
Deposit Metal2
117

118. LOCOS –step 9
METAL2 mask
Form Metal2 Traces
•
Deposit photoresist
n+ n+ n+
p+ p+ p+
n
METAL2 mask
118

119. LOCOS –step 9
METAL2 mask
Form Metal2 Traces
•
Deposit photoresist
•
Pattern photoresist n+ p+ p+ n+ n+ p+
−
*METAL2 Mask n
METAL2 mask
119

120. LOCOS –step 9
Form Metal2 Traces
•
Deposit photoresist
•
Pattern photoresist n+ p+ p+ n+ n+ p+
•
*METAL2 Mask n
•
Etch metal
Page 120

121. Latch-up
•
CMOS ICs have parasitic silicon-controlled
rectifiers (SCRs).
•
When powered up, SCRs can turn on, creating
low-resistance path from power to ground.
Current can destroy chip.
•
Early CMOS problem. Can be solved with proper
circuit/layout structures.
121

122. Parasitic SCR
Circuit I-V behavior
122

123. Parasitic Transistors
•
Parasitic bipolar transistors form at N/P junctions
•
Latchup - when parasitic transistors turn on
•
Preventing latchup:
−
Add substrate contacts (“tub ties”) to reduce Rs, Rw
OR
−
Use Silicon-on-Insulator
G nd V dd
n+ n+ p+ p+
Rw
n well
p substrate Rs
123

124. Controlling Latchup - Substrate Contacts
•
Purpose: connect well/substrate to power supply
•
Alternative term: tub tie
•
Recommendations (source: Weste & Eshraghian)
−
Conservative: 1 substrate contact for every supply
connection
−
Less conservative: 1 substrate contact for every 5-10
transistors
−
High-current circuits: use guard rings
G nd V dd
Substrate p+ n+ n+ p+ p+ n+ Substrate
Contact Rw Contact
n well
p substrate Rs
124

125. Solution to latch-up
Use tub ties to connect tub to power rail. Use
enough to create low-voltage connection.
125

126. Scaling of CMOS
Advances in device manufacturing technology allow for a
steady reduction of the minimum feature size such as the
minimum transistor channel length realizable on a chip.
Evolution of (average) minimum channel length of MOS transistors over time.
126

127. Scaling of CMOS….
Scaling refers to the systematic reduction of transistor
dimensions from one generation to the next.
It reduces the parasitic capacitances and also the
carrier transit times in the devices.
Improves the circuit speed.
It narrows the performance gap between CMOS and
logic gates based on bipolar transistors.
Reduction of the transistor dimensions improves the
packing density of CMOS.
127

128. Full Scaling of CMOS
“Full Scaling,” involves scaling all dimensions and voltages by
the same factor, 1/s, where s is greater than one.
Scaling factor of 1/2 is used (s = 2 ), then the packing
density
in transistors per square centimeter will be doubled.
The goal is to keep the electrical field patterns in the scaled
device identical to those in the original device.
Keeping the electrical fields constant ensures the physical
integrity of the device and avoids breakdown or other
secondary effects.
This scaling leads to greater device density (Area), higher
performance (Intrinsic Delay), and reduced power consumption (P).
128

129. Full Scaling of CMOS
129

130. Fixed-Voltage Scaling
In reality, full scaling is not a feasible option:
1. To keep new devices compatible with existing components,
voltages cannot be scaled arbitrarily.
2. Having to provide for multiple supply voltages adds
considerably to the cost of a system.
As a result, voltages have not been scaled down along
with feature sizes, and designers adhere to well-defined
standards for supply voltages and signal levels.
130

131. Scaling scenarios for short-channel devices
131

132. CMOS INVERTER
132

133. CMOS Inverter
N VD
Wel
D
VDD l
PM 2
OS λ
Conta
PMOS cts
In Out
I O
Metal 1
u
n
t
Polysilic
NMOS on
NM
OS
G
N
D

134. CMOS INVERTER
A simplified model of the Simplified model of the
A CMOS inverter inverter for a high input level. inverter for a low input
uses one NMOS and The output is forced to zero level. The output is pulled
one PMOS transistor. through the on-resistance of to VDD through the on-
the NMOS transistor. resistance of the PMOS
transistor.
134

135. CMOS Inverter - DC Response
•
DC Response: Vout vs. Vin for a gate
•
Ex: Inverter
−
When Vin = 0 -> Vout = VDD
−
When Vin = VDD -> Vout = 0
VDD
−
In between, Vout depends on
transistor size and current Idsp
Vin Vout
−
By KCL, must settle such that Idsn
Idsn = |Idsp|
−
We could solve equations
−
But graphical solution gives more insight
135

136. Transistor Operation
•
Current depends on region of transistor behavior
•
For what Vin and Vout are NMOS and PMOS in
−
Cutoff?
−
Linear? linear saturation
ID
−
Saturation? V GS =5V
V GS =2.5V
V GS =1.5V
VD S
n transistor
136

137. NMOS Operation
Cutoff Linear Saturated
Vgsn < Vtn Vgsn > Vtn Vgsn > Vtn
Vin < Vtn Vin > Vtn Vin > Vtn
Vdsn < Vgsn – Vdsn > Vgsn –
Vtn Vtn
Vout < Vin - Vtn Vout > Vin - Vtn
VDD
Vgsn = Vin
Idsp
Vdsn = Vout Vin Vout
Idsn
137

138. PMOS Operation
Cutoff Linear Saturated
Vgsp < Vtp Vgsp < Vtp Vgsp < Vtp
Vin < VDD + Vtp Vin < VDD + Vtp Vin < VDD + Vtp
Vdsp > Vgsp – Vdsp < Vgsp –
Vtp Vtp
Vout > Vin – Vtp Vout < Vin - Vtp
VDD
Vgsp = Vin - VDD Vtp < 0
Idsp
Vdsp = Vout - VDD Vin Vout
Idsn
138

139. I-V Characteristics
•
Make PMOS is wider than NMOS such that Κn = Κp
139

140. Current vs. Vout, Vin
Vin0 Vin5
4
Vin1 Vin4
Idsn, |Idsp| 3
Vin2 Vin3
2
Vin3 Vin2
1
Vin4 Vin1
0
VDD
Vout
140

141. Load Line Analysis
•
For a given Vin:
−
Plot Idsn, Idsp vs. Vout
−
Vout must be where |currents| are equal in magnitude
Vin0 Vin5
4
Vin1 Vin4
3
VDD
Idsn, |Idsp|
Idsp
Vin Vout
Vin2 Vin3
2 Idsn
Vin3 Vin2
1
Vin4 Vin1
0
VDD
Vout
141

142. Load Line Analysis
Vin = 0.8VDD
0
0.2VDD
0.6VDD
0.4VDD
VDD
142

143. CMOS Inverter Load Characteristics
ID n
Vin = 0 Vin = 2.5
PMOS Vin = 0.5 Vin = 2 NMOS
Vin = 1 Vin = 1.5
Vin = 1.5 Vin = 1
Vin = 1.5 Vin = 1
Vin = 2 Vin = 0.5
Vin = 2.5 Vin = 0
Vout

144. DC Transfer Curve
•
Transcribe points onto Vin vs. Vout plot
Vin0 Vin1
VDD Vin2
Vin0 Vin5
A B
Vin1 Vin4 Vout
C
Vin2 Vin3
Vin3
Vin3 Vin2 D Vin4 Vin5
Vin4 Vin1 E
0 Vtn VDD/2 VDD+Vtp
VDD VDD
Vout
Vin
144

145. Operating Regions
•
Revisit transistor operating regions
Region NMOS PMOS

Click to edit the
A Cutoff Linear outline text
B Saturation Linear format
V DD
C Saturation Saturation A B
D Linear Saturation

Second
Vout
E Linear Cutoff Outline Level
C
− Third Outline
D
0 Level
Vtn
E
V
VDD/2 VDD+Vtp
DD
V

Fourth in
Outline
145
Level

146. CMOS voltage transfer characteristics
KR =
Kn/Kp
Symmetrical design (Kp = Kn)
If Kp  Kn, then the transition shifts away from VDD/2.
146

147. CMOS voltage transfer characteristics
147

148. CMOS voltage transfer characteristics
Calculate the critical points of the resulting
voltage transfer curve. For this we need the i- v
relationships of QN and QP .
For QN
For QP
148

149. CMOS voltage transfer characteristics…..

CMOS inverter is usually designed to have Vtn = lVtpl = Vt and
kn’(WIL)n = k’p(WIL)p
 p is 0.3 to 0.5 times n. Kn and Kp should be
equal.

The width of the p-channel device is made two to three times that
of the n-channel device.

The two devices are designed to have equal lengths, with widths
related by (Wp / Wn) = (p / n)

This will result in k’n(W / L)n = k’p(W / L)p (KN = KP) and the
inverter will have a symmetric transfer characteristic and equal
current-driving capability in both directions (pull-up and pull-down).
149

150. CMOS voltage transfer characteristics…..
VIL — Maximum permitted logic-0 or "low" level at the input.
VIH — Minimum permitted logic-1or "high" level at the input.
Above are formally defined as the two
points on the transfer curve at which
the incremental gain is unity. (i.e. the
slope is =1 V/ V).
150

151. CMOS voltage transfer characteristics…..
To determine VIH : QN is in the triode region QP is in salutation (KN =
KP)
Equating iDN and iDP and assume matched devices (KN =
KP)
Differentiating both sides relative to vI
Substitute vI = VIH and dvO/dvI = -1 to obtain
151

152. CMOS voltage transfer characteristics…..
VIL can be determined in a manner similar to that used to find VIH.
Alternatively, we can use the symmetry relationship.
Hence we get,
152

153. CMOS voltage transfer characteristics…..
The noise margins can now be determined as follows:
The symmetry of the voltage transfer
characteristic results in equal noise
margins. If QN and QP are not matched,
the voltage transfer characteristic will
no longer be symmetric.
153

154. CMOS Inverter — Dynamic Operation
Speed of operation of a digital system (e.g., a computer)
is determined by the propagation delay of the logic
gates used to construct the system.
I nverteris the basic logic gate of any digital IC
technology, the propagation delay of the inverter is a
fundamental parameter in characterizing the technology.
Switching operation of the CMOS inverter should be
analyzed to determine its propagation delay.
154

155. CMOS Inverter — Dynamic Operation……
Inverter is driven
by an ideal pulse
Input – Output waveform
C = Internal capacitances of the MOSFETs QN and QP, +
Capacitance of the interconnect wire between the inverter output node
and the input(s) of the other logic gates the inverter is driving and the
total input capacitance of these load (or fan-out) gates.
155

156. CMOS Inverter — Dynamic Operation……
QN Saturation — C discharges —
Current of QN remains constant
until Vo = VDD - Vt (point F).
This portion of the
discharge interval
tPHL1
Equivalent circuit during
the capacitor discharge.
Trajectory of the operating point as the input
goes high and C discharges through QN.
156

157. CMOS Inverter — Dynamic Operation……
HL indicates the high-to-
low output transition
Beyond point P, transistor QN operates in the triode region
Subst. for iDN and rearrange,
157

158. CMOS Inverter — Dynamic Operation……
To find the component of the delay time tPHL during which Vo
decreases from (VDD - Vt) to the 50% point, vo = VDDI2, we
integrate both sides of above equation. Denoting this component of
delay time tPHL2 we find that:
Adding tPHL1 and tPHL2 we get
For Vt  0.2VDD,
Similarly analyze of the turn-off process.
Expression for tPLH identical to this.(k’n( W
/ L)n replaced with k’p(W / L)p. Propagation
delay tp = Average of tPHL and tPLH.
158

159. Stick Diagram

Stick Diagram is a simple sketch of the layout that can easily be
changed/modified/redrawn with minimal effort.

Shows only active, poly, metal, contact, and n-well layers

Each layer is color coded (typically use colored pencils or pens)

Active, poly, metal traces are drawn with lines (not rectangles)

Contacts are marked with an X —Typically only need to show contacts
between metal and active.
 N-well are indicated by a rectangle around PMOS transistors — Typically
using dashed lines
159

160. Sticks Diagram…… VDD
PMOS
In Out
VD 3 NMOS
D
I O
n ut
•
Dimensionless layout entities
•
Only topology is important
•
Final layout generated by
1 “compaction” program
GN
D
Stick diagram of
inverter 160

161. Stick Diagram NAND
Circuit Layer Design
Stick Diagram
Metal supply rails – blue
n and p Active – green
Poly gates – red
Metal connections – supply, outputs
Contacts – black X
161

162. Stick Diagram NOR
162