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3DD 1e 31 Luglio Apertura

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Marco Santambrogio
Marco Santambrogio
Economy & FinanceTechnology
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D ynamic R econfigurability in E mbedded S ystem D esign - Prima Edizione della 3-Giorni DRESD - 31/07 - 1-2/08, 2006 Hotel Villa Gina Goglio
Outline ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Outline ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
DRESD Philosophy ,[object Object],[object Object],[object Object],[object Object],[object Object]
DRESD Team ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Where we are working: Reconfiguration f i x Total Embedded
DRESD in the WORLD ,[object Object],[object Object],[object Object],[object Object],[object Object]
Progetti di RLA 03/04 Campione di 30 Studenti
Progetti di RLA 04/05 Campione di 75 Studenti
Progetti di RLA 05/06 Campione di 33 Studenti
Some results: Conferences ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Some results: Partnerships ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
DRESD and HNI ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
DRESD and UIC ,[object Object],[object Object]
[object Object],[object Object],DRESD and Northwestern
Outline ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Caronte ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
DRESD: The Caronte Flow
HW-SSP Sequencing
DRESD: The Caronte Architecture
DRESD and Linux ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Software Architecture ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
The ICAP Kernel Module ,[object Object],[object Object],[object Object],[object Object]
The IP-Core Manager ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
The IP-Core Manager: Hierarchy ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Caronte: Standalone Vs Linux Table 2 - Original Caronte vs. Caronte with Linux on the XC2VP7 FPGA 4 50 2 50 2 DCM s 44 72 32 72 32 Block RAM 396 42 168 27 107 Bonded IOBs 4928 45 2262 36 1818 Occupied Slices 9856 22 2173 17 1727 4-input LUTs 9856 24 2369 18 1843 Slice Flip Flops Perc .(%) Elem. Perc .(%) Elem. Total Available Caronte Linux Orignal Caronte Resource
Distributed scenarios
Outline ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
SyCERS ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
TLM e SystemC ,[object Object],[object Object],[object Object],[object Object],[object Object],write() read() module A pA->write(v) module B v=pB->read() channel pA pB sc_interface sc_port
The SyCERS methodology Specification Model Component Assembly Model Bus Functional Model ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
A reconfigurable component using SystemC ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],*g() Reconfigurable Component (sc_module) Configuration (function pointer) mutex
Reconfigurable component behaviour
Caronte Models Control Code (SystemC) Compiler GCC Configurations BlackBox (SystemC) Configuration Control Process Scheduler and Controller Memory Model Cross Compiler GCC Control Code (C/C++) Modello Memoria BlackBoxes Model CoreConnect PowerPC ISS Open SystemC PowerPC core models
Theoretical Aspects ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Reconfigurable Hardware: why?
Reconfigurable Hardware: why?
Partitioning problem
The Acheronte Flow ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Acheronte: il flusso per la creazione di YaRA .:: Obiettivi .:: Caronte .:: YaRA > Parte fissa > Moduli riconf. > Infrastruttura di comunicaz. .:: Acheronte .:: Test .:: Conclusioni .:: Sviluppi futuri .::Domande
YaRA ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
YaRA: the embedded 1D approach
YaRA: parte fissa
YaRA: FPGA Layers Clock Modulo Riconf. Macro HW PPC-405 BRAM e Moltiplicatori 18x18 Parte Fissa .:: Obiettivi .:: Caronte .:: YaRA > Parte fissa > Moduli riconf. > Infrastruttura di comunicaz. .:: Acheronte .:: Test .:: Conclusioni .:: Sviluppi futuri .::Domande CLB x CLB y Layer
Caronte Vs YaRA Utilizzo tecnologie standard Intercambiabilità dei moduli Continuazione della comunicazione durante la riconfigurazione N° di moduli Riconfigurabilità Interna Riconfigurabilità Parziale e Dinamica Anche diverse decine  2 YaRA Caronte
How to extend YaRA and Acheronte ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
D-ICAP: DRESD - ICAP ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
D-WBM: DRESD - Wishbone BUSMacro ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
BiRF: Bitstream Relocation Filter ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],IP-Core Generator Tool
EDK System Creator ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
RCPCG: Reconfigurable Core Placer Constraints Generator ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
ADG: Automatic Driver Genarator ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
BAnMaT: Bitstream Analizer Manipulator Tool ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
RecOnDemand ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

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3DD 1e 31 Luglio Apertura

  • 1. D ynamic R econfigurability in E mbedded S ystem D esign - Prima Edizione della 3-Giorni DRESD - 31/07 - 1-2/08, 2006 Hotel Villa Gina Goglio
  • 2.
  • 3.
  • 4.
  • 5.
  • 6. Where we are working: Reconfiguration f i x Total Embedded
  • 7.
  • 8. Progetti di RLA 03/04 Campione di 30 Studenti
  • 9. Progetti di RLA 04/05 Campione di 75 Studenti
  • 10. Progetti di RLA 05/06 Campione di 33 Studenti
  • 11.
  • 12.
  • 13.
  • 14.
  • 15.
  • 16.
  • 17.
  • 20. DRESD: The Caronte Architecture
  • 21.
  • 22.
  • 23.
  • 24.
  • 25.
  • 26. Caronte: Standalone Vs Linux Table 2 - Original Caronte vs. Caronte with Linux on the XC2VP7 FPGA 4 50 2 50 2 DCM s 44 72 32 72 32 Block RAM 396 42 168 27 107 Bonded IOBs 4928 45 2262 36 1818 Occupied Slices 9856 22 2173 17 1727 4-input LUTs 9856 24 2369 18 1843 Slice Flip Flops Perc .(%) Elem. Perc .(%) Elem. Total Available Caronte Linux Orignal Caronte Resource
  • 28.
  • 29.
  • 30.
  • 31.
  • 32.
  • 34. Caronte Models Control Code (SystemC) Compiler GCC Configurations BlackBox (SystemC) Configuration Control Process Scheduler and Controller Memory Model Cross Compiler GCC Control Code (C/C++) Modello Memoria BlackBoxes Model CoreConnect PowerPC ISS Open SystemC PowerPC core models
  • 35.
  • 39.
  • 40. Acheronte: il flusso per la creazione di YaRA .:: Obiettivi .:: Caronte .:: YaRA > Parte fissa > Moduli riconf. > Infrastruttura di comunicaz. .:: Acheronte .:: Test .:: Conclusioni .:: Sviluppi futuri .::Domande
  • 41.
  • 42. YaRA: the embedded 1D approach
  • 44. YaRA: FPGA Layers Clock Modulo Riconf. Macro HW PPC-405 BRAM e Moltiplicatori 18x18 Parte Fissa .:: Obiettivi .:: Caronte .:: YaRA > Parte fissa > Moduli riconf. > Infrastruttura di comunicaz. .:: Acheronte .:: Test .:: Conclusioni .:: Sviluppi futuri .::Domande CLB x CLB y Layer
  • 45. Caronte Vs YaRA Utilizzo tecnologie standard Intercambiabilità dei moduli Continuazione della comunicazione durante la riconfigurazione N° di moduli Riconfigurabilità Interna Riconfigurabilità Parziale e Dinamica Anche diverse decine  2 YaRA Caronte
  • 46.
  • 47.
  • 48.
  • 49.
  • 50.
  • 51.
  • 52.
  • 53.
  • 54.
  • 55.