Test Tutorial

ATD Module Training

Provides answers to a
score of important
questions about the ATD
module!

Caveat: Your ATD module
may differ in detail from the
one described.
Check your spec.!

DR Adams 11 March 2003
General Business Information, ATD_Training.ppt, Rev A.
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All
other product or service names are the property of their respective owners. © Motorola, Inc. 2003.

Overview of ATD Design Features

• MCU applications normally include the monitoring of analog input voltages
from various sensors. These signals typically must be read with a high
degree of precision. 10 bits of resolution is equivalent to 0.1% sensitivity.
• Noise sensitivity is thus much more critical on analog signals than it is on the
digital circuitry. Test hardware must provide separate analog ground planes
to isolate analog signals from digital noise. ATD converters should have
differential inputs in order to reject common mode signals and thus reject
noise.
• The differential signal is impressed across the pos. and neg. inputs.
• Common mode signal element is from the negative input relative to ground.

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-
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General Business Information

What’s the most common Analog to Digital Conversion
Technique?

• Successive approximation is the most common technique employed by the ADC
module within an MCU. It resolves one bit at a time, from MSB down to LSB. (It’s
the same as a implementing a binary search method.)
• A diagram of a successive approximation converter is shown:

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Successive
Approximation
Register
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How is the Analog to Digital Converter Implemented on MCUs?

• Start of Conversion (SOC) signal from the MCU initiates the A to D conversion.
• End of Conversion (EOC) signal from the ADC indicates that a digital result is
available to the MCU.
• ATD Converter Modules usually provide 8 or more multiplexed input channels, a
command register, and a result register configured as shown:

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SAR VDDA
VSSA
-
Commands Results
Registers

What are the different A to D Operating Modes?

• The conversion mode determines:
1. Which analog input channels to convert
2. How many conversions to perform in sequence
3. Whether to perform continuous conversion or not
4. Type of conversion event trigger
5. Result register assignment
6. Sample time

• Conversion mode is defined by control bits. For example:
1. ETRIGE enables the external trigger to start conversion sequences
2. ETRIGLE selects either edge or level active trigger
3. ETRIGEP selects trigger polarity
4. MULT selects either single or multiple channels for input – Tested in atd_mulchan_scan
5. SCAN enables continuous conversion Reference Voltages
6. SC selects special conversion mode
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SAR
Analog Power
-

What are Special Conversion Modes and What is Their
Purpose?

• Special conversion modes are designed to be used for self test of the A to D
converter.
• Some of the special conversions that are possible:
1. Convert VRL or VRH
2. Convert (VRL + VRH)/2
3. Can you name another special conversion?
4. The atd_int_conv_vrh_vrl pattern is one of the special conversion mode test patterns.

Reference Voltages
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-
SAR
Analog Power
-

How do I select which analog input channels to convert?

• The input channels are selected by the use of the control bits CD/CC/CB/CA
• (The mulchan_scan pattern exercises these controls.)

• What determines the number of conversions to be performed?
• The register control bits S8C/S4C/S1C define the number of conversions to be
performed in sequence. (Covered by atd_singchan_scan pattern)

• Which registers control the ATD sample time?
• SMP0/SMP1 define the length of the sample time
• (This function is tested by the atd_sample pattern)

• Refer to your spec. for the control register memory maps.


Are there any default ATD mode selections?

• The default sequence length is typically 4 – Check your specifications
• The default prescalar value is typically 3 – This provides an ATD clock rate of
one sixth the bus clock rate.

• What else should I know about control registers and conversion
modes?
• Writing to control register 5 initiates conversion sequences.
• In continuous conversion mode, conversions continue until a subsequent non-
continuous conversion sequence is performed, the ATD is reset or powered
down, or the bus Wait or Stop line is activated.

Reference Voltages
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SAR
Analog Power
-

How is the MCU notified that conversion is complete and result
data is available in the result registers?

1. If the interrupt enable bit is set, the MCU can be interrupted when the
conversion is complete. (atd_interrupt and atd_fifo patterns use this method)
2. Otherwise, the ATD conversion complete flags can be polled by the MCU to
determine when the results registers are ready.
• (This method is employed by the atd_singchan_s8c_scan pattern)
• The Conversion Complete Flag (CCF) bit for each result register is set when the
result data is available.

Reference Voltages
+
-
SAR
Analog Power
-

What does the ATD module look like from a programming
perspective?

1. An ATD module has a memory mapped control register block which stores the
ATD configuration, status, test, and result data.
2. A typical ATD module uses 24 words or 48 bytes of address space.
• 4 bytes are reserved for module configuration
• 2 bytes reserved for special test mode
• 3 bytes reserved for status information
• 24 bytes reserved for ATD result registers (for a 12 channel ATD)
• 2 bytes reserved for digital port data
• The remaining bytes are undefined ( reserved for future use )

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VRH DAC
-
VRL

Control SAR
+
- Analog Power
Logic
EOC
COMMAND RESULT


What does the comparator do for the conversion process?

• The comparator tests whether the DAC output is higher or lower than the
sampled analog input. The comparator feeds this information to the SAR, which
adjusts the DAC one bit at a time until the conversion is complete.

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VRH DAC
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VRL

Control SAR
+
- Analog Power
Logic
EOC
COMMAND RESULT


What does the Successive Approximation Register do?

• The successive approximation register sets one bit of the conversion value at a
time, starting with the MSB. After all bits of the conversion have been
determined, the SAR contents are transferred to the Results Register, where it
can be accessed from the module bus under software control.

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VRH DAC
-
VRL

Control SAR
+
- Analog Power
Logic
EOC
COMMAND RESULT


What are some of the limitations of the ATD function?

• The conversion time of the ATD is dependent on the sample time selection.
• There is typically no DC level correction circuitry in the ATD module. This
means that any difference in ground levels between the analog sensor and the
ATD will create a corresponding error in the conversion result.
• Channel to channel gain adjust function is normally not included either.
Therefore, all analog sensor inputs need to have comparable voltage ranges.

+
VRH
DAC
-
VRL

Control SAR
+
- Analog Power
Start Conv. Logic
EOC
COMMAND RESULT


Conversion Mode Control and the Registers

• The programmer is primarily concerned with conversion mode control and the register
block.
• The register block is essentially an address assigned to access the module’s control setting,
status, and result data.
• External Trigger (ETRIG) allows synchronization of analog data capture with external
events, either in edge trigger mode or level trigger mode.
• When the ETRIGE control bit is 0, the external trigger is ignored.
• When the ETRIGE control bit is 1, external trigger modes are:

ETRIGE ETRIGLE ETRIGP
(enable) (level) (polarity)
1 0 0 Falling edge triggered- single conversion
1 0 1 Rising edge triggered – single conversion
1 1 0 Trigger active low- continuous conversion
1 1 1 Trigger active Hi – continuous conversion


Conversion Mode Control – Trigger Modes
• The atd_etrig_level_pol pattern exercises the various trigger modes.
• In all trigger modes, conversion starts when a trigger event occurs on the ETRIG pin.
• Latency time is a maximum of one bus cycle plus the delay inherent in the trigger circuit.
• When ETRIGE is enabled, conversions cannot be initiated by writing to the control register,
but rather must be triggered externally - using channel 0 as the external trigger input.
• In the atd_mulchan patterns, an entire sequence of conversions are initiated by a single
external trigger event.

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Control +
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ETRIG
Start Conv. Logic
EOC


Port Sharing Between Analog and Digital Data

• The ATD module is capable of sharing the input data port between analog and digital data.
• We have described the use of the port for providing analog input signals through the
multiplexer and the sample buffer to the ATD converter. (atd_analog_mux patterns)
• When configured as a digital input port, the data is directed to the digital port registers
(atd_port_func patterns)
• The port may even be split between analog and digital functions.

• Note: If your test pattern reads in undefined levels in digital input mode, check your timing
to ensure that analog signals are not present during the digital sample period.

• Gotcha: A read of the ATDPORT can affect the accuracy of an analog sample period.
Timing is important here in your test pattern also.

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What is the Clock Prescale Function?

• This function divides the bus clock down to a frequency suitable for the ATD converter.
(atd_prescalar pattern) The ATD has a max. operating frequency which is typically less
than the max. bus frequency.
• The prescale function provides a means for the user to control the ATD sample period. Of
course, the conversion time will also be affected. (atd_sample pattern)
• The binary prescalar value (0 to 31) plus one (1 to 32) equals the divisor value for the
modulus counter. The resulting frequency is divided again by 2.
• Example: MCU max. bus clock frequency = 16MHz and the ATD module has a max.
frequency spec. of 2MHz. Choose a prescalar value of 00011. (3+1)x2 = divide by 8

Bus Clock Modulus Counter Divide ATD Clock
+ by 2

PRS0-PRS4


A List of Some Other Modes and Test Patterns

• Power Down Mode is verified by the atd_adpu pattern. The purpose of this mode is to
conserve power when the ATD function is not in use. The module may be powered down
by the setting the ADPU bit to zero.

• Stop and Wait modes temporarily power down the module. (stop and wait patterns)

• Background Debug Mode – Used to set breakpoints for software debug (atd_freeze pat)

• Module Reset – There are two ways to reset the ATD module; either via the module’s bus
master reset signal, or by setting the RST bit in the ATDTEST register. (atd_reset pat)

• Gotcha – Powering up the module using the ADPU bit does not reset the module or
initialize the register block.


Testing ATD Patterns and Performance Specifications:

• Note: Ensure that VRH/VRL analog supply reference levels are inside of VDDA power
supply levels to prevent clipping the analog input signals. Check your Min Vdd functional
test instance setup. We don’t want 5V on VRH and 4.5V on VDDA…

• Example ATD Performance Specifications:

PARAMETER SYMBOL MIN TYP MAX UNITS

Resolution LSB 5 mV
Differential Nonlinearity DNL -1 1 Counts
Integral Nonlinearity INL -2 2 Counts
Absolute Error AE / TUA -2 2 Counts

The ramp test verifies all of these specifications. Definitions for each of these
specifications are on the following page.


Testing ATD Patterns and Performance Specifications:

PARAMETER Definition TEST?
Gain Error Difference in gain from ideal gain of one No
Differential Nonlinearity The difference of each code width from 1LSB. - Yes -
Based on normalized data - Spec
Integral (cumulative) Difference in transition points from ideal - Based on Yes -
Nonlinearity - INL normalized data - Spec
Missing Codes How many digital output codes were not generated Yes -
(Resolution) by the steps in input voltage. Gotcha
Offset Error Offset error is similar to INL except that only the No
first transition is checked and raw data is used.

Absolute Error Difference in transition points from ideal. Yes -
-Based on raw data (non-normalized) – Spec
MAX[(ViActual – ViIdeal)]


ATD Accuracy Definitions

ACTUAL 10-BIT TRANSFER CURVE

IDEAL TRANSFER CURVE
C
ABS ERROR LIMIT (10mV)
A (VRH-VRL)/(# bits of resolution) = one LSB.
For a 10-Bit ATD with VRH at 5.12V,
AE one LSB = 5.12V/1024 = .005V
8
AE = 10mV absolute error equals 2 counts
7
6
DNL = the difference of each code width
5 from one LSB or 5mV.
4
3
2
1

20 40 60 80
ANALOG INPUT VOLTAGE (mV)


A Key Section of the Register Table:

Reg Name Bit 7 6 5 4 3 2 1 Bit 0
ATDCTL2 ADPU AFFC AWAI ETRIGLE ETRIGP ETRIGE ASCIE ASCIF

ATDCTL3 0 S8C S4C 0 S1C FIFO FRZ1 FRZ0
ATDCTL4 0 SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0
ATDCTL5 SC 0 SCAN MULT CD CC CB CA
ATDSTAT0 SCF 0 ETORF FIFOR CC3 CC2 CC1 CC0
ATDSTAT1 CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0
ATDTEST0 SAR9 SAR8 SAR7 SAR6 SAR5 SAR4 SAR3 SAR2
ATDTEST1 SAR1 SAR0 RST 0 0 0 0 0
ATDSTAT2 0 0 0 0 CCF11 CCF10 CCF9 CCF8
ATDPORT0 0 0 0 0 Bit 11 Bit 10 Bit 9 Bit 8
ATDPORT1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0


ATD Control and Status Registers
• For example, ATD Control Register 2 (ADCTL2);
controls power up mode (ADPU), fast flag clear mode (AFFC),
Trigger modes, and interrupt control (ASCIE and ASCIF).
All of these bits are set to zero upon RESET.

• Control bits (CD/CC/CB/CA) comprise the analog input channel selection code.
Beware that setting these bits to create an invalid channel selection – results in the ATD
converting a value of zero. There will be no error flag set if this occurs!

• The same bits have a different function in special conversion mode: they select which of the
following special conversions to perform:
convert VRH
convert VRL
convert (VRH +VRL)/2.

• ATD status registers report status on; conversion complete, conversion sequence counter,
test bit, and external trigger.


Test Registers / Test Considerations
• The test registers implement various special (test) modes that are used to test the ATD
module. For example; this is the only mode that allows the Successive Approximation
Register to be written.

NOTES:

1. The accuracy of the ATD converter depends on the accuracy of the reference potentials.
Noise on the VREF pins is not rejected and will create noise in the digital output data.
It’s important for the reference pins to have a low AC impedance path to the source.
100nF or larger capacitor is recommended for this purpose.

2. Analog inputs also require low AC impedance in order to shunt noise current. A capacitor
with good high frequency characteristics between the input pin and VSSA would provide
this effect. The capacitor would have to be large enough to shunt the noise current and
small enough to avoid filtering out valid input signals. Since this conflicts with leakage test
requirements, it is practical to add these caps only on the CTO pins where they can be
switched out by DIB relays.


Sample Conversion Time
• Sample conversion time includes three elements:
1. Fixed sample period
2. Programmable sample period – 2, 4, 3, or 16 cycles in length
3. Conversion resolution period – requires 10 ATD clock cycles for a 10-bit conversion

• The fixed sample period is 2 ATD clock cycles
• The programmable sample period varies from 2 to 16 ATD clocks
• The conversion resolution period is equal to the number of bits.

• 10 bit sample / conversion = 2 + 2 + 10 cycles = 14 ATD clock cycles, assuming a
programmable sample period of 2 ATD clock cycles.

Fixed Program-
Sample able Successive Approximation Sequence
Period Sample (Resolution Period)
Period


Details from J750 Ramp Test Pattern:
• instruments = { ATD0P0_CTO:ctsrc;}
• vector ( $tset, crystal, control, address , data , porte , portk, timp , pwmp ,
pwmcp , wstp , scip, spip, mscanp, dlcp, atd0p , atd1p )
• //=============================================================================
• // This pattern works to incrementally test the accuracy of the ATD converter (Physical Test).
• // Notes: Pattern flow for single conversion.
• // A loop of #bit_val times will be inserted in the pattern.svmadr tester code.
• // This allows the code to be minimal and also, for the A/D template to
• // set and clear handshaking flags in a predictable manner.
• // The variable "bit_val" can be adjusted to loop for fractional LSB
• // ramp tests and provides a safety net for runaway code
//***************************************************************************
• //Design Strategy:
• // 1) Clear Teradyne Tester flags with Tester Directive.
• // 2) Power up ATD. The default pre-scalar is 6
• // (A pre-scalar value of 6 corresponds to an ATD conversion clock of 1.75MHz for 14 MHz bus).
• // 3) Initiate a conversion sequence.
• // Set the SCAN=1. This will start continuous conversions, sequence length = 4. ATD channel 0 is used.
• // 5) Set up loop to repeat A/D conversions.
• // Each conversion requires 84 ATD clocks.
• // A. Wait 10 us for CTO settling time and convert on current CTO voltage.
• // B. Read ATD result registers.
• // C. Increment CTO +1 LSB for input to ATD channel.
• // D. Store Conversion result.
• // Repeat steps A thru D above until the CTO has reached the maximum ramp value.
• //=========================================================

• // Start of loops for atd0 conversions - Hand Edited!
• // First 'stv' of every 12 is thrown away, so we must break up the loop into groups of 12.
• // To get 2048 data points, run the outer loop 186 times (186 * 11 =2046), plus 2 loops equal 2048.
• // Set up loop to repeat A/D conversions.
• set_loopA 186 > spm 111 H1X11 0000000000000000 XXXXXXXXXXXXXXXX 11010L0110 … ;
global conversion_2046:
• > spm 111 H1X11 0000000000000000 XXXXXXXXXXXXXXXX 11010L1011 11111 1111111 … ;
• // Dummy stv to begin modulo 12 datapoint capture loop
• stv > spm 111 H1X11 0000000000000000 XXXXXXXXXXXXXXXX 11010L0110 11111 … ;
• // Set inner loop to run 11 times for next 11 data points
• set_loopB 11 > spm 111 H1X11 0000000000000000 XXXXXXXXXXXXXXXX 11010L0110 … ;
• global datasend_2046:
• > spm 111 H1X11 0000000000000000 XXXXXXXXXXXXXXXX 11010L0111 11111 1111111 … ;
// A. Wait 10 us for CTO settling time and convert on current CTO voltage. Add delay for channel
conversion.
• // Repeat Wide Reads - Addr = $0000 Expected_Data = $xxxx, 140 times at 14MHz (frequency
dependent) Hand edited repeat count!
• repeat 139 > spm 111 H1X11 0000000000000000 XXXXXXXXXXXXXXXX 11010L0111 … ;
• > spm 111 H1X11 0000000000000000 XXXXXXXXXXXXXXXX 11010L0111 11111 1111111 …;
• // Repeat Wide Reads - Addr = $0000 Expected_Data = $xxxx, 112 times (frequency dependent) Hand
edited repeat count!
• // (One clock for each bit of resolution + 4 for selected sample period) x (prescalar value of 8) = 14 x 8
= 112 clock cycles
• repeat 111 > spm 111 H1X11 0000000000000000 XXXXXXXXXXXXXXXX 11010L0111 …;


• // B. Read ATD result registers
• // Wide Read - Addr = 0110 Expected_Data = XXXX
• > spm 111 H1X11 0000000100010000 XXXXXXXXXXXXXXXX 11010L0111 11111 1111111 … ; //
// C. Increment the CTO +1 LSB to the next ramp value
• (ATD0P0_CTO = send_i)
• stv > spm 111 H1X11 0000000100010000 VVVVVVVVVVXXXXXX 11010L0110 11111 1111111 … ;
• // #0021 The following vector is the end of the inner loop
• end_loopB datasend_2046 > spm 111 H1X11 0000000000000000 XXXXXXXXXXXXXXXX
11010L0110 11111 1111111 11111111 111111111 11111111XXXX 11 1111 11 11 111111…;
• // The following vector is the end of the conversion loop
• end_loopA conversion_2046 > spm 111 H1X11 0000000000000000 XXXXXXXXXXXXXXXX
11010L0110 11111 1111111 11111111 111111111 11111111XXXX 11 1111 11 11 1111111…;

• // Finish getting the last two conversion results:
• // Dummy stv to begin modulo 12 data point capture loop
• stv > spm 111 H1X11 0000000000000000 XXXXXXXXXXXXXXXX 11010L0110 11111 …;
• // Set loop to run twice for last 2 data points:
• set_loopB 2 > spm 111 H1X11 0000000000000000 XXXXXXXXXXXXXXXX 11010L0110 …;
• > spm 111 H1X11 0000000000000000 XXXXXXXXXXXXXXXX 11010L0111 11111 …;


• // Set loop to run twice for last 2 datapoints:
• set_loopB 2 > spm 111 H1X11 0000000000000000 XXXXXXXXXXXXXXXX 11010L0110 …;
• // A. Wait >10 us for CTO settling time and convert on current
• // CTO voltage. Add delay for channel conversion.
• // Repeat Wide Reads - Addr = $0000 Expected_Data = $xxxx, repeat 139 > spm 111 H1X11
0000000000000000 XXXXXXXXXXXXXXXX 11010L0111 11111 1111111 11111111 …;
• // Repeat Wide Reads - Addr = $0000 Expected_Data = $xxxx, 112 times (frequency dependent)
• // (One clock for each bit of resolution + 4 for selected sample period) x (prescalar value of 8) = 14 x 8
= 112 clock cycles
• repeat 111 > spm 111 H1X11 0000000000000000 XXXXXXXXXXXXXXXX 11010L0111 …;
• // B. Read ATD result registers
• // Wide Read - Addr = 0110 Expected_Data = XXXX
• // C. Increment the CTO +1 LSB to the next ramp value
• (ATD0P0_CTO = send_i)
• stv > spm 111 H1X11 0000000100010000 VVVVVVVVVVXXXXXX 11010L0110 11111 …;
• // #0021 The following vector is the end of the loop
• end_loopB datasend_2 > spm 111 H1X11 0000000000000000 XXXXXXXXXXXXXXXX
11010L0110 11111 1111111 11111111 111111111 11111111XXXX 11 1111 11 11 …;
• // This is an excerpt from the complete test pattern for illustration.


J750 Instance Editor for Ramp Test


Hardware Design Considerations

CTO0 RefA VRHA

0.1µF 0.1µF
CTO0 RefB VRLA

0.1µF

Analog GND

• Illustration of the capacitor network required for the CTO reference pins.


Questions & Answers

• Q - How do I know which analog pin to use for performing the ATD ramp test?
• A – Ask the design team which input pin is the worst case (longest path) input.
• Q – If signals arrive on multiple input channels, which channel takes priority?
• A – The channel is selected by the channel selection code: CD/CC/CB/CA.

+
VRH
DAC
-
VRL

Control SAR
+
-
Start Conv. Logic
EOC
COMMAND RESULT


References

• Using Microprocessors and Microcomputers, The Motorola Family;
Wray/Greenfield/Bannatyne
• Motorola Product Specifications
• Teradyne Integra Help File

Reference Voltages
+
-
Analog Power
-

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