SlideShare uma empresa Scribd logo
1 de 8
QUICK TUTORIAL ON IEEE 754
FLOATING POINT REPRESENTATION
-by
RITU RANJAN SHRIVASTWA
Decimal to IEEE 754 Floating point
representation
There are 32 bits in Standard IEEE 754 representation of floating point numbers in binary and
is divided into three parts namely:
• Sign bit
• Exponent
• Mantissa
The representation in bit format is as follows
Sign bit
1 or 0

EXPONENT
8 bits

MANTISSA
23 bits

To be represented in this format, a number should be in the following normalized form.
(+ or -) 1.(mantissa) x 2^(exponent)
Sometimes in question it asks not to convert in normalized form, otherwise it should be
converted to its normalized form
Decimal to IEEE 754 Floating point
representation
To convert a number into its normalized form, we need to do the following:
For example, we will take the decimal number +4.6
We see that the number before decimal is not equal to 1 which means we need to convert it
into normalized form and bring 1 there. To do this, we need to keep dividing it by 2 till we get
the normalized form with just 1 left before decimal.
This means
4.6 / 2
2.3 / 2

= 2.3
= 1.15

Hence we get the normalized form and we can write
+4.6  1.15 x 22
Now we will represent this using IEEE 754 standard
Decimal to IEEE 754 Floating point
representation
We have +1.15 x 22 to represent
1. The sign bit will be ‘0’ as the number is positive
2. The exponent will be 127+2=129 (here we are using 127 as bias value because, the 8 bit
exponent part can accommodate 256 values i.e., 0-255. In this range we need to display
both positive and negative powers, thus we use the first 128 numbers(0-127) to denote
negative power and next 128(128-255) for positive power. Thus unless mentioned as
Excess-128 or Excess-64, we will use 2n-1 as the Bias value where n is the number of bits
in the exponent part.) Hence, if the power had been negative, then the exponent value
would have been
127+(-2) = 127-2 = 125
3. Since we have got our sign bit, and exponent, lets fill them up in the bit pattern.
0

10000001
12910  100000012

MANTISSA
23 bits
Decimal to IEEE 754 Floating point
representation
Now we need to find out the mantissa part.
First of all, not that the ‘1’ is NOT represented in the bit pattern since it is in the normalized
form, it is known that the ‘1’ will exist. Thus in the mantissa part only the decimal part i.e.,
(0.15) need to be represented.
Let us convert the 0.15 to binary
0.15 x 2 = 0.3 0
0.3 x 2 = 0.6
0
0.6 x 2 = 1.2
1
(i)
0.2 x 2 = 0.4
0
0.4 x 2 = 0.8
0
0.8 x 2 = 1.6
1
(ii)
Now the value from (i) till (ii) will continue to recur and we will keep recurring it till 23 bits
are filled.
Thus the bits obtained are 00100110011001100110011
Hence the bit pattern in the 32 bit format are
0

10000001

00100110011001100110011

 (40933333)16
EXAMPLE PROBLEM

NOTE : In this question,
The total no of bits is only
16. They have given the
bias as 64, where it
should be 63, so you
need to use 64. And also,
the given number need
not be converted into its
normal form
IEEE 754 Floating point to Decimal
conversion
You need to do just the reverse of the above which is very simple.
For example:
Given Binary representation: 11000001101111110……0
Thus we will break it into three parts as:
1

10000011

01111110000000000000000

We clearly see that the number is negative and the power is 131-127 = 4
Mantissa is: 2-1x0 + 2-2x1 + 2-3x1 + 2-4x1 + 2-5x1 + 2-6x1 + 2-7x1 = 0.4921875
The number is -1.4921875 x 24 [note the ‘1’ is added before the 0 in the normal fom]
Which is equal to -23.875
ANS: -23.875
THANK YOU

Mais conteúdo relacionado

Mais procurados (20)

3.Fixed-Floating Point.ppt
3.Fixed-Floating Point.ppt3.Fixed-Floating Point.ppt
3.Fixed-Floating Point.ppt
 
Chapter 1 digital systems and binary numbers
Chapter 1 digital systems and binary numbersChapter 1 digital systems and binary numbers
Chapter 1 digital systems and binary numbers
 
Floating point presentation
Floating point presentationFloating point presentation
Floating point presentation
 
06 floating point
06 floating point06 floating point
06 floating point
 
Binary Arithmetic
Binary ArithmeticBinary Arithmetic
Binary Arithmetic
 
Booth’s algorithm.(a014& a015)
Booth’s algorithm.(a014& a015)Booth’s algorithm.(a014& a015)
Booth’s algorithm.(a014& a015)
 
Binary codes
Binary codesBinary codes
Binary codes
 
K - Map
  K - Map    K - Map
K - Map
 
BCD.
BCD.BCD.
BCD.
 
Multiplication algorithm
Multiplication algorithmMultiplication algorithm
Multiplication algorithm
 
Gray Code.pptx
Gray Code.pptxGray Code.pptx
Gray Code.pptx
 
encoder and decoder in digital electronics
encoder and decoder in digital electronicsencoder and decoder in digital electronics
encoder and decoder in digital electronics
 
Number system conversion
Number system conversionNumber system conversion
Number system conversion
 
Computer arithmetic
Computer arithmeticComputer arithmetic
Computer arithmetic
 
Basics of digital electronics
Basics of digital electronicsBasics of digital electronics
Basics of digital electronics
 
Binary Arithmetic
Binary ArithmeticBinary Arithmetic
Binary Arithmetic
 
1’s and 2’s complements
1’s and 2’s complements1’s and 2’s complements
1’s and 2’s complements
 
Binary codes
Binary codesBinary codes
Binary codes
 
Combinational circuits
Combinational circuitsCombinational circuits
Combinational circuits
 
SOP POS, Minterm and Maxterm
SOP POS, Minterm and MaxtermSOP POS, Minterm and Maxterm
SOP POS, Minterm and Maxterm
 

Destaque

Floating point ALU using VHDL implemented on FPGA
Floating point ALU using VHDL implemented on FPGAFloating point ALU using VHDL implemented on FPGA
Floating point ALU using VHDL implemented on FPGAAzhar Syed
 
Design and implementation of 32 bit alu using verilog
Design and implementation of 32 bit alu using verilogDesign and implementation of 32 bit alu using verilog
Design and implementation of 32 bit alu using verilogSTEPHEN MOIRANGTHEM
 
Bit Serial multiplier using Verilog
Bit Serial multiplier using VerilogBit Serial multiplier using Verilog
Bit Serial multiplier using VerilogBhargavKatkam
 
floating point multiplier
floating point multiplierfloating point multiplier
floating point multiplierBipin Likhar
 
implementation and design of 32-bit adder
implementation and design of 32-bit adderimplementation and design of 32-bit adder
implementation and design of 32-bit adderveereshwararao
 
Alu design-project
Alu design-projectAlu design-project
Alu design-projectalphankg1
 
Wallace tree multiplier.pptx1
Wallace tree multiplier.pptx1Wallace tree multiplier.pptx1
Wallace tree multiplier.pptx1vamshi krishna
 
DESIGN AND SIMULATION OF DIFFERENT 8-BIT MULTIPLIERS USING VERILOG CODE BY SA...
DESIGN AND SIMULATION OF DIFFERENT 8-BIT MULTIPLIERS USING VERILOG CODE BY SA...DESIGN AND SIMULATION OF DIFFERENT 8-BIT MULTIPLIERS USING VERILOG CODE BY SA...
DESIGN AND SIMULATION OF DIFFERENT 8-BIT MULTIPLIERS USING VERILOG CODE BY SA...Saikiran Panjala
 
Wallace tree multiplier
Wallace tree multiplierWallace tree multiplier
Wallace tree multiplierSudhir Kumar
 
All VLSI programs
All VLSI programsAll VLSI programs
All VLSI programsGouthaman V
 
Designing of 8 BIT Arithmetic and Logical Unit and implementing on Xilinx Ver...
Designing of 8 BIT Arithmetic and Logical Unit and implementing on Xilinx Ver...Designing of 8 BIT Arithmetic and Logical Unit and implementing on Xilinx Ver...
Designing of 8 BIT Arithmetic and Logical Unit and implementing on Xilinx Ver...Rahul Borthakur
 
Microsoft GDI+ JPEG Integer Underflow Vulnerability
Microsoft GDI+ JPEG Integer Underflow VulnerabilityMicrosoft GDI+ JPEG Integer Underflow Vulnerability
Microsoft GDI+ JPEG Integer Underflow VulnerabilityAshish Malik
 
Design and Implementation of Single Precision Pipelined Floating Point Co-Pro...
Design and Implementation of Single Precision Pipelined Floating Point Co-Pro...Design and Implementation of Single Precision Pipelined Floating Point Co-Pro...
Design and Implementation of Single Precision Pipelined Floating Point Co-Pro...Silicon Mentor
 
Free video lectures for mca
Free video lectures for mcaFree video lectures for mca
Free video lectures for mcaEdhole.com
 
Decimal arithmetic in Processors
Decimal arithmetic in ProcessorsDecimal arithmetic in Processors
Decimal arithmetic in ProcessorsPeeyush Pashine
 
data representation
 data representation data representation
data representationHaroon_007
 

Destaque (20)

Floating point ALU using VHDL implemented on FPGA
Floating point ALU using VHDL implemented on FPGAFloating point ALU using VHDL implemented on FPGA
Floating point ALU using VHDL implemented on FPGA
 
Design and implementation of 32 bit alu using verilog
Design and implementation of 32 bit alu using verilogDesign and implementation of 32 bit alu using verilog
Design and implementation of 32 bit alu using verilog
 
Bit Serial multiplier using Verilog
Bit Serial multiplier using VerilogBit Serial multiplier using Verilog
Bit Serial multiplier using Verilog
 
floating point multiplier
floating point multiplierfloating point multiplier
floating point multiplier
 
implementation and design of 32-bit adder
implementation and design of 32-bit adderimplementation and design of 32-bit adder
implementation and design of 32-bit adder
 
Alu design-project
Alu design-projectAlu design-project
Alu design-project
 
Wallace tree multiplier.pptx1
Wallace tree multiplier.pptx1Wallace tree multiplier.pptx1
Wallace tree multiplier.pptx1
 
DESIGN AND SIMULATION OF DIFFERENT 8-BIT MULTIPLIERS USING VERILOG CODE BY SA...
DESIGN AND SIMULATION OF DIFFERENT 8-BIT MULTIPLIERS USING VERILOG CODE BY SA...DESIGN AND SIMULATION OF DIFFERENT 8-BIT MULTIPLIERS USING VERILOG CODE BY SA...
DESIGN AND SIMULATION OF DIFFERENT 8-BIT MULTIPLIERS USING VERILOG CODE BY SA...
 
Wallace tree multiplier
Wallace tree multiplierWallace tree multiplier
Wallace tree multiplier
 
All VLSI programs
All VLSI programsAll VLSI programs
All VLSI programs
 
VERILOG CODE
VERILOG CODEVERILOG CODE
VERILOG CODE
 
Designing of 8 BIT Arithmetic and Logical Unit and implementing on Xilinx Ver...
Designing of 8 BIT Arithmetic and Logical Unit and implementing on Xilinx Ver...Designing of 8 BIT Arithmetic and Logical Unit and implementing on Xilinx Ver...
Designing of 8 BIT Arithmetic and Logical Unit and implementing on Xilinx Ver...
 
Array multiplier
Array multiplierArray multiplier
Array multiplier
 
Microsoft GDI+ JPEG Integer Underflow Vulnerability
Microsoft GDI+ JPEG Integer Underflow VulnerabilityMicrosoft GDI+ JPEG Integer Underflow Vulnerability
Microsoft GDI+ JPEG Integer Underflow Vulnerability
 
IEEE Floating Point
IEEE Floating PointIEEE Floating Point
IEEE Floating Point
 
Class10
Class10Class10
Class10
 
Design and Implementation of Single Precision Pipelined Floating Point Co-Pro...
Design and Implementation of Single Precision Pipelined Floating Point Co-Pro...Design and Implementation of Single Precision Pipelined Floating Point Co-Pro...
Design and Implementation of Single Precision Pipelined Floating Point Co-Pro...
 
Free video lectures for mca
Free video lectures for mcaFree video lectures for mca
Free video lectures for mca
 
Decimal arithmetic in Processors
Decimal arithmetic in ProcessorsDecimal arithmetic in Processors
Decimal arithmetic in Processors
 
data representation
 data representation data representation
data representation
 

Semelhante a Quick tutorial on IEEE 754 FLOATING POINT representation

International Journal of Engineering Research and Development
International Journal of Engineering Research and DevelopmentInternational Journal of Engineering Research and Development
International Journal of Engineering Research and DevelopmentIJERD Editor
 
Binary octal
Binary octalBinary octal
Binary octaldrdipo4
 
Lec 02 data representation part 1
Lec 02 data representation part 1Lec 02 data representation part 1
Lec 02 data representation part 1Abdul Khan
 
Integer Representation
Integer RepresentationInteger Representation
Integer Representationgavhays
 
Number system and codes
Number system and codesNumber system and codes
Number system and codesAbhiraj Bohra
 
100_2_digitalSystem_Chap1 (2).ppt
100_2_digitalSystem_Chap1 (2).ppt100_2_digitalSystem_Chap1 (2).ppt
100_2_digitalSystem_Chap1 (2).pptnamraashraf56
 
Lesson 1 basic theory of information
Lesson 1   basic theory of informationLesson 1   basic theory of information
Lesson 1 basic theory of informationRoma Kimberly Erolin
 
Lesson 1 basic theory of information
Lesson 1   basic theory of informationLesson 1   basic theory of information
Lesson 1 basic theory of informationRoma Kimberly Erolin
 
digital systems and information
digital systems and informationdigital systems and information
digital systems and informationKamran Zafar
 
Convertion of single precision
Convertion of single precisionConvertion of single precision
Convertion of single precisionnikhilarora2211
 
Number system by ammar nawab
Number system by ammar nawabNumber system by ammar nawab
Number system by ammar nawabAmmar_n
 
U1 - Code Conversion.pptx
U1 - Code Conversion.pptxU1 - Code Conversion.pptx
U1 - Code Conversion.pptxRamKumar612299
 
Chapter 2_Number system (EEEg4302).pdf
Chapter 2_Number system (EEEg4302).pdfChapter 2_Number system (EEEg4302).pdf
Chapter 2_Number system (EEEg4302).pdfTamiratDejene1
 
Computer Oraganizaation.pptx
Computer Oraganizaation.pptxComputer Oraganizaation.pptx
Computer Oraganizaation.pptxbmangesh
 

Semelhante a Quick tutorial on IEEE 754 FLOATING POINT representation (20)

International Journal of Engineering Research and Development
International Journal of Engineering Research and DevelopmentInternational Journal of Engineering Research and Development
International Journal of Engineering Research and Development
 
Binary octal
Binary octalBinary octal
Binary octal
 
Representation of Negative Numbers
Representation of Negative NumbersRepresentation of Negative Numbers
Representation of Negative Numbers
 
Lec 02 data representation part 1
Lec 02 data representation part 1Lec 02 data representation part 1
Lec 02 data representation part 1
 
Alu1
Alu1Alu1
Alu1
 
Integer Representation
Integer RepresentationInteger Representation
Integer Representation
 
Data Representation
Data RepresentationData Representation
Data Representation
 
Number system and codes
Number system and codesNumber system and codes
Number system and codes
 
100_2_digitalSystem_Chap1 (2).ppt
100_2_digitalSystem_Chap1 (2).ppt100_2_digitalSystem_Chap1 (2).ppt
100_2_digitalSystem_Chap1 (2).ppt
 
2's complement
2's complement2's complement
2's complement
 
Lesson 1 basic theory of information
Lesson 1   basic theory of informationLesson 1   basic theory of information
Lesson 1 basic theory of information
 
Lesson 1 basic theory of information
Lesson 1   basic theory of informationLesson 1   basic theory of information
Lesson 1 basic theory of information
 
digital systems and information
digital systems and informationdigital systems and information
digital systems and information
 
Data Representation
Data RepresentationData Representation
Data Representation
 
Convertion of single precision
Convertion of single precisionConvertion of single precision
Convertion of single precision
 
Number system by ammar nawab
Number system by ammar nawabNumber system by ammar nawab
Number system by ammar nawab
 
U1 - Code Conversion.pptx
U1 - Code Conversion.pptxU1 - Code Conversion.pptx
U1 - Code Conversion.pptx
 
Chapter 2_Number system (EEEg4302).pdf
Chapter 2_Number system (EEEg4302).pdfChapter 2_Number system (EEEg4302).pdf
Chapter 2_Number system (EEEg4302).pdf
 
09 Arithmetic
09  Arithmetic09  Arithmetic
09 Arithmetic
 
Computer Oraganizaation.pptx
Computer Oraganizaation.pptxComputer Oraganizaation.pptx
Computer Oraganizaation.pptx
 

Último

Measures of Central Tendency: Mean, Median and Mode
Measures of Central Tendency: Mean, Median and ModeMeasures of Central Tendency: Mean, Median and Mode
Measures of Central Tendency: Mean, Median and ModeThiyagu K
 
Sanyam Choudhary Chemistry practical.pdf
Sanyam Choudhary Chemistry practical.pdfSanyam Choudhary Chemistry practical.pdf
Sanyam Choudhary Chemistry practical.pdfsanyamsingh5019
 
BASLIQ CURRENT LOOKBOOK LOOKBOOK(1) (1).pdf
BASLIQ CURRENT LOOKBOOK  LOOKBOOK(1) (1).pdfBASLIQ CURRENT LOOKBOOK  LOOKBOOK(1) (1).pdf
BASLIQ CURRENT LOOKBOOK LOOKBOOK(1) (1).pdfSoniaTolstoy
 
A Critique of the Proposed National Education Policy Reform
A Critique of the Proposed National Education Policy ReformA Critique of the Proposed National Education Policy Reform
A Critique of the Proposed National Education Policy ReformChameera Dedduwage
 
Software Engineering Methodologies (overview)
Software Engineering Methodologies (overview)Software Engineering Methodologies (overview)
Software Engineering Methodologies (overview)eniolaolutunde
 
Kisan Call Centre - To harness potential of ICT in Agriculture by answer farm...
Kisan Call Centre - To harness potential of ICT in Agriculture by answer farm...Kisan Call Centre - To harness potential of ICT in Agriculture by answer farm...
Kisan Call Centre - To harness potential of ICT in Agriculture by answer farm...Krashi Coaching
 
Call Girls in Dwarka Mor Delhi Contact Us 9654467111
Call Girls in Dwarka Mor Delhi Contact Us 9654467111Call Girls in Dwarka Mor Delhi Contact Us 9654467111
Call Girls in Dwarka Mor Delhi Contact Us 9654467111Sapana Sha
 
SOCIAL AND HISTORICAL CONTEXT - LFTVD.pptx
SOCIAL AND HISTORICAL CONTEXT - LFTVD.pptxSOCIAL AND HISTORICAL CONTEXT - LFTVD.pptx
SOCIAL AND HISTORICAL CONTEXT - LFTVD.pptxiammrhaywood
 
Ecosystem Interactions Class Discussion Presentation in Blue Green Lined Styl...
Ecosystem Interactions Class Discussion Presentation in Blue Green Lined Styl...Ecosystem Interactions Class Discussion Presentation in Blue Green Lined Styl...
Ecosystem Interactions Class Discussion Presentation in Blue Green Lined Styl...fonyou31
 
General AI for Medical Educators April 2024
General AI for Medical Educators April 2024General AI for Medical Educators April 2024
General AI for Medical Educators April 2024Janet Corral
 
Arihant handbook biology for class 11 .pdf
Arihant handbook biology for class 11 .pdfArihant handbook biology for class 11 .pdf
Arihant handbook biology for class 11 .pdfchloefrazer622
 
Beyond the EU: DORA and NIS 2 Directive's Global Impact
Beyond the EU: DORA and NIS 2 Directive's Global ImpactBeyond the EU: DORA and NIS 2 Directive's Global Impact
Beyond the EU: DORA and NIS 2 Directive's Global ImpactPECB
 
Student login on Anyboli platform.helpin
Student login on Anyboli platform.helpinStudent login on Anyboli platform.helpin
Student login on Anyboli platform.helpinRaunakKeshri1
 
9548086042 for call girls in Indira Nagar with room service
9548086042  for call girls in Indira Nagar  with room service9548086042  for call girls in Indira Nagar  with room service
9548086042 for call girls in Indira Nagar with room servicediscovermytutordmt
 
fourth grading exam for kindergarten in writing
fourth grading exam for kindergarten in writingfourth grading exam for kindergarten in writing
fourth grading exam for kindergarten in writingTeacherCyreneCayanan
 
Introduction to Nonprofit Accounting: The Basics
Introduction to Nonprofit Accounting: The BasicsIntroduction to Nonprofit Accounting: The Basics
Introduction to Nonprofit Accounting: The BasicsTechSoup
 
Key note speaker Neum_Admir Softic_ENG.pdf
Key note speaker Neum_Admir Softic_ENG.pdfKey note speaker Neum_Admir Softic_ENG.pdf
Key note speaker Neum_Admir Softic_ENG.pdfAdmir Softic
 
Class 11th Physics NEET formula sheet pdf
Class 11th Physics NEET formula sheet pdfClass 11th Physics NEET formula sheet pdf
Class 11th Physics NEET formula sheet pdfAyushMahapatra5
 
Z Score,T Score, Percential Rank and Box Plot Graph
Z Score,T Score, Percential Rank and Box Plot GraphZ Score,T Score, Percential Rank and Box Plot Graph
Z Score,T Score, Percential Rank and Box Plot GraphThiyagu K
 

Último (20)

Measures of Central Tendency: Mean, Median and Mode
Measures of Central Tendency: Mean, Median and ModeMeasures of Central Tendency: Mean, Median and Mode
Measures of Central Tendency: Mean, Median and Mode
 
Sanyam Choudhary Chemistry practical.pdf
Sanyam Choudhary Chemistry practical.pdfSanyam Choudhary Chemistry practical.pdf
Sanyam Choudhary Chemistry practical.pdf
 
BASLIQ CURRENT LOOKBOOK LOOKBOOK(1) (1).pdf
BASLIQ CURRENT LOOKBOOK  LOOKBOOK(1) (1).pdfBASLIQ CURRENT LOOKBOOK  LOOKBOOK(1) (1).pdf
BASLIQ CURRENT LOOKBOOK LOOKBOOK(1) (1).pdf
 
A Critique of the Proposed National Education Policy Reform
A Critique of the Proposed National Education Policy ReformA Critique of the Proposed National Education Policy Reform
A Critique of the Proposed National Education Policy Reform
 
Software Engineering Methodologies (overview)
Software Engineering Methodologies (overview)Software Engineering Methodologies (overview)
Software Engineering Methodologies (overview)
 
INDIA QUIZ 2024 RLAC DELHI UNIVERSITY.pptx
INDIA QUIZ 2024 RLAC DELHI UNIVERSITY.pptxINDIA QUIZ 2024 RLAC DELHI UNIVERSITY.pptx
INDIA QUIZ 2024 RLAC DELHI UNIVERSITY.pptx
 
Kisan Call Centre - To harness potential of ICT in Agriculture by answer farm...
Kisan Call Centre - To harness potential of ICT in Agriculture by answer farm...Kisan Call Centre - To harness potential of ICT in Agriculture by answer farm...
Kisan Call Centre - To harness potential of ICT in Agriculture by answer farm...
 
Call Girls in Dwarka Mor Delhi Contact Us 9654467111
Call Girls in Dwarka Mor Delhi Contact Us 9654467111Call Girls in Dwarka Mor Delhi Contact Us 9654467111
Call Girls in Dwarka Mor Delhi Contact Us 9654467111
 
SOCIAL AND HISTORICAL CONTEXT - LFTVD.pptx
SOCIAL AND HISTORICAL CONTEXT - LFTVD.pptxSOCIAL AND HISTORICAL CONTEXT - LFTVD.pptx
SOCIAL AND HISTORICAL CONTEXT - LFTVD.pptx
 
Ecosystem Interactions Class Discussion Presentation in Blue Green Lined Styl...
Ecosystem Interactions Class Discussion Presentation in Blue Green Lined Styl...Ecosystem Interactions Class Discussion Presentation in Blue Green Lined Styl...
Ecosystem Interactions Class Discussion Presentation in Blue Green Lined Styl...
 
General AI for Medical Educators April 2024
General AI for Medical Educators April 2024General AI for Medical Educators April 2024
General AI for Medical Educators April 2024
 
Arihant handbook biology for class 11 .pdf
Arihant handbook biology for class 11 .pdfArihant handbook biology for class 11 .pdf
Arihant handbook biology for class 11 .pdf
 
Beyond the EU: DORA and NIS 2 Directive's Global Impact
Beyond the EU: DORA and NIS 2 Directive's Global ImpactBeyond the EU: DORA and NIS 2 Directive's Global Impact
Beyond the EU: DORA and NIS 2 Directive's Global Impact
 
Student login on Anyboli platform.helpin
Student login on Anyboli platform.helpinStudent login on Anyboli platform.helpin
Student login on Anyboli platform.helpin
 
9548086042 for call girls in Indira Nagar with room service
9548086042  for call girls in Indira Nagar  with room service9548086042  for call girls in Indira Nagar  with room service
9548086042 for call girls in Indira Nagar with room service
 
fourth grading exam for kindergarten in writing
fourth grading exam for kindergarten in writingfourth grading exam for kindergarten in writing
fourth grading exam for kindergarten in writing
 
Introduction to Nonprofit Accounting: The Basics
Introduction to Nonprofit Accounting: The BasicsIntroduction to Nonprofit Accounting: The Basics
Introduction to Nonprofit Accounting: The Basics
 
Key note speaker Neum_Admir Softic_ENG.pdf
Key note speaker Neum_Admir Softic_ENG.pdfKey note speaker Neum_Admir Softic_ENG.pdf
Key note speaker Neum_Admir Softic_ENG.pdf
 
Class 11th Physics NEET formula sheet pdf
Class 11th Physics NEET formula sheet pdfClass 11th Physics NEET formula sheet pdf
Class 11th Physics NEET formula sheet pdf
 
Z Score,T Score, Percential Rank and Box Plot Graph
Z Score,T Score, Percential Rank and Box Plot GraphZ Score,T Score, Percential Rank and Box Plot Graph
Z Score,T Score, Percential Rank and Box Plot Graph
 

Quick tutorial on IEEE 754 FLOATING POINT representation

  • 1. QUICK TUTORIAL ON IEEE 754 FLOATING POINT REPRESENTATION -by RITU RANJAN SHRIVASTWA
  • 2. Decimal to IEEE 754 Floating point representation There are 32 bits in Standard IEEE 754 representation of floating point numbers in binary and is divided into three parts namely: • Sign bit • Exponent • Mantissa The representation in bit format is as follows Sign bit 1 or 0 EXPONENT 8 bits MANTISSA 23 bits To be represented in this format, a number should be in the following normalized form. (+ or -) 1.(mantissa) x 2^(exponent) Sometimes in question it asks not to convert in normalized form, otherwise it should be converted to its normalized form
  • 3. Decimal to IEEE 754 Floating point representation To convert a number into its normalized form, we need to do the following: For example, we will take the decimal number +4.6 We see that the number before decimal is not equal to 1 which means we need to convert it into normalized form and bring 1 there. To do this, we need to keep dividing it by 2 till we get the normalized form with just 1 left before decimal. This means 4.6 / 2 2.3 / 2 = 2.3 = 1.15 Hence we get the normalized form and we can write +4.6  1.15 x 22 Now we will represent this using IEEE 754 standard
  • 4. Decimal to IEEE 754 Floating point representation We have +1.15 x 22 to represent 1. The sign bit will be ‘0’ as the number is positive 2. The exponent will be 127+2=129 (here we are using 127 as bias value because, the 8 bit exponent part can accommodate 256 values i.e., 0-255. In this range we need to display both positive and negative powers, thus we use the first 128 numbers(0-127) to denote negative power and next 128(128-255) for positive power. Thus unless mentioned as Excess-128 or Excess-64, we will use 2n-1 as the Bias value where n is the number of bits in the exponent part.) Hence, if the power had been negative, then the exponent value would have been 127+(-2) = 127-2 = 125 3. Since we have got our sign bit, and exponent, lets fill them up in the bit pattern. 0 10000001 12910  100000012 MANTISSA 23 bits
  • 5. Decimal to IEEE 754 Floating point representation Now we need to find out the mantissa part. First of all, not that the ‘1’ is NOT represented in the bit pattern since it is in the normalized form, it is known that the ‘1’ will exist. Thus in the mantissa part only the decimal part i.e., (0.15) need to be represented. Let us convert the 0.15 to binary 0.15 x 2 = 0.3 0 0.3 x 2 = 0.6 0 0.6 x 2 = 1.2 1 (i) 0.2 x 2 = 0.4 0 0.4 x 2 = 0.8 0 0.8 x 2 = 1.6 1 (ii) Now the value from (i) till (ii) will continue to recur and we will keep recurring it till 23 bits are filled. Thus the bits obtained are 00100110011001100110011 Hence the bit pattern in the 32 bit format are 0 10000001 00100110011001100110011  (40933333)16
  • 6. EXAMPLE PROBLEM NOTE : In this question, The total no of bits is only 16. They have given the bias as 64, where it should be 63, so you need to use 64. And also, the given number need not be converted into its normal form
  • 7. IEEE 754 Floating point to Decimal conversion You need to do just the reverse of the above which is very simple. For example: Given Binary representation: 11000001101111110……0 Thus we will break it into three parts as: 1 10000011 01111110000000000000000 We clearly see that the number is negative and the power is 131-127 = 4 Mantissa is: 2-1x0 + 2-2x1 + 2-3x1 + 2-4x1 + 2-5x1 + 2-6x1 + 2-7x1 = 0.4921875 The number is -1.4921875 x 24 [note the ‘1’ is added before the 0 in the normal fom] Which is equal to -23.875 ANS: -23.875