SlideShare a Scribd company logo

VHDL

•Download as PPT, PDF•
•
Ramasubbu .P
Ramasubbu .P

The document provides an introduction to VHDL including its origins, domains of description, abstraction levels, modeling styles, and examples of behavioral and structural descriptions. It discusses key VHDL concepts such as entities, architectures, concurrency, hierarchy, and modeling at different levels of abstraction using both behavioral and structural descriptions. Examples include behavioral descriptions of basic components like an AND gate, full adder, D flip-flop, and 4-to-1 multiplexer as well as structural descriptions of a 4-bit adder and 4-bit comparator.

EducationTechnologyDesign
1 of 34
Introduction to VHDL M. Balakrishnan Dept of Computer Science & Engg. I.I.T. Delhi
Domains of Description : Gajski’s Y-Chart Behavioral domain Structural domain Physical domain Level of abstraction VHDL models
VHDL Development ,[object Object],[object Object],[object Object],[object Object]
HDL Requirements ,[object Object],[object Object],[object Object],[object Object]
Abstraction ,[object Object],[object Object],[object Object],[object Object]
Modularity ,[object Object],[object Object],[object Object],[object Object]
VHDL Example a b c AND
VHDL Description: AND gate ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Concurrency in VHDL Descriptions signals process 1 process 2 process n signals
Concurrent and Sequential Computations ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Hierarchy in VHDL
Modeling Styles in VHDL M. Balakrishnan Dept. of Comp. Sci. & Engg. I.I.T. Delhi
Modeling Styles ,[object Object],[object Object],[object Object],[object Object],[object Object]
Modeling Choices in VHDL ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Structural Description ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Behavioral Description ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Concurrent Statements in VHDL ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Example: 1-bit Full Adder ,[object Object],[object Object],[object Object],[object Object],X Y Cin Sum Cout FullAdder
Example: 1-bit Full Adder (contd.) ,[object Object],[object Object],[object Object],[object Object],[object Object]
Example: 4-bit Adder ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Example: 4-bit Adder (contd.) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Example: 4-bit Comparator ,[object Object],[object Object],[object Object],[object Object],[object Object]
Structural Description (contd.) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Example: 1-bit Comparator (data flow) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
References ,[object Object],[object Object],[object Object],[object Object],[object Object]
Behavioral Description in VHDL M. Balakrishnan Dept. of Comp. Sci. & Engg. I.I.T. Delhi
Modeling Styles ,[object Object],[object Object],[object Object],[object Object],[object Object]
Concurrent Statements in VHDL ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Example: D Flip-Flop ,[object Object],[object Object],[object Object],[object Object],D CLK Q QN DFF
Example: DFF (contd.) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Concurrent Conditional Assignment: 4 to 1 Multiplexer ,[object Object],[object Object],[object Object],[object Object],x0 x1 x2 x3 sel y
CASE Statement: 4 to 1 Multiplexer Case sel is when 0 => y <= x0 when 1 => y <= x1 when 2 => y <= x2 when 3 => y <= x3 end case x0 x1 x2 x3 y
Variables And Signals ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Variables And Signals ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Recommended

VHDL-PRESENTATION.ppt
VHDL-PRESENTATION.pptVHDL-PRESENTATION.ppt
VHDL-PRESENTATION.pptDr.YNM
 
Verilog HDL
Verilog HDLVerilog HDL
Verilog HDLMantra VLSI
 
Vlsi
VlsiVlsi
VlsiPoornima institute of engineering and technology
 
Verilog hdl
Verilog hdlVerilog hdl
Verilog hdlMuhammad Uzair Rasheed
 
Logic Synthesis
Logic SynthesisLogic Synthesis
Logic SynthesisVandanaPagar1
 
Altera flex
Altera flexAltera flex
Altera flexSharmil Nila
 
Fpga architectures and applications
Fpga architectures and applicationsFpga architectures and applications
Fpga architectures and applicationsSudhanshu Janwadkar
 
Introduction to VHDL - Part 1
Introduction to VHDL - Part 1Introduction to VHDL - Part 1
Introduction to VHDL - Part 1Abhilash Nair
 

Recommended

VHDL-PRESENTATION.ppt
VHDL-PRESENTATION.pptVHDL-PRESENTATION.ppt
VHDL-PRESENTATION.pptDr.YNM
 
Verilog HDL
Verilog HDLVerilog HDL
Verilog HDLMantra VLSI
 
Vlsi
VlsiVlsi
VlsiPoornima institute of engineering and technology
 
Verilog hdl
Verilog hdlVerilog hdl
Verilog hdlMuhammad Uzair Rasheed
 
Logic Synthesis
Logic SynthesisLogic Synthesis
Logic SynthesisVandanaPagar1
 
Altera flex
Altera flexAltera flex
Altera flexSharmil Nila
 
Fpga architectures and applications
Fpga architectures and applicationsFpga architectures and applications
Fpga architectures and applicationsSudhanshu Janwadkar
 
Introduction to VHDL - Part 1
Introduction to VHDL - Part 1Introduction to VHDL - Part 1
Introduction to VHDL - Part 1Abhilash Nair
 
Verilog tutorial
Verilog tutorialVerilog tutorial
Verilog tutorialMaryala Srinivas
 
Xilinx 4000 series
Xilinx 4000 seriesXilinx 4000 series
Xilinx 4000 seriesdragonpradeep
 
VLSI Testing Techniques
VLSI Testing TechniquesVLSI Testing Techniques
VLSI Testing TechniquesA B Shinde
 
Verilog Tasks & Functions
Verilog Tasks & FunctionsVerilog Tasks & Functions
Verilog Tasks & Functionsanand hd
 
Introduction to FPGA, VHDL
Introduction to FPGA, VHDL Introduction to FPGA, VHDL
Introduction to FPGA, VHDL Amr Rashed
 
FPGA
FPGAFPGA
FPGAsubin mathew
 
Embedded c
Embedded cEmbedded c
Embedded cAmi Prakash
 
An Introductory course on Verilog HDL-Verilog hdl ppr
An Introductory course on Verilog HDL-Verilog hdl pprAn Introductory course on Verilog HDL-Verilog hdl ppr
An Introductory course on Verilog HDL-Verilog hdl pprPrabhavathi P
 
Complex Programmable Logic Devices(CPLD) & Field Programmable Logic Devices (...
Complex Programmable Logic Devices(CPLD) & Field Programmable Logic Devices (...Complex Programmable Logic Devices(CPLD) & Field Programmable Logic Devices (...
Complex Programmable Logic Devices(CPLD) & Field Programmable Logic Devices (...Revathi Subramaniam
 
Design and implementation of 32 bit alu using verilog
Design and implementation of 32 bit alu using verilogDesign and implementation of 32 bit alu using verilog
Design and implementation of 32 bit alu using verilogSTEPHEN MOIRANGTHEM
 
Pipelining approach
Pipelining approachPipelining approach
Pipelining approachGopinathD17
 
Asic design
Asic designAsic design
Asic designAksum Institute of Technology(AIT, @Letsgo)
 
Programmable Logic Devices Plds
Programmable Logic Devices PldsProgrammable Logic Devices Plds
Programmable Logic Devices PldsGaditek
 
fpga programming
fpga programmingfpga programming
fpga programmingAnish Gupta
 
Chapter 5 introduction to VHDL
Chapter 5 introduction to VHDLChapter 5 introduction to VHDL
Chapter 5 introduction to VHDLSSE_AndyLi
 
Programmable logic device (PLD)
Programmable logic device (PLD)Programmable logic device (PLD)
Programmable logic device (PLD)Sɐɐp ɐɥɯǝp
 
VLSI Design Flow
VLSI Design FlowVLSI Design Flow
VLSI Design FlowA B Shinde
 
Complex Programmable Logic Device (CPLD) Architecture and Its Applications
Complex Programmable Logic Device (CPLD) Architecture and Its ApplicationsComplex Programmable Logic Device (CPLD) Architecture and Its Applications
Complex Programmable Logic Device (CPLD) Architecture and Its Applicationselprocus
 
VHDL- data types
VHDL- data typesVHDL- data types
VHDL- data typesVandanaPagar1
 
Basics of digital verilog design(alok singh kanpur)
Basics of digital verilog design(alok singh kanpur)Basics of digital verilog design(alok singh kanpur)
Basics of digital verilog design(alok singh kanpur)Alok Singh
 
Shift Registers
Shift RegistersShift Registers
Shift RegistersAbhilash Nair
 
Fpga
FpgaFpga
Fpgabharadwajareddy
 

More Related Content

What's hot

VLSI Testing Techniques
VLSI Testing TechniquesVLSI Testing Techniques
VLSI Testing TechniquesA B Shinde
 
Verilog Tasks & Functions
Verilog Tasks & FunctionsVerilog Tasks & Functions
Verilog Tasks & Functionsanand hd
 
Introduction to FPGA, VHDL
Introduction to FPGA, VHDL Introduction to FPGA, VHDL
Introduction to FPGA, VHDL Amr Rashed
 
An Introductory course on Verilog HDL-Verilog hdl ppr
An Introductory course on Verilog HDL-Verilog hdl pprAn Introductory course on Verilog HDL-Verilog hdl ppr
An Introductory course on Verilog HDL-Verilog hdl pprPrabhavathi P
 
Complex Programmable Logic Devices(CPLD) & Field Programmable Logic Devices (...
Complex Programmable Logic Devices(CPLD) & Field Programmable Logic Devices (...Complex Programmable Logic Devices(CPLD) & Field Programmable Logic Devices (...
Complex Programmable Logic Devices(CPLD) & Field Programmable Logic Devices (...Revathi Subramaniam
 
Design and implementation of 32 bit alu using verilog
Design and implementation of 32 bit alu using verilogDesign and implementation of 32 bit alu using verilog
Design and implementation of 32 bit alu using verilogSTEPHEN MOIRANGTHEM
 
Pipelining approach
Pipelining approachPipelining approach
Pipelining approachGopinathD17
 
Programmable Logic Devices Plds
Programmable Logic Devices PldsProgrammable Logic Devices Plds
Programmable Logic Devices PldsGaditek
 
fpga programming
fpga programmingfpga programming
fpga programmingAnish Gupta
 
Chapter 5 introduction to VHDL
Chapter 5 introduction to VHDLChapter 5 introduction to VHDL
Chapter 5 introduction to VHDLSSE_AndyLi
 
Programmable logic device (PLD)
Programmable logic device (PLD)Programmable logic device (PLD)
Programmable logic device (PLD)Sɐɐp ɐɥɯǝp
 
VLSI Design Flow
VLSI Design FlowVLSI Design Flow
VLSI Design FlowA B Shinde
 
Complex Programmable Logic Device (CPLD) Architecture and Its Applications
Complex Programmable Logic Device (CPLD) Architecture and Its ApplicationsComplex Programmable Logic Device (CPLD) Architecture and Its Applications
Complex Programmable Logic Device (CPLD) Architecture and Its Applicationselprocus
 
Basics of digital verilog design(alok singh kanpur)
Basics of digital verilog design(alok singh kanpur)Basics of digital verilog design(alok singh kanpur)
Basics of digital verilog design(alok singh kanpur)Alok Singh
 

What's hot (20)

Verilog tutorial
Verilog tutorialVerilog tutorial
Verilog tutorial
 
Xilinx 4000 series
Xilinx 4000 seriesXilinx 4000 series
Xilinx 4000 series
 
VLSI Testing Techniques
VLSI Testing TechniquesVLSI Testing Techniques
VLSI Testing Techniques
 
Verilog Tasks & Functions
Verilog Tasks & FunctionsVerilog Tasks & Functions
Verilog Tasks & Functions
 
Introduction to FPGA, VHDL
Introduction to FPGA, VHDL Introduction to FPGA, VHDL
Introduction to FPGA, VHDL
 
FPGA
FPGAFPGA
FPGA
 
Embedded c
Embedded cEmbedded c
Embedded c
 
An Introductory course on Verilog HDL-Verilog hdl ppr
An Introductory course on Verilog HDL-Verilog hdl pprAn Introductory course on Verilog HDL-Verilog hdl ppr
An Introductory course on Verilog HDL-Verilog hdl ppr
 
Complex Programmable Logic Devices(CPLD) & Field Programmable Logic Devices (...
Complex Programmable Logic Devices(CPLD) & Field Programmable Logic Devices (...Complex Programmable Logic Devices(CPLD) & Field Programmable Logic Devices (...
Complex Programmable Logic Devices(CPLD) & Field Programmable Logic Devices (...
 
Design and implementation of 32 bit alu using verilog
Design and implementation of 32 bit alu using verilogDesign and implementation of 32 bit alu using verilog
Design and implementation of 32 bit alu using verilog
 
Pipelining approach
Pipelining approachPipelining approach
Pipelining approach
 
Asic design
Asic designAsic design
Asic design
 
Programmable Logic Devices Plds
Programmable Logic Devices PldsProgrammable Logic Devices Plds
Programmable Logic Devices Plds
 
fpga programming
fpga programmingfpga programming
fpga programming
 
Chapter 5 introduction to VHDL
Chapter 5 introduction to VHDLChapter 5 introduction to VHDL
Chapter 5 introduction to VHDL
 
Programmable logic device (PLD)
Programmable logic device (PLD)Programmable logic device (PLD)
Programmable logic device (PLD)
 
VLSI Design Flow
VLSI Design FlowVLSI Design Flow
VLSI Design Flow
 
Complex Programmable Logic Device (CPLD) Architecture and Its Applications
Complex Programmable Logic Device (CPLD) Architecture and Its ApplicationsComplex Programmable Logic Device (CPLD) Architecture and Its Applications
Complex Programmable Logic Device (CPLD) Architecture and Its Applications
 
VHDL- data types
VHDL- data typesVHDL- data types
VHDL- data types
 
Basics of digital verilog design(alok singh kanpur)
Basics of digital verilog design(alok singh kanpur)Basics of digital verilog design(alok singh kanpur)
Basics of digital verilog design(alok singh kanpur)
 

Viewers also liked

Dlc{binary to gray code conversion} ppt
Dlc{binary to gray code conversion} pptDlc{binary to gray code conversion} ppt
Dlc{binary to gray code conversion} pptTanish Gupta
 
Binary to grey code conversion
Binary to grey code conversionBinary to grey code conversion
Binary to grey code conversionSunny
 
BCD,GRAY and EXCESS 3 codes
BCD,GRAY and EXCESS 3 codesBCD,GRAY and EXCESS 3 codes
BCD,GRAY and EXCESS 3 codesstudent
 
Fundamentals of FPGA
Fundamentals of FPGAFundamentals of FPGA
Fundamentals of FPGAvelamakuri
 

Viewers also liked (11)

Shift Registers
Shift RegistersShift Registers
Shift Registers
 
Fpga
FpgaFpga
Fpga
 
Dlc{binary to gray code conversion} ppt
Dlc{binary to gray code conversion} pptDlc{binary to gray code conversion} ppt
Dlc{binary to gray code conversion} ppt
 
VHDL CODE
VHDL CODE VHDL CODE
VHDL CODE
 
23 gray codes
23 gray codes23 gray codes
23 gray codes
 
Binary to grey code conversion
Binary to grey code conversionBinary to grey code conversion
Binary to grey code conversion
 
Programs of VHDL
Programs of VHDLPrograms of VHDL
Programs of VHDL
 
BCD,GRAY and EXCESS 3 codes
BCD,GRAY and EXCESS 3 codesBCD,GRAY and EXCESS 3 codes
BCD,GRAY and EXCESS 3 codes
 
Counters
CountersCounters
Counters
 
FPGA
FPGAFPGA
FPGA
 
Fundamentals of FPGA
Fundamentals of FPGAFundamentals of FPGA
Fundamentals of FPGA
 

Similar to VHDL

Introduction to VHDL
Introduction to VHDLIntroduction to VHDL
Introduction to VHDLYaser Kalifa
 
Vhd lhigh2003
Vhd lhigh2003Vhd lhigh2003
Vhd lhigh2003gkumawat
 
VHDL-Behavioral-Programs-Structure of VHDL
VHDL-Behavioral-Programs-Structure of VHDLVHDL-Behavioral-Programs-Structure of VHDL
VHDL-Behavioral-Programs-Structure of VHDLRevathi Subramaniam
 
vlsi introduction to hdl and its typesunit-1.pptx
vlsi introduction to hdl and its typesunit-1.pptxvlsi introduction to hdl and its typesunit-1.pptx
vlsi introduction to hdl and its typesunit-1.pptxiconicyt2
 
Introduction to-vhdl
Introduction to-vhdlIntroduction to-vhdl
Introduction to-vhdlNeeraj Gupta
 
Basic Coding In VHDL COding
Basic Coding In VHDL COdingBasic Coding In VHDL COding
Basic Coding In VHDL COdinganna university
 
L6_Slides_vhdl coures temporary hair dye for dark hair
L6_Slides_vhdl coures temporary hair dye for dark hairL6_Slides_vhdl coures temporary hair dye for dark hair
L6_Slides_vhdl coures temporary hair dye for dark hairloyad20119
 
Seminar on Digital Multiplier(Booth Multiplier) Using VHDL
Seminar on Digital Multiplier(Booth Multiplier) Using VHDLSeminar on Digital Multiplier(Booth Multiplier) Using VHDL
Seminar on Digital Multiplier(Booth Multiplier) Using VHDLNaseer LoneRider
 
Hardware Description Language
Hardware Description Language Hardware Description Language
Hardware Description Language Prachi Pandey
 
Verilog presentation final
Verilog presentation finalVerilog presentation final
Verilog presentation finalAnkur Gupta
 

Similar to VHDL (20)

Introduction to VHDL
Introduction to VHDLIntroduction to VHDL
Introduction to VHDL
 
Hd6
Hd6Hd6
Hd6
 
Vhdl introduction
Vhdl introductionVhdl introduction
Vhdl introduction
 
Spdas2 vlsibput
Spdas2 vlsibputSpdas2 vlsibput
Spdas2 vlsibput
 
Vhd lhigh2003
Vhd lhigh2003Vhd lhigh2003
Vhd lhigh2003
 
Hd2
Hd2Hd2
Hd2
 
VHDL-Behavioral-Programs-Structure of VHDL
VHDL-Behavioral-Programs-Structure of VHDLVHDL-Behavioral-Programs-Structure of VHDL
VHDL-Behavioral-Programs-Structure of VHDL
 
verilog_tutorial1.pptx
verilog_tutorial1.pptxverilog_tutorial1.pptx
verilog_tutorial1.pptx
 
vlsi introduction to hdl and its typesunit-1.pptx
vlsi introduction to hdl and its typesunit-1.pptxvlsi introduction to hdl and its typesunit-1.pptx
vlsi introduction to hdl and its typesunit-1.pptx
 
DSD
DSDDSD
DSD
 
Introduction to-vhdl
Introduction to-vhdlIntroduction to-vhdl
Introduction to-vhdl
 
Basic Coding In VHDL COding
Basic Coding In VHDL COdingBasic Coding In VHDL COding
Basic Coding In VHDL COding
 
L6_Slides_vhdl coures temporary hair dye for dark hair
L6_Slides_vhdl coures temporary hair dye for dark hairL6_Slides_vhdl coures temporary hair dye for dark hair
L6_Slides_vhdl coures temporary hair dye for dark hair
 
Seminar on Digital Multiplier(Booth Multiplier) Using VHDL
Seminar on Digital Multiplier(Booth Multiplier) Using VHDLSeminar on Digital Multiplier(Booth Multiplier) Using VHDL
Seminar on Digital Multiplier(Booth Multiplier) Using VHDL
 
Hardware Description Language
Hardware Description Language Hardware Description Language
Hardware Description Language
 
ece223-vhdl-lab1-w07.ppt
ece223-vhdl-lab1-w07.pptece223-vhdl-lab1-w07.ppt
ece223-vhdl-lab1-w07.ppt
 
ece223-vhdl-lab1-w07.ppt
ece223-vhdl-lab1-w07.pptece223-vhdl-lab1-w07.ppt
ece223-vhdl-lab1-w07.ppt
 
vhdl
vhdlvhdl
vhdl
 
Dica ii chapter slides
Dica ii chapter slidesDica ii chapter slides
Dica ii chapter slides
 
Verilog presentation final
Verilog presentation finalVerilog presentation final
Verilog presentation final
 

More from Ramasubbu .P

Tractor Components
Tractor ComponentsTractor Components
Tractor ComponentsRamasubbu .P
 

More from Ramasubbu .P (20)

radar
radarradar
radar
 
Press
PressPress
Press
 
Milling 2
Milling 2Milling 2
Milling 2
 
MIlling 1
MIlling 1MIlling 1
MIlling 1
 
Drillings
DrillingsDrillings
Drillings
 
Holding
HoldingHolding
Holding
 
Saftey
SafteySaftey
Saftey
 
Harvesting
HarvestingHarvesting
Harvesting
 
Plough
PloughPlough
Plough
 
Tractor PTO
Tractor PTOTractor PTO
Tractor PTO
 
Tractor Components
Tractor ComponentsTractor Components
Tractor Components
 
MSAT
MSATMSAT
MSAT
 
GPS
GPSGPS
GPS
 
RTOS
RTOSRTOS
RTOS
 
Virus
VirusVirus
Virus
 
Hacker
HackerHacker
Hacker
 
Denail of Service
Denail of ServiceDenail of Service
Denail of Service
 
RAID CONCEPT
RAID CONCEPTRAID CONCEPT
RAID CONCEPT
 
Network Security
Network SecurityNetwork Security
Network Security
 
Timer
TimerTimer
Timer
 

Recently uploaded

Measures of Dispersion and Variability: Range, QD, AD and SD
Measures of Dispersion and Variability: Range, QD, AD and SDMeasures of Dispersion and Variability: Range, QD, AD and SD
Measures of Dispersion and Variability: Range, QD, AD and SDThiyagu K
 
Z Score,T Score, Percential Rank and Box Plot Graph
Z Score,T Score, Percential Rank and Box Plot GraphZ Score,T Score, Percential Rank and Box Plot Graph
Z Score,T Score, Percential Rank and Box Plot GraphThiyagu K
 
Mixin Classes in Odoo 17 How to Extend Models Using Mixin Classes
Mixin Classes in Odoo 17 How to Extend Models Using Mixin ClassesMixin Classes in Odoo 17 How to Extend Models Using Mixin Classes
Mixin Classes in Odoo 17 How to Extend Models Using Mixin ClassesCeline George
 
Beyond the EU: DORA and NIS 2 Directive's Global Impact
Beyond the EU: DORA and NIS 2 Directive's Global ImpactBeyond the EU: DORA and NIS 2 Directive's Global Impact
Beyond the EU: DORA and NIS 2 Directive's Global ImpactPECB
 
Advanced Views - Calendar View in Odoo 17
Advanced Views - Calendar View in Odoo 17Advanced Views - Calendar View in Odoo 17
Advanced Views - Calendar View in Odoo 17Celine George
 
Accessible design: Minimum effort, maximum impact
Accessible design: Minimum effort, maximum impactAccessible design: Minimum effort, maximum impact
Accessible design: Minimum effort, maximum impactdawncurless
 
SECOND SEMESTER TOPIC COVERAGE SY 2023-2024 Trends, Networks, and Critical Th...
SECOND SEMESTER TOPIC COVERAGE SY 2023-2024 Trends, Networks, and Critical Th...SECOND SEMESTER TOPIC COVERAGE SY 2023-2024 Trends, Networks, and Critical Th...
SECOND SEMESTER TOPIC COVERAGE SY 2023-2024 Trends, Networks, and Critical Th...KokoStevan
 
ICT Role in 21st Century Education & its Challenges.pptx
ICT Role in 21st Century Education & its Challenges.pptxICT Role in 21st Century Education & its Challenges.pptx
ICT Role in 21st Century Education & its Challenges.pptxAreebaZafar22
 
An Overview of Mutual Funds Bcom Project.pdf
An Overview of Mutual Funds Bcom Project.pdfAn Overview of Mutual Funds Bcom Project.pdf
An Overview of Mutual Funds Bcom Project.pdfSanaAli374401
 
microwave assisted reaction. General introduction
microwave assisted reaction. General introductionmicrowave assisted reaction. General introduction
microwave assisted reaction. General introductionMaksud Ahmed
 
Introduction to Nonprofit Accounting: The Basics
Introduction to Nonprofit Accounting: The BasicsIntroduction to Nonprofit Accounting: The Basics
Introduction to Nonprofit Accounting: The BasicsTechSoup
 
Activity 01 - Artificial Culture (1).pdf
Activity 01 - Artificial Culture (1).pdfActivity 01 - Artificial Culture (1).pdf
Activity 01 - Artificial Culture (1).pdfciinovamais
 
How to Give a Domain for a Field in Odoo 17
How to Give a Domain for a Field in Odoo 17How to Give a Domain for a Field in Odoo 17
How to Give a Domain for a Field in Odoo 17Celine George
 
Key note speaker Neum_Admir Softic_ENG.pdf
Key note speaker Neum_Admir Softic_ENG.pdfKey note speaker Neum_Admir Softic_ENG.pdf
Key note speaker Neum_Admir Softic_ENG.pdfAdmir Softic
 
Ecological Succession. ( ECOSYSTEM, B. Pharmacy, 1st Year, Sem-II, Environmen...
Ecological Succession. ( ECOSYSTEM, B. Pharmacy, 1st Year, Sem-II, Environmen...Ecological Succession. ( ECOSYSTEM, B. Pharmacy, 1st Year, Sem-II, Environmen...
Ecological Succession. ( ECOSYSTEM, B. Pharmacy, 1st Year, Sem-II, Environmen...Shubhangi Sonawane
 
Sports & Fitness Value Added Course FY..
Sports & Fitness Value Added Course FY..Sports & Fitness Value Added Course FY..
Sports & Fitness Value Added Course FY..Disha Kariya
 
APM Welcome, APM North West Network Conference, Synergies Across Sectors
APM Welcome, APM North West Network Conference, Synergies Across SectorsAPM Welcome, APM North West Network Conference, Synergies Across Sectors
APM Welcome, APM North West Network Conference, Synergies Across SectorsAssociation for Project Management
 

Recently uploaded (20)

Measures of Dispersion and Variability: Range, QD, AD and SD
Measures of Dispersion and Variability: Range, QD, AD and SDMeasures of Dispersion and Variability: Range, QD, AD and SD
Measures of Dispersion and Variability: Range, QD, AD and SD
 
Z Score,T Score, Percential Rank and Box Plot Graph
Z Score,T Score, Percential Rank and Box Plot GraphZ Score,T Score, Percential Rank and Box Plot Graph
Z Score,T Score, Percential Rank and Box Plot Graph
 
Mixin Classes in Odoo 17 How to Extend Models Using Mixin Classes
Mixin Classes in Odoo 17 How to Extend Models Using Mixin ClassesMixin Classes in Odoo 17 How to Extend Models Using Mixin Classes
Mixin Classes in Odoo 17 How to Extend Models Using Mixin Classes
 
Beyond the EU: DORA and NIS 2 Directive's Global Impact
Beyond the EU: DORA and NIS 2 Directive's Global ImpactBeyond the EU: DORA and NIS 2 Directive's Global Impact
Beyond the EU: DORA and NIS 2 Directive's Global Impact
 
Advanced Views - Calendar View in Odoo 17
Advanced Views - Calendar View in Odoo 17Advanced Views - Calendar View in Odoo 17
Advanced Views - Calendar View in Odoo 17
 
Accessible design: Minimum effort, maximum impact
Accessible design: Minimum effort, maximum impactAccessible design: Minimum effort, maximum impact
Accessible design: Minimum effort, maximum impact
 
SECOND SEMESTER TOPIC COVERAGE SY 2023-2024 Trends, Networks, and Critical Th...
SECOND SEMESTER TOPIC COVERAGE SY 2023-2024 Trends, Networks, and Critical Th...SECOND SEMESTER TOPIC COVERAGE SY 2023-2024 Trends, Networks, and Critical Th...
SECOND SEMESTER TOPIC COVERAGE SY 2023-2024 Trends, Networks, and Critical Th...
 
ICT Role in 21st Century Education & its Challenges.pptx
ICT Role in 21st Century Education & its Challenges.pptxICT Role in 21st Century Education & its Challenges.pptx
ICT Role in 21st Century Education & its Challenges.pptx
 
An Overview of Mutual Funds Bcom Project.pdf
An Overview of Mutual Funds Bcom Project.pdfAn Overview of Mutual Funds Bcom Project.pdf
An Overview of Mutual Funds Bcom Project.pdf
 
Código Creativo y Arte de Software | Unidad 1
Código Creativo y Arte de Software | Unidad 1Código Creativo y Arte de Software | Unidad 1
Código Creativo y Arte de Software | Unidad 1
 
microwave assisted reaction. General introduction
microwave assisted reaction. General introductionmicrowave assisted reaction. General introduction
microwave assisted reaction. General introduction
 
Introduction to Nonprofit Accounting: The Basics
Introduction to Nonprofit Accounting: The BasicsIntroduction to Nonprofit Accounting: The Basics
Introduction to Nonprofit Accounting: The Basics
 
Activity 01 - Artificial Culture (1).pdf
Activity 01 - Artificial Culture (1).pdfActivity 01 - Artificial Culture (1).pdf
Activity 01 - Artificial Culture (1).pdf
 
How to Give a Domain for a Field in Odoo 17
How to Give a Domain for a Field in Odoo 17How to Give a Domain for a Field in Odoo 17
How to Give a Domain for a Field in Odoo 17
 
Key note speaker Neum_Admir Softic_ENG.pdf
Key note speaker Neum_Admir Softic_ENG.pdfKey note speaker Neum_Admir Softic_ENG.pdf
Key note speaker Neum_Admir Softic_ENG.pdf
 
Mattingly "AI & Prompt Design: Structured Data, Assistants, & RAG"
Mattingly "AI & Prompt Design: Structured Data, Assistants, & RAG"Mattingly "AI & Prompt Design: Structured Data, Assistants, & RAG"
Mattingly "AI & Prompt Design: Structured Data, Assistants, & RAG"
 
Ecological Succession. ( ECOSYSTEM, B. Pharmacy, 1st Year, Sem-II, Environmen...
Ecological Succession. ( ECOSYSTEM, B. Pharmacy, 1st Year, Sem-II, Environmen...Ecological Succession. ( ECOSYSTEM, B. Pharmacy, 1st Year, Sem-II, Environmen...
Ecological Succession. ( ECOSYSTEM, B. Pharmacy, 1st Year, Sem-II, Environmen...
 
Advance Mobile Application Development class 07
Advance Mobile Application Development class 07Advance Mobile Application Development class 07
Advance Mobile Application Development class 07
 
Sports & Fitness Value Added Course FY..
Sports & Fitness Value Added Course FY..Sports & Fitness Value Added Course FY..
Sports & Fitness Value Added Course FY..
 
APM Welcome, APM North West Network Conference, Synergies Across Sectors
APM Welcome, APM North West Network Conference, Synergies Across SectorsAPM Welcome, APM North West Network Conference, Synergies Across Sectors
APM Welcome, APM North West Network Conference, Synergies Across Sectors
 

VHDL

  • 1. Introduction to VHDL M. Balakrishnan Dept of Computer Science & Engg. I.I.T. Delhi
  • 2. Domains of Description : Gajski’s Y-Chart Behavioral domain Structural domain Physical domain Level of abstraction VHDL models
  • 3.
  • 4.
  • 5.
  • 6.
  • 7. VHDL Example a b c AND
  • 8.
  • 9. Concurrency in VHDL Descriptions signals process 1 process 2 process n signals
  • 10.
  • 12. Modeling Styles in VHDL M. Balakrishnan Dept. of Comp. Sci. & Engg. I.I.T. Delhi
  • 13.
  • 14.
  • 15.
  • 16.
  • 17.
  • 18.
  • 19.
  • 20.
  • 21.
  • 22.
  • 23.
  • 24.
  • 25.
  • 26. Behavioral Description in VHDL M. Balakrishnan Dept. of Comp. Sci. & Engg. I.I.T. Delhi
  • 27.
  • 28.
  • 29.
  • 30.
  • 31.
  • 32. CASE Statement: 4 to 1 Multiplexer Case sel is when 0 => y <= x0 when 1 => y <= x1 when 2 => y <= x2 when 3 => y <= x3 end case x0 x1 x2 x3 y
  • 33.
  • 34.