SlideShare uma empresa Scribd logo
1 de 16
DIGITAL LOGIC CIRCUITS
~ INTRODUCTION TO COMBINATIONAL AND
SEQUENTIAL CIRCUITS.
~DESIGN PROCEDURE OF COMBINATIONAL
CIRCUITS
~ANALYSIS PROCEDURE OF COMBINATIONAL
CIRCUITS
PRESENTED BY:
QURATULAIN
BS(CS)-1
QUAID-E-AZAM UNIVERSITY
ISLAMABAD ,PAKISTAN.
TYPES OF DIGITAL LOGIC
CIRCUITS
 COMBINATIONAL CIRCUITS
 SEQUENTIAL CIRCUITS
COMBINATIONAL CIRCUITS
 Combinational Circuits are made of logic
gates.
 Doesn’t contain memory element , that’s
why they cant store any information.
 Value of present output is determined by
present input.
 Examples of combinational circuits are
half adders, full adders, sub tractors etc.
BLOCK DIAGRAM OF A
COMBINATIONAL CIRCUIT
SEQUENTIAL LOGIC CIRCUITS
 Made up of combinational circuits and
memory elements.
 These memory elements are devices
capable of storing ONE-BIT information.
 Output depend on input and previous
state.
 Examples of sequential circuits are flip
flops, counters, shift registers
BLOCK DIAGRAM OF A
SEQUENTIAL CIRCUIT
TYPES OF SEQUENTIAL
CIRCUITS
Sequential circuits are of two types:
1.SYNCHRONOUS CIRCUITS:
 In synchronous sequential circuits, the state
of the device changes only at discrete times
in response to a clock Pulse.
2.ASYNCHRONOUS CIRCUITS:
 Asynchronous circuit is not synchronized by
a clock signal; the outputs of the circuit
change directly in response to changes in
Inputs.
DESIGN PROCEDURE OF
COMBINATIONAL CIRCUITS
This procedure involves the following
steps:
 The problem is stated.
 The number of available input
variables and output variables is
determined.
 The input and output variables are
assigned letter symbols.
 Truth table is drawn
 Boolean function for output is obtained.
ANALYSIS PROCEDURE OF
COMBINATIONAL CIRCUIT
 TO DETERMINE THE OUTPUT FUNCTIONS
AS ALGEBRAIC EXPRESSIONS.
 It is the reverse process of design procedure.
 Logic diagram of the circuit is given.
 Obtain the truth table from the diagram.
 Obtain Boolean function from the Truth Table
for output.
LOGIC DIAGRAM FOR
ANALYSIS EXAMPLE:
THE CIRCUIT HAS THREE
INPUTS, A,B,C
AND TWO OUTPUTS F1 AND F2
 The Boolean function for outputs are:
F2=AB+AC+BC
T1=A+B+C
T2=ABC
 Outputs functions for gates are :
T3=F2’T1
F1=T3+T2
Substituting and simplifying, we get :
TRUTH TABLE DRAWN FROM
THE LOGIC DIAGRAM.
BOOLEAN FUNCTIONS
OBTAINED FOR OUTPUT ARE :
 F2=AB+AC+BC
 F1=A’BC’+A’B’C+AB’C’+ABC
SEQUENTIAL AND COMBINATIONAL CIRCUITS,DIGITAL LOGIC DESIGN

Mais conteúdo relacionado

Mais procurados

Clock divider by 3
Clock divider by 3Clock divider by 3
Clock divider by 3Ashok Reddy
 
Sequential Logic Circuit
Sequential Logic CircuitSequential Logic Circuit
Sequential Logic CircuitRamasubbu .P
 
sequential circuits
sequential circuitssequential circuits
sequential circuitsUnsa Shakir
 
Adder substracter
Adder substracterAdder substracter
Adder substracterWanNurdiana
 
Combinational circuits
Combinational circuitsCombinational circuits
Combinational circuitsSARITHA REDDY
 
Sequential circuit design
Sequential circuit designSequential circuit design
Sequential circuit designSatya P. Joshi
 
Flip flop conversions
Flip flop conversionsFlip flop conversions
Flip flop conversionsuma jangaman
 
Half Adder and Full Adder
Half Adder and Full AdderHalf Adder and Full Adder
Half Adder and Full AdderShayshab Azad
 
Latches and flip flop
Latches and flip flopLatches and flip flop
Latches and flip flopShuaib Hotak
 
Introduction to digital logic
Introduction to digital logicIntroduction to digital logic
Introduction to digital logicKamal Acharya
 
Half Subtractor.pptx
Half Subtractor.pptxHalf Subtractor.pptx
Half Subtractor.pptxPooja Dixit
 
Magnitude comparator
Magnitude comparatorMagnitude comparator
Magnitude comparatorSyed Saeed
 
Verilog HDL Training Course
Verilog HDL Training CourseVerilog HDL Training Course
Verilog HDL Training CoursePaul Laskowski
 

Mais procurados (20)

Clock divider by 3
Clock divider by 3Clock divider by 3
Clock divider by 3
 
Chapter 4: Combinational Logic
Chapter 4: Combinational LogicChapter 4: Combinational Logic
Chapter 4: Combinational Logic
 
Sequential Logic Circuit
Sequential Logic CircuitSequential Logic Circuit
Sequential Logic Circuit
 
sequential circuits
sequential circuitssequential circuits
sequential circuits
 
Adder substracter
Adder substracterAdder substracter
Adder substracter
 
Counters
CountersCounters
Counters
 
Combinational circuits
Combinational circuitsCombinational circuits
Combinational circuits
 
Sequential circuit design
Sequential circuit designSequential circuit design
Sequential circuit design
 
Flip flop conversions
Flip flop conversionsFlip flop conversions
Flip flop conversions
 
Half Adder and Full Adder
Half Adder and Full AdderHalf Adder and Full Adder
Half Adder and Full Adder
 
Latches and flip flop
Latches and flip flopLatches and flip flop
Latches and flip flop
 
Introduction to digital logic
Introduction to digital logicIntroduction to digital logic
Introduction to digital logic
 
Half Subtractor.pptx
Half Subtractor.pptxHalf Subtractor.pptx
Half Subtractor.pptx
 
Unit 4-booth algorithm
Unit 4-booth algorithmUnit 4-booth algorithm
Unit 4-booth algorithm
 
Flip flop
Flip flopFlip flop
Flip flop
 
De lab manual
De lab manualDe lab manual
De lab manual
 
Sequential circuits
Sequential circuitsSequential circuits
Sequential circuits
 
Magnitude comparator
Magnitude comparatorMagnitude comparator
Magnitude comparator
 
Verilog HDL Training Course
Verilog HDL Training CourseVerilog HDL Training Course
Verilog HDL Training Course
 
Flip flop
Flip flop Flip flop
Flip flop
 

Destaque

Sequential circuits in digital logic design
Sequential circuits in digital logic designSequential circuits in digital logic design
Sequential circuits in digital logic designNallapati Anindra
 
Difference between combinational and
Difference between combinational andDifference between combinational and
Difference between combinational andDamodar Panigrahy
 
Encoders and Decoders
Encoders and DecodersEncoders and Decoders
Encoders and DecodersNic JM
 
Sequential Circuits - Flip Flops (Part 2)
Sequential Circuits - Flip Flops (Part 2)Sequential Circuits - Flip Flops (Part 2)
Sequential Circuits - Flip Flops (Part 2)Abhilash Nair
 
Digital logic circuits important question and answers for 5 units
Digital logic circuits important question and answers for 5 unitsDigital logic circuits important question and answers for 5 units
Digital logic circuits important question and answers for 5 unitsLekashri Subramanian
 
Sequential and combinational alu
Sequential and combinational alu Sequential and combinational alu
Sequential and combinational alu Piyush Rochwani
 
1 Multiplexer
1 Multiplexer1 Multiplexer
1 Multiplexerna491
 
COMBINATIONAL CIRCUITS & FLIP FLOPS
COMBINATIONAL CIRCUITS & FLIP FLOPSCOMBINATIONAL CIRCUITS & FLIP FLOPS
COMBINATIONAL CIRCUITS & FLIP FLOPSStarlee Lathong
 
Encoders and decoders
Encoders and decodersEncoders and decoders
Encoders and decodersGaditek
 
Logic gates - AND, OR, NOT, NOR, NAND, XOR, XNOR Gates.
Logic gates - AND, OR, NOT, NOR, NAND, XOR, XNOR Gates.Logic gates - AND, OR, NOT, NOR, NAND, XOR, XNOR Gates.
Logic gates - AND, OR, NOT, NOR, NAND, XOR, XNOR Gates.Satya P. Joshi
 
simplification of boolean algebra
simplification of boolean algebrasimplification of boolean algebra
simplification of boolean algebramayannpolisticoLNU
 

Destaque (20)

Sequential circuits in digital logic design
Sequential circuits in digital logic designSequential circuits in digital logic design
Sequential circuits in digital logic design
 
Digital 1 8
Digital 1 8Digital 1 8
Digital 1 8
 
Difference between combinational and
Difference between combinational andDifference between combinational and
Difference between combinational and
 
Encoder and decoder
Encoder and decoderEncoder and decoder
Encoder and decoder
 
Encoders and Decoders
Encoders and DecodersEncoders and Decoders
Encoders and Decoders
 
Sequential Circuits - Flip Flops (Part 2)
Sequential Circuits - Flip Flops (Part 2)Sequential Circuits - Flip Flops (Part 2)
Sequential Circuits - Flip Flops (Part 2)
 
Multiplexers & Demultiplexers
Multiplexers & DemultiplexersMultiplexers & Demultiplexers
Multiplexers & Demultiplexers
 
Digital logic circuits important question and answers for 5 units
Digital logic circuits important question and answers for 5 unitsDigital logic circuits important question and answers for 5 units
Digital logic circuits important question and answers for 5 units
 
Sequential and combinational alu
Sequential and combinational alu Sequential and combinational alu
Sequential and combinational alu
 
1 Multiplexer
1 Multiplexer1 Multiplexer
1 Multiplexer
 
Multiplexer
MultiplexerMultiplexer
Multiplexer
 
COMBINATIONAL CIRCUITS & FLIP FLOPS
COMBINATIONAL CIRCUITS & FLIP FLOPSCOMBINATIONAL CIRCUITS & FLIP FLOPS
COMBINATIONAL CIRCUITS & FLIP FLOPS
 
Basics of K map
Basics of K mapBasics of K map
Basics of K map
 
K - Map
  K - Map    K - Map
K - Map
 
Encoders and decoders
Encoders and decodersEncoders and decoders
Encoders and decoders
 
Encoder
EncoderEncoder
Encoder
 
K map
K mapK map
K map
 
Flipflop
FlipflopFlipflop
Flipflop
 
Logic gates - AND, OR, NOT, NOR, NAND, XOR, XNOR Gates.
Logic gates - AND, OR, NOT, NOR, NAND, XOR, XNOR Gates.Logic gates - AND, OR, NOT, NOR, NAND, XOR, XNOR Gates.
Logic gates - AND, OR, NOT, NOR, NAND, XOR, XNOR Gates.
 
simplification of boolean algebra
simplification of boolean algebrasimplification of boolean algebra
simplification of boolean algebra
 

Semelhante a SEQUENTIAL AND COMBINATIONAL CIRCUITS,DIGITAL LOGIC DESIGN

Combinational circuits
Combinational circuitsCombinational circuits
Combinational circuitsmarangburu42
 
Combinational circuits
Combinational circuitsCombinational circuits
Combinational circuitsmarangburu42
 
Ieee project reversible logic gates by_amit
Ieee project reversible logic gates  by_amitIeee project reversible logic gates  by_amit
Ieee project reversible logic gates by_amitAmith Bhonsle
 
Ieee project reversible logic gates by_amit
Ieee project reversible logic gates  by_amitIeee project reversible logic gates  by_amit
Ieee project reversible logic gates by_amitAmith Bhonsle
 
Combinational circuit
Combinational circuitCombinational circuit
Combinational circuitchauhankapil
 
Binary parallel adder, decimal adder
Binary parallel adder, decimal adderBinary parallel adder, decimal adder
Binary parallel adder, decimal addershahzad ali
 
Digital Electronics (EC8392) UNIT-II -PPT-S.SESHA VIDHYA/ ASP/ECE
Digital Electronics (EC8392) UNIT-II -PPT-S.SESHA VIDHYA/ ASP/ECEDigital Electronics (EC8392) UNIT-II -PPT-S.SESHA VIDHYA/ ASP/ECE
Digital Electronics (EC8392) UNIT-II -PPT-S.SESHA VIDHYA/ ASP/ECESeshaVidhyaS
 
Implementation of Reversable Logic Based Design using Submicron Technology
Implementation of Reversable Logic Based Design using Submicron TechnologyImplementation of Reversable Logic Based Design using Submicron Technology
Implementation of Reversable Logic Based Design using Submicron TechnologySai Viswanath
 
Digital Principles and system design Combination Circuits
Digital Principles and system design Combination CircuitsDigital Principles and system design Combination Circuits
Digital Principles and system design Combination Circuitsssuserf49c5a
 
DLD Lecture No 18 Analysis and Design of Combinational Circuit.pptx
DLD Lecture No 18 Analysis and Design of Combinational Circuit.pptxDLD Lecture No 18 Analysis and Design of Combinational Circuit.pptx
DLD Lecture No 18 Analysis and Design of Combinational Circuit.pptxSaveraAyub2
 
Digital electronics lab
Digital electronics labDigital electronics lab
Digital electronics labswatymanoja
 
Introduction of Combinational logic circuits & half adder
Introduction of Combinational logic circuits & half adderIntroduction of Combinational logic circuits & half adder
Introduction of Combinational logic circuits & half adderhymalakshmitirumani
 
Programmable Logic Array(PLA), digital circuits
Programmable Logic Array(PLA), digital circuits Programmable Logic Array(PLA), digital circuits
Programmable Logic Array(PLA), digital circuits warda aziz
 
An Explicit Cell-Based Nesting Robust Architecture and Analysis of Full Adder
An Explicit Cell-Based Nesting Robust Architecture and Analysis of Full AdderAn Explicit Cell-Based Nesting Robust Architecture and Analysis of Full Adder
An Explicit Cell-Based Nesting Robust Architecture and Analysis of Full AdderVIT-AP University
 
LCE-UNIT 2 PPT.pdf
LCE-UNIT 2 PPT.pdfLCE-UNIT 2 PPT.pdf
LCE-UNIT 2 PPT.pdfHODECE21
 
2 marks DPCO.pdf
2 marks DPCO.pdf2 marks DPCO.pdf
2 marks DPCO.pdfVhhvf
 
Design and Implementation of Low Power 16-bit Carry-lookahead Adder using Adi...
Design and Implementation of Low Power 16-bit Carry-lookahead Adder using Adi...Design and Implementation of Low Power 16-bit Carry-lookahead Adder using Adi...
Design and Implementation of Low Power 16-bit Carry-lookahead Adder using Adi...IRJET Journal
 
Digital Electronics – Unit IV.pdf
Digital Electronics – Unit IV.pdfDigital Electronics – Unit IV.pdf
Digital Electronics – Unit IV.pdfKannan Kanagaraj
 

Semelhante a SEQUENTIAL AND COMBINATIONAL CIRCUITS,DIGITAL LOGIC DESIGN (20)

Combinational circuits
Combinational circuitsCombinational circuits
Combinational circuits
 
Combinational circuits
Combinational circuitsCombinational circuits
Combinational circuits
 
Ieee project reversible logic gates by_amit
Ieee project reversible logic gates  by_amitIeee project reversible logic gates  by_amit
Ieee project reversible logic gates by_amit
 
Ieee project reversible logic gates by_amit
Ieee project reversible logic gates  by_amitIeee project reversible logic gates  by_amit
Ieee project reversible logic gates by_amit
 
Combinational circuit
Combinational circuitCombinational circuit
Combinational circuit
 
Binary parallel adder, decimal adder
Binary parallel adder, decimal adderBinary parallel adder, decimal adder
Binary parallel adder, decimal adder
 
Digital Electronics (EC8392) UNIT-II -PPT-S.SESHA VIDHYA/ ASP/ECE
Digital Electronics (EC8392) UNIT-II -PPT-S.SESHA VIDHYA/ ASP/ECEDigital Electronics (EC8392) UNIT-II -PPT-S.SESHA VIDHYA/ ASP/ECE
Digital Electronics (EC8392) UNIT-II -PPT-S.SESHA VIDHYA/ ASP/ECE
 
Implementation of Reversable Logic Based Design using Submicron Technology
Implementation of Reversable Logic Based Design using Submicron TechnologyImplementation of Reversable Logic Based Design using Submicron Technology
Implementation of Reversable Logic Based Design using Submicron Technology
 
Combinational circuit
Combinational circuitCombinational circuit
Combinational circuit
 
Digital Principles and system design Combination Circuits
Digital Principles and system design Combination CircuitsDigital Principles and system design Combination Circuits
Digital Principles and system design Combination Circuits
 
DLD Lecture No 18 Analysis and Design of Combinational Circuit.pptx
DLD Lecture No 18 Analysis and Design of Combinational Circuit.pptxDLD Lecture No 18 Analysis and Design of Combinational Circuit.pptx
DLD Lecture No 18 Analysis and Design of Combinational Circuit.pptx
 
Digital electronics lab
Digital electronics labDigital electronics lab
Digital electronics lab
 
Introduction of Combinational logic circuits & half adder
Introduction of Combinational logic circuits & half adderIntroduction of Combinational logic circuits & half adder
Introduction of Combinational logic circuits & half adder
 
Programmable Logic Array(PLA), digital circuits
Programmable Logic Array(PLA), digital circuits Programmable Logic Array(PLA), digital circuits
Programmable Logic Array(PLA), digital circuits
 
Lesson Week 1-2.pptx
Lesson Week 1-2.pptxLesson Week 1-2.pptx
Lesson Week 1-2.pptx
 
An Explicit Cell-Based Nesting Robust Architecture and Analysis of Full Adder
An Explicit Cell-Based Nesting Robust Architecture and Analysis of Full AdderAn Explicit Cell-Based Nesting Robust Architecture and Analysis of Full Adder
An Explicit Cell-Based Nesting Robust Architecture and Analysis of Full Adder
 
LCE-UNIT 2 PPT.pdf
LCE-UNIT 2 PPT.pdfLCE-UNIT 2 PPT.pdf
LCE-UNIT 2 PPT.pdf
 
2 marks DPCO.pdf
2 marks DPCO.pdf2 marks DPCO.pdf
2 marks DPCO.pdf
 
Design and Implementation of Low Power 16-bit Carry-lookahead Adder using Adi...
Design and Implementation of Low Power 16-bit Carry-lookahead Adder using Adi...Design and Implementation of Low Power 16-bit Carry-lookahead Adder using Adi...
Design and Implementation of Low Power 16-bit Carry-lookahead Adder using Adi...
 
Digital Electronics – Unit IV.pdf
Digital Electronics – Unit IV.pdfDigital Electronics – Unit IV.pdf
Digital Electronics – Unit IV.pdf
 

Último

Boost Fertility New Invention Ups Success Rates.pdf
Boost Fertility New Invention Ups Success Rates.pdfBoost Fertility New Invention Ups Success Rates.pdf
Boost Fertility New Invention Ups Success Rates.pdfsudhanshuwaghmare1
 
A Call to Action for Generative AI in 2024
A Call to Action for Generative AI in 2024A Call to Action for Generative AI in 2024
A Call to Action for Generative AI in 2024Results
 
Exploring the Future Potential of AI-Enabled Smartphone Processors
Exploring the Future Potential of AI-Enabled Smartphone ProcessorsExploring the Future Potential of AI-Enabled Smartphone Processors
Exploring the Future Potential of AI-Enabled Smartphone Processorsdebabhi2
 
Driving Behavioral Change for Information Management through Data-Driven Gree...
Driving Behavioral Change for Information Management through Data-Driven Gree...Driving Behavioral Change for Information Management through Data-Driven Gree...
Driving Behavioral Change for Information Management through Data-Driven Gree...Enterprise Knowledge
 
How to convert PDF to text with Nanonets
How to convert PDF to text with NanonetsHow to convert PDF to text with Nanonets
How to convert PDF to text with Nanonetsnaman860154
 
Artificial Intelligence: Facts and Myths
Artificial Intelligence: Facts and MythsArtificial Intelligence: Facts and Myths
Artificial Intelligence: Facts and MythsJoaquim Jorge
 
What Are The Drone Anti-jamming Systems Technology?
What Are The Drone Anti-jamming Systems Technology?What Are The Drone Anti-jamming Systems Technology?
What Are The Drone Anti-jamming Systems Technology?Antenna Manufacturer Coco
 
Scaling API-first – The story of a global engineering organization
Scaling API-first – The story of a global engineering organizationScaling API-first – The story of a global engineering organization
Scaling API-first – The story of a global engineering organizationRadu Cotescu
 
Boost PC performance: How more available memory can improve productivity
Boost PC performance: How more available memory can improve productivityBoost PC performance: How more available memory can improve productivity
Boost PC performance: How more available memory can improve productivityPrincipled Technologies
 
Histor y of HAM Radio presentation slide
Histor y of HAM Radio presentation slideHistor y of HAM Radio presentation slide
Histor y of HAM Radio presentation slidevu2urc
 
Advantages of Hiring UIUX Design Service Providers for Your Business
Advantages of Hiring UIUX Design Service Providers for Your BusinessAdvantages of Hiring UIUX Design Service Providers for Your Business
Advantages of Hiring UIUX Design Service Providers for Your BusinessPixlogix Infotech
 
TrustArc Webinar - Stay Ahead of US State Data Privacy Law Developments
TrustArc Webinar - Stay Ahead of US State Data Privacy Law DevelopmentsTrustArc Webinar - Stay Ahead of US State Data Privacy Law Developments
TrustArc Webinar - Stay Ahead of US State Data Privacy Law DevelopmentsTrustArc
 
GenCyber Cyber Security Day Presentation
GenCyber Cyber Security Day PresentationGenCyber Cyber Security Day Presentation
GenCyber Cyber Security Day PresentationMichael W. Hawkins
 
Handwritten Text Recognition for manuscripts and early printed texts
Handwritten Text Recognition for manuscripts and early printed textsHandwritten Text Recognition for manuscripts and early printed texts
Handwritten Text Recognition for manuscripts and early printed textsMaria Levchenko
 
08448380779 Call Girls In Greater Kailash - I Women Seeking Men
08448380779 Call Girls In Greater Kailash - I Women Seeking Men08448380779 Call Girls In Greater Kailash - I Women Seeking Men
08448380779 Call Girls In Greater Kailash - I Women Seeking MenDelhi Call girls
 
IAC 2024 - IA Fast Track to Search Focused AI Solutions
IAC 2024 - IA Fast Track to Search Focused AI SolutionsIAC 2024 - IA Fast Track to Search Focused AI Solutions
IAC 2024 - IA Fast Track to Search Focused AI SolutionsEnterprise Knowledge
 
Mastering MySQL Database Architecture: Deep Dive into MySQL Shell and MySQL R...
Mastering MySQL Database Architecture: Deep Dive into MySQL Shell and MySQL R...Mastering MySQL Database Architecture: Deep Dive into MySQL Shell and MySQL R...
Mastering MySQL Database Architecture: Deep Dive into MySQL Shell and MySQL R...Miguel Araújo
 
08448380779 Call Girls In Civil Lines Women Seeking Men
08448380779 Call Girls In Civil Lines Women Seeking Men08448380779 Call Girls In Civil Lines Women Seeking Men
08448380779 Call Girls In Civil Lines Women Seeking MenDelhi Call girls
 
From Event to Action: Accelerate Your Decision Making with Real-Time Automation
From Event to Action: Accelerate Your Decision Making with Real-Time AutomationFrom Event to Action: Accelerate Your Decision Making with Real-Time Automation
From Event to Action: Accelerate Your Decision Making with Real-Time AutomationSafe Software
 
Breaking the Kubernetes Kill Chain: Host Path Mount
Breaking the Kubernetes Kill Chain: Host Path MountBreaking the Kubernetes Kill Chain: Host Path Mount
Breaking the Kubernetes Kill Chain: Host Path MountPuma Security, LLC
 

Último (20)

Boost Fertility New Invention Ups Success Rates.pdf
Boost Fertility New Invention Ups Success Rates.pdfBoost Fertility New Invention Ups Success Rates.pdf
Boost Fertility New Invention Ups Success Rates.pdf
 
A Call to Action for Generative AI in 2024
A Call to Action for Generative AI in 2024A Call to Action for Generative AI in 2024
A Call to Action for Generative AI in 2024
 
Exploring the Future Potential of AI-Enabled Smartphone Processors
Exploring the Future Potential of AI-Enabled Smartphone ProcessorsExploring the Future Potential of AI-Enabled Smartphone Processors
Exploring the Future Potential of AI-Enabled Smartphone Processors
 
Driving Behavioral Change for Information Management through Data-Driven Gree...
Driving Behavioral Change for Information Management through Data-Driven Gree...Driving Behavioral Change for Information Management through Data-Driven Gree...
Driving Behavioral Change for Information Management through Data-Driven Gree...
 
How to convert PDF to text with Nanonets
How to convert PDF to text with NanonetsHow to convert PDF to text with Nanonets
How to convert PDF to text with Nanonets
 
Artificial Intelligence: Facts and Myths
Artificial Intelligence: Facts and MythsArtificial Intelligence: Facts and Myths
Artificial Intelligence: Facts and Myths
 
What Are The Drone Anti-jamming Systems Technology?
What Are The Drone Anti-jamming Systems Technology?What Are The Drone Anti-jamming Systems Technology?
What Are The Drone Anti-jamming Systems Technology?
 
Scaling API-first – The story of a global engineering organization
Scaling API-first – The story of a global engineering organizationScaling API-first – The story of a global engineering organization
Scaling API-first – The story of a global engineering organization
 
Boost PC performance: How more available memory can improve productivity
Boost PC performance: How more available memory can improve productivityBoost PC performance: How more available memory can improve productivity
Boost PC performance: How more available memory can improve productivity
 
Histor y of HAM Radio presentation slide
Histor y of HAM Radio presentation slideHistor y of HAM Radio presentation slide
Histor y of HAM Radio presentation slide
 
Advantages of Hiring UIUX Design Service Providers for Your Business
Advantages of Hiring UIUX Design Service Providers for Your BusinessAdvantages of Hiring UIUX Design Service Providers for Your Business
Advantages of Hiring UIUX Design Service Providers for Your Business
 
TrustArc Webinar - Stay Ahead of US State Data Privacy Law Developments
TrustArc Webinar - Stay Ahead of US State Data Privacy Law DevelopmentsTrustArc Webinar - Stay Ahead of US State Data Privacy Law Developments
TrustArc Webinar - Stay Ahead of US State Data Privacy Law Developments
 
GenCyber Cyber Security Day Presentation
GenCyber Cyber Security Day PresentationGenCyber Cyber Security Day Presentation
GenCyber Cyber Security Day Presentation
 
Handwritten Text Recognition for manuscripts and early printed texts
Handwritten Text Recognition for manuscripts and early printed textsHandwritten Text Recognition for manuscripts and early printed texts
Handwritten Text Recognition for manuscripts and early printed texts
 
08448380779 Call Girls In Greater Kailash - I Women Seeking Men
08448380779 Call Girls In Greater Kailash - I Women Seeking Men08448380779 Call Girls In Greater Kailash - I Women Seeking Men
08448380779 Call Girls In Greater Kailash - I Women Seeking Men
 
IAC 2024 - IA Fast Track to Search Focused AI Solutions
IAC 2024 - IA Fast Track to Search Focused AI SolutionsIAC 2024 - IA Fast Track to Search Focused AI Solutions
IAC 2024 - IA Fast Track to Search Focused AI Solutions
 
Mastering MySQL Database Architecture: Deep Dive into MySQL Shell and MySQL R...
Mastering MySQL Database Architecture: Deep Dive into MySQL Shell and MySQL R...Mastering MySQL Database Architecture: Deep Dive into MySQL Shell and MySQL R...
Mastering MySQL Database Architecture: Deep Dive into MySQL Shell and MySQL R...
 
08448380779 Call Girls In Civil Lines Women Seeking Men
08448380779 Call Girls In Civil Lines Women Seeking Men08448380779 Call Girls In Civil Lines Women Seeking Men
08448380779 Call Girls In Civil Lines Women Seeking Men
 
From Event to Action: Accelerate Your Decision Making with Real-Time Automation
From Event to Action: Accelerate Your Decision Making with Real-Time AutomationFrom Event to Action: Accelerate Your Decision Making with Real-Time Automation
From Event to Action: Accelerate Your Decision Making with Real-Time Automation
 
Breaking the Kubernetes Kill Chain: Host Path Mount
Breaking the Kubernetes Kill Chain: Host Path MountBreaking the Kubernetes Kill Chain: Host Path Mount
Breaking the Kubernetes Kill Chain: Host Path Mount
 

SEQUENTIAL AND COMBINATIONAL CIRCUITS,DIGITAL LOGIC DESIGN

  • 1.
  • 2. DIGITAL LOGIC CIRCUITS ~ INTRODUCTION TO COMBINATIONAL AND SEQUENTIAL CIRCUITS. ~DESIGN PROCEDURE OF COMBINATIONAL CIRCUITS ~ANALYSIS PROCEDURE OF COMBINATIONAL CIRCUITS PRESENTED BY: QURATULAIN BS(CS)-1 QUAID-E-AZAM UNIVERSITY ISLAMABAD ,PAKISTAN.
  • 3. TYPES OF DIGITAL LOGIC CIRCUITS  COMBINATIONAL CIRCUITS  SEQUENTIAL CIRCUITS
  • 4. COMBINATIONAL CIRCUITS  Combinational Circuits are made of logic gates.  Doesn’t contain memory element , that’s why they cant store any information.  Value of present output is determined by present input.  Examples of combinational circuits are half adders, full adders, sub tractors etc.
  • 5. BLOCK DIAGRAM OF A COMBINATIONAL CIRCUIT
  • 6. SEQUENTIAL LOGIC CIRCUITS  Made up of combinational circuits and memory elements.  These memory elements are devices capable of storing ONE-BIT information.  Output depend on input and previous state.  Examples of sequential circuits are flip flops, counters, shift registers
  • 7. BLOCK DIAGRAM OF A SEQUENTIAL CIRCUIT
  • 8. TYPES OF SEQUENTIAL CIRCUITS Sequential circuits are of two types: 1.SYNCHRONOUS CIRCUITS:  In synchronous sequential circuits, the state of the device changes only at discrete times in response to a clock Pulse. 2.ASYNCHRONOUS CIRCUITS:  Asynchronous circuit is not synchronized by a clock signal; the outputs of the circuit change directly in response to changes in Inputs.
  • 9. DESIGN PROCEDURE OF COMBINATIONAL CIRCUITS This procedure involves the following steps:  The problem is stated.  The number of available input variables and output variables is determined.  The input and output variables are assigned letter symbols.  Truth table is drawn  Boolean function for output is obtained.
  • 10. ANALYSIS PROCEDURE OF COMBINATIONAL CIRCUIT  TO DETERMINE THE OUTPUT FUNCTIONS AS ALGEBRAIC EXPRESSIONS.  It is the reverse process of design procedure.  Logic diagram of the circuit is given.  Obtain the truth table from the diagram.  Obtain Boolean function from the Truth Table for output.
  • 12. THE CIRCUIT HAS THREE INPUTS, A,B,C AND TWO OUTPUTS F1 AND F2  The Boolean function for outputs are: F2=AB+AC+BC T1=A+B+C T2=ABC  Outputs functions for gates are : T3=F2’T1 F1=T3+T2
  • 14. TRUTH TABLE DRAWN FROM THE LOGIC DIAGRAM.
  • 15. BOOLEAN FUNCTIONS OBTAINED FOR OUTPUT ARE :  F2=AB+AC+BC  F1=A’BC’+A’B’C+AB’C’+ABC