1. Design Verification at D2Audio
March 8, 2006
Mayur Mehta
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2. D2Audio Products
• D2Audio builds all Digital Class D amplifier controller ICs
which use sophisticated digital Pulse Width Modulation
(PWM) Techniques.
All-digital signal path
On-Chip DSP provides amplifier controls and
comprehensive audio signal processing.
25-600 watts per channel
93% power efficient
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3. D2Audio Products –
Enabling Digital Power In The Broad Audio Market
Consumer
Professional
Automotive
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4. D2Audio Integrates Multiple Functions in IC
Amplifier GUI
DSP
Digital I /O
VID1___
Firmware
VID2___
AUD___
HDMI__
S/PDIF_
Tuner__
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5. ONLY True “Scalable” Solution from 15W to 600W Today!
Assumed Performance Constraints
• 8-ohm Loudspeaker
• < 0.1% Distortion
• > 100dB SNR D2Audio
150W+
• Reliable and Cost-Effective Intelligent Discrete Discrete
PWM Controller Driver N+N FETs
D2Audio
125W Intelligent Discrete Discrete
PWM Controller Driver N+P FETs
Power Level (8 ohm)
Technology-Imposed Limit
Integrated Discrete
75W Controller
Driver FETs
• 40V Process Limit
• Protection
• Control
Integrated • Drive
50W Controller
Power Stage
PWM controller Drive/Protection/Power
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6. Verification Overview
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7. Chips Developed
• 1st Gen Digital Audio Engine IC (DAE-1)
PWM Controller with SRC (Sample Rate Converter), DSP, Output
Protection
In production for > 1year
• Demonstrated full audio performance and features on first silicon.
• 2nd Gen Digital Audio Engine IC (DAE-2)
First to develop Class D amplifier with all-digital feedback
• Power supply feed-forward and closed-loop feedback technology correct for
power supply variations, non-linearity and other distortion-inducing
mechanisms
• As much as 60dB performance improvement
• Most analog PWM Solutions use analog closed-loop feedback
In Production Now
• Demonstrated full audio performance with feed forward and feedback on first
silicon
• 4 channel and 7 channel reference design solutions
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8. Chip Block Diagram
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9. Verification Techniques
• C++ Model
• Verilog simulations
Block-level and chip-level verification
NC-Verilog, Verdi and SureCov
CVS, Bugzilla and nLint
Verilog level transactors interacting with embedded C Program to
synchronize DSP and I/O functions
Assembly level and C code to perform DSP functions
• FPGA emulation
Full chip implementation synthesized to Xilinx FPGA
Custom I/O boards developed for “rest of system”
Connectivity to real world audio streams
Back-end power electronics for amplifier system testing
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10. Development and Verification Flow for Signal Processing
Blocks
• Matlab – Numerical Analysis tool to aid in developing
algorithms
• C++ based simulator
• Matlab script generates a setup file and input data files
Executes the C++ simulator and dumps output into files.
On termination of simulator, Matlab script performs analysis of
the data produced by simulator.
• C++ model to implement algorithms on a fairly high level
Verify the functionality using the above C++ simulator
Determine gross computational complexity
• Refine the algorithms to a cycle accurate level
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11. Development and Verification Flow
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12. Development and Verification Flow (Contd.)
• Verification environment
Generate setup files, input and expected output data for the RTL
Simulator.
Verilog based transactor performs RTL initialization, initializes the
computational engine and runs the simulation with input data while it
compares output data to the expected data read from files.
Run Verilog simulations with the cycle accurate model in parallel to verify
that the RTL implementation has same functionality and identical
performance to the original model.
• Run extensive simulations to exercise typical setups as well as the
boundaries of the design.
• Typically the output files from Matlab become part of the design data
base
Test Suites for regression testing
• Maintain C++ model to match architectural and design changes
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13. Block Diagram of Chip-level Verification
Global
Transactor Transactor Transactor
PUMPLO
PSSYNC
OSCOUT
PUMPHI
XTALO
SRD0
SRD1
SCK0
SCK1
XTALI
STD0
STD1
SC0
SC1
TIO
3
3
3
2
SDIN
Reserved
Serial Audio Interface
2 PLL Timer
SCKR Serial Audio Interface
Transactor
2
LRCLK
MCLK
SCLKT
LRCKT Digital Signal Processor Pulse Width Modulator
SDOUT
SCLK PWMH0
Frequency Response Correction
RXD SCI Sample Rate Conversion PWML0
Transactor
TXD PWMH1
Transactor
Linear Interpolator
PWM Correction
PWML1
Noise Shaper
Output Drive
SCL
Quantizer
2-Wire
Effects
PWMH2
SDA
PWML2
SPDIFRX PWMH3
S/PDIF PWML3
SPDIFTX
nRESET OTSEL
Control
nRSTOUT
Transactor
PWMSYNC
5
SYS
4
BMS
8
GPIO
16 TEST Power Supply Protection
XGPIO
4
4
4
PROTECTC
PROTECTA
PROTECTB
PLLAVDD
PLLAGND
PLLDVDD
PLLDGND
OSCVDD
PWMVDD
PWMGND
CVDD
CGND
RVDD
RGND
nTRST
TEST
Test.c Test.V
Transactor
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14. Verification Techniques – FPGA Emulation
•1:1 Mapping with the chip
•Capability to do
performance correlation
•Verify external Interfaces
•Platform for software
development
•Vehicle to demonstrate
performance and new
FPGA Emulation System features
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15. Lessons Learned
• Always Emulate
Bug count found in FPGA emulation easily justifies effort and
resources expended
Confidence of working with real world interfaces without surprises
Great tool to develop software which allows us to accelerate
firmware development
Emulation system should be scalable, repeatable and
transportable
• Top-level environment where tests can be
interchangeably simulated and emulated is very valuable.
Needed to debug emulation system during bring up stages
FPGA was always correlated with RTL
FPGA emulation is used as a hardware accelerator
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16. Lessons Learned (Contd.)
• Code Coverage was useful in finding holes in our test
cases
• Project Management
Comprehensive Microsoft Project scheduling with detailed
dependencies between RTL Development, Block-level
verification,Chip verification, FPGA and Physical design
completion
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17. Why the current methodology works for D2Audio
• Comprehensive block-level and system-level specifications
• Easy to use test environment allowed us to generate comprehensive
tests
• Everything under CVS control
• Production firmware was run on FPGA emulation before tape-out
• Comprehensive verification in simulation environment before starting
FPGA Verification
• FPGA emulation confirmed performance before tape-out
Confirms that the high-level model represents reality
Plug tests
• Simple verification environment allowed us to scale verification
resources
• Mature engineering team
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18. Improvements
• Plan to use assertion tools for debugging, verification and
Code/functional coverage
• Add regression suite for FPGA builds
• Evaluate System C/System Verilog
Improve inefficiencies in the current verification environment
• Test Development
• CPU intensive
• Verify external IP for complete functionality and clear
specifications
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19. Suggested Follow-up activities of DVClub
• Present a methodology which has used assertion tools
• Present a methodology which has used code and
functional coverage tools
Correlation with bugs found on chip
How do you use it to predict schedule and tape-out decision
• Discuss Verification projects which did not use FPGA
emulation
• Discuss projects which developed software simulator of a
chip for partners to use for software development
• DV for mixed signal ICs
• Pros and Cons of outsourcing verification
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