SlideShare uma empresa Scribd logo
1 de 9
Baixar para ler offline
The Design is not Correct!



              Adam Krolnik
Co-Author Assertion-Based Design 2nd Edition
   ZSP Verification Mgr. LSI Logic Corp
Introduction
●   Assertions are 50+ years old [Alan Turing]

●   Conceived to assist in validation

●   Statements of truth to be verified.

●   Basis for functional coverage.
Designer and DV Tool
●   Allows Concise description of protocols
●   Easily written next to HDL code for review,
    recall, etc.
●   Describe intent not normally known to DV!
●   Trap faulty behavior closer to source.
●   Quick to modify if spec. or behavior is
    changed.
●   Minimal effort (few hours) for good results
Best practices
●   Errors get fixed, Warnings are ignored.
●   Thinking about assertions can find bugs.
●   Write assertions for module interfaces as
    they are written. [~1 per port] (HW)
●   Write protocol checks/monitors (DV)
●   Minimum #3-5 required as encouragement.
    (HW)
●   Active comments detect bad behavior (HW)
Best Practices cont.
●   Verify old vs. new equations (HW timing opt)
●  Error messages convey missing information
Illegal alignment of address (25) for word size
Illegal request during pending flush, See John
Extra done sent. See BR block.
Request (4) did not complete in 1000
 cycles.

●   Stop simulations on the first error.
OVL vs. PSL vs. SVA
●   80% of Assertions are simple
    SVA assert property (@(posedge clk)
            disable_iff ! rst_n ( expression ));
    PSL assert always (expression)
           @(posedge clk) abort ! rst_n ;
    OVL assert_always A1(clk, rst_n, expression );

●   10% of Assertions need either
    SVA not ( expr1 ##1 expr2) or expr1 |-> expr2
    PSL      ( expr1 ; expr2)   or expr1 |-> expr2
    OVL assert_next()
Next steps
●   Protocol verification tools
    –   Need assertions on interface to define legal
        behavior (best practice)

●   End to end verification
    –   Need well defined specifications
          (Assertions help reduce ambiguity)
Conclusions
●   Unbug the design, don't debug the design.
    Assertions are the designers part.

●   Assertions are concise;
    simplifying monitors and checking code

●   Focus assertions on interfaces to trap wrong
    behavior early.

Mais conteúdo relacionado

Mais procurados

Measuring Code Quality in WTF/min.
Measuring Code Quality in WTF/min. Measuring Code Quality in WTF/min.
Measuring Code Quality in WTF/min. David Gómez García
 
Randomization and Constraints - Workshop at BMS College
Randomization and Constraints - Workshop at BMS CollegeRandomization and Constraints - Workshop at BMS College
Randomization and Constraints - Workshop at BMS CollegeRamdas Mozhikunnath
 
Integrating Proof and Testing in Verification Strategies for Safety Critical ...
Integrating Proof and Testing in Verification Strategies for Safety Critical ...Integrating Proof and Testing in Verification Strategies for Safety Critical ...
Integrating Proof and Testing in Verification Strategies for Safety Critical ...AdaCore
 
Systematic Evaluation of the Unsoundness of Call Graph Algorithms for Java
Systematic Evaluation of the Unsoundness of Call Graph Algorithms for JavaSystematic Evaluation of the Unsoundness of Call Graph Algorithms for Java
Systematic Evaluation of the Unsoundness of Call Graph Algorithms for JavaMichael Reif
 

Mais procurados (6)

Measuring Code Quality in WTF/min.
Measuring Code Quality in WTF/min. Measuring Code Quality in WTF/min.
Measuring Code Quality in WTF/min.
 
Randomization and Constraints - Workshop at BMS College
Randomization and Constraints - Workshop at BMS CollegeRandomization and Constraints - Workshop at BMS College
Randomization and Constraints - Workshop at BMS College
 
Integrating Proof and Testing in Verification Strategies for Safety Critical ...
Integrating Proof and Testing in Verification Strategies for Safety Critical ...Integrating Proof and Testing in Verification Strategies for Safety Critical ...
Integrating Proof and Testing in Verification Strategies for Safety Critical ...
 
Static Code Analysis
Static Code AnalysisStatic Code Analysis
Static Code Analysis
 
Systematic Evaluation of the Unsoundness of Call Graph Algorithms for Java
Systematic Evaluation of the Unsoundness of Call Graph Algorithms for JavaSystematic Evaluation of the Unsoundness of Call Graph Algorithms for Java
Systematic Evaluation of the Unsoundness of Call Graph Algorithms for Java
 
SYNCHRONIZATION
SYNCHRONIZATIONSYNCHRONIZATION
SYNCHRONIZATION
 

Destaque

Alley vsu functional_coverage_1f
Alley vsu functional_coverage_1fAlley vsu functional_coverage_1f
Alley vsu functional_coverage_1fObsidian Software
 
Lear design con_east_2004_simplifing_mixed_signal_simulation
Lear design con_east_2004_simplifing_mixed_signal_simulationLear design con_east_2004_simplifing_mixed_signal_simulation
Lear design con_east_2004_simplifing_mixed_signal_simulationObsidian Software
 
2010 bristol q1_heuristic-stimuli-generation
2010 bristol q1_heuristic-stimuli-generation2010 bristol q1_heuristic-stimuli-generation
2010 bristol q1_heuristic-stimuli-generationObsidian Software
 
D2 audio digital_media_drives_ic_content
D2 audio digital_media_drives_ic_contentD2 audio digital_media_drives_ic_content
D2 audio digital_media_drives_ic_contentObsidian Software
 
Low power design-ver_26_mar08
Low power design-ver_26_mar08Low power design-ver_26_mar08
Low power design-ver_26_mar08Obsidian Software
 
Jm future of system verilog verification
Jm future of system verilog verificationJm future of system verilog verification
Jm future of system verilog verificationObsidian Software
 
Durgam vahia open_sparc_fpga
Durgam vahia open_sparc_fpgaDurgam vahia open_sparc_fpga
Durgam vahia open_sparc_fpgaObsidian Software
 
Nilesh ranpura systemmodelling
Nilesh ranpura systemmodellingNilesh ranpura systemmodelling
Nilesh ranpura systemmodellingObsidian Software
 

Destaque (13)

Abraham march07
Abraham march07Abraham march07
Abraham march07
 
Alley vsu functional_coverage_1f
Alley vsu functional_coverage_1fAlley vsu functional_coverage_1f
Alley vsu functional_coverage_1f
 
Dham bangalore q407
Dham bangalore q407Dham bangalore q407
Dham bangalore q407
 
Lear design con_east_2004_simplifing_mixed_signal_simulation
Lear design con_east_2004_simplifing_mixed_signal_simulationLear design con_east_2004_simplifing_mixed_signal_simulation
Lear design con_east_2004_simplifing_mixed_signal_simulation
 
Kl assertions 081705
Kl assertions 081705Kl assertions 081705
Kl assertions 081705
 
Firstenberg q207
Firstenberg q207Firstenberg q207
Firstenberg q207
 
2010 bristol q1_heuristic-stimuli-generation
2010 bristol q1_heuristic-stimuli-generation2010 bristol q1_heuristic-stimuli-generation
2010 bristol q1_heuristic-stimuli-generation
 
D2 audio digital_media_drives_ic_content
D2 audio digital_media_drives_ic_contentD2 audio digital_media_drives_ic_content
D2 audio digital_media_drives_ic_content
 
Low power design-ver_26_mar08
Low power design-ver_26_mar08Low power design-ver_26_mar08
Low power design-ver_26_mar08
 
Jm future of system verilog verification
Jm future of system verilog verificationJm future of system verilog verification
Jm future of system verilog verification
 
3 d to_hpc
3 d to_hpc3 d to_hpc
3 d to_hpc
 
Durgam vahia open_sparc_fpga
Durgam vahia open_sparc_fpgaDurgam vahia open_sparc_fpga
Durgam vahia open_sparc_fpga
 
Nilesh ranpura systemmodelling
Nilesh ranpura systemmodellingNilesh ranpura systemmodelling
Nilesh ranpura systemmodelling
 

Semelhante a Krolnik ak metro_dv_nov

Simplified Troubleshooting through API Scripting
Simplified Troubleshooting through API Scripting Simplified Troubleshooting through API Scripting
Simplified Troubleshooting through API Scripting Network Automation Forum
 
Exploring No Mans Land with Keyword-Driven Testing
Exploring No Mans Land with Keyword-Driven TestingExploring No Mans Land with Keyword-Driven Testing
Exploring No Mans Land with Keyword-Driven TestingMartinGijsen
 
Introduction to Contracts and Functional Contracts
Introduction to Contracts and Functional ContractsIntroduction to Contracts and Functional Contracts
Introduction to Contracts and Functional ContractsDaniel Prager
 
Python for Data Logistics
Python for Data LogisticsPython for Data Logistics
Python for Data LogisticsKen Farmer
 
Computer network (8)
Computer network (8)Computer network (8)
Computer network (8)NYversity
 
Floripa Gophers - Analysing Code Quality (Linters and Static Analysis)
Floripa Gophers - Analysing Code Quality (Linters and Static Analysis)Floripa Gophers - Analysing Code Quality (Linters and Static Analysis)
Floripa Gophers - Analysing Code Quality (Linters and Static Analysis)Weverton Timoteo
 
fpgartl-verilog-coding-for-sequential-circuit.pptx
fpgartl-verilog-coding-for-sequential-circuit.pptxfpgartl-verilog-coding-for-sequential-circuit.pptx
fpgartl-verilog-coding-for-sequential-circuit.pptxmohan676910
 
Improving Code Quality Through Effective Review Process
Improving Code Quality Through Effective  Review ProcessImproving Code Quality Through Effective  Review Process
Improving Code Quality Through Effective Review ProcessDr. Syed Hassan Amin
 
Unit Testing and TDD 2017
Unit Testing and TDD 2017Unit Testing and TDD 2017
Unit Testing and TDD 2017Xavi Hidalgo
 
Architecture for Massively Parallel HDL Simulations
Architecture for Massively Parallel HDL Simulations Architecture for Massively Parallel HDL Simulations
Architecture for Massively Parallel HDL Simulations DVClub
 
Quality Assurance
Quality AssuranceQuality Assurance
Quality AssuranceKiran Kumar
 
Dealing with the Three Horrible Problems in Verification
Dealing with the Three Horrible Problems in VerificationDealing with the Three Horrible Problems in Verification
Dealing with the Three Horrible Problems in VerificationDVClub
 
Keynote: Machine Learning for Design Automation at DAC 2018
Keynote:  Machine Learning for Design Automation at DAC 2018Keynote:  Machine Learning for Design Automation at DAC 2018
Keynote: Machine Learning for Design Automation at DAC 2018Manish Pandey
 
On component interface
On component interfaceOn component interface
On component interfaceLaurence Chen
 

Semelhante a Krolnik ak metro_dv_nov (20)

2nd presantation
2nd presantation2nd presantation
2nd presantation
 
Dill may-2008
Dill may-2008Dill may-2008
Dill may-2008
 
Coding style for good synthesis
Coding style for good synthesisCoding style for good synthesis
Coding style for good synthesis
 
Simplified Troubleshooting through API Scripting
Simplified Troubleshooting through API Scripting Simplified Troubleshooting through API Scripting
Simplified Troubleshooting through API Scripting
 
Tdd in practice
Tdd in practiceTdd in practice
Tdd in practice
 
Exploring No Mans Land with Keyword-Driven Testing
Exploring No Mans Land with Keyword-Driven TestingExploring No Mans Land with Keyword-Driven Testing
Exploring No Mans Land with Keyword-Driven Testing
 
Lecture1 introduction compilers
Lecture1 introduction compilersLecture1 introduction compilers
Lecture1 introduction compilers
 
Introduction to Contracts and Functional Contracts
Introduction to Contracts and Functional ContractsIntroduction to Contracts and Functional Contracts
Introduction to Contracts and Functional Contracts
 
Python for Data Logistics
Python for Data LogisticsPython for Data Logistics
Python for Data Logistics
 
Computer network (8)
Computer network (8)Computer network (8)
Computer network (8)
 
Floripa Gophers - Analysing Code Quality (Linters and Static Analysis)
Floripa Gophers - Analysing Code Quality (Linters and Static Analysis)Floripa Gophers - Analysing Code Quality (Linters and Static Analysis)
Floripa Gophers - Analysing Code Quality (Linters and Static Analysis)
 
fpgartl-verilog-coding-for-sequential-circuit.pptx
fpgartl-verilog-coding-for-sequential-circuit.pptxfpgartl-verilog-coding-for-sequential-circuit.pptx
fpgartl-verilog-coding-for-sequential-circuit.pptx
 
Improving Code Quality Through Effective Review Process
Improving Code Quality Through Effective  Review ProcessImproving Code Quality Through Effective  Review Process
Improving Code Quality Through Effective Review Process
 
Unit Testing and TDD 2017
Unit Testing and TDD 2017Unit Testing and TDD 2017
Unit Testing and TDD 2017
 
Architecture for Massively Parallel HDL Simulations
Architecture for Massively Parallel HDL Simulations Architecture for Massively Parallel HDL Simulations
Architecture for Massively Parallel HDL Simulations
 
Quality Assurance
Quality AssuranceQuality Assurance
Quality Assurance
 
Dealing with the Three Horrible Problems in Verification
Dealing with the Three Horrible Problems in VerificationDealing with the Three Horrible Problems in Verification
Dealing with the Three Horrible Problems in Verification
 
Keynote: Machine Learning for Design Automation at DAC 2018
Keynote:  Machine Learning for Design Automation at DAC 2018Keynote:  Machine Learning for Design Automation at DAC 2018
Keynote: Machine Learning for Design Automation at DAC 2018
 
On component interface
On component interfaceOn component interface
On component interface
 
OpenGL (ES) debugging
OpenGL (ES) debuggingOpenGL (ES) debugging
OpenGL (ES) debugging
 

Mais de Obsidian Software (20)

Zhang rtp q307
Zhang rtp q307Zhang rtp q307
Zhang rtp q307
 
Zehr dv club_12052006
Zehr dv club_12052006Zehr dv club_12052006
Zehr dv club_12052006
 
Yang greenstein part_2
Yang greenstein part_2Yang greenstein part_2
Yang greenstein part_2
 
Yang greenstein part_1
Yang greenstein part_1Yang greenstein part_1
Yang greenstein part_1
 
Williamson arm validation metrics
Williamson arm validation metricsWilliamson arm validation metrics
Williamson arm validation metrics
 
Whipp q3 2008_sv
Whipp q3 2008_svWhipp q3 2008_sv
Whipp q3 2008_sv
 
Vishakantaiah validating
Vishakantaiah validatingVishakantaiah validating
Vishakantaiah validating
 
Validation and-design-in-a-small-team-environment
Validation and-design-in-a-small-team-environmentValidation and-design-in-a-small-team-environment
Validation and-design-in-a-small-team-environment
 
Tobin verification isglobal
Tobin verification isglobalTobin verification isglobal
Tobin verification isglobal
 
Tierney bq207
Tierney bq207Tierney bq207
Tierney bq207
 
The validation attitude
The validation attitudeThe validation attitude
The validation attitude
 
Thaker q3 2008
Thaker q3 2008Thaker q3 2008
Thaker q3 2008
 
Thaker q3 2008
Thaker q3 2008Thaker q3 2008
Thaker q3 2008
 
Strickland dvclub
Strickland dvclubStrickland dvclub
Strickland dvclub
 
Stinson post si and verification
Stinson post si and verificationStinson post si and verification
Stinson post si and verification
 
Shultz dallas q108
Shultz dallas q108Shultz dallas q108
Shultz dallas q108
 
Shreeve dv club_ams
Shreeve dv club_amsShreeve dv club_ams
Shreeve dv club_ams
 
Sharam salamian
Sharam salamianSharam salamian
Sharam salamian
 
Schulz sv q2_2009
Schulz sv q2_2009Schulz sv q2_2009
Schulz sv q2_2009
 
Schulz dallas q1_2008
Schulz dallas q1_2008Schulz dallas q1_2008
Schulz dallas q1_2008
 

Krolnik ak metro_dv_nov

  • 1. The Design is not Correct! Adam Krolnik Co-Author Assertion-Based Design 2nd Edition ZSP Verification Mgr. LSI Logic Corp
  • 2. Introduction ● Assertions are 50+ years old [Alan Turing] ● Conceived to assist in validation ● Statements of truth to be verified. ● Basis for functional coverage.
  • 3. Designer and DV Tool ● Allows Concise description of protocols ● Easily written next to HDL code for review, recall, etc. ● Describe intent not normally known to DV! ● Trap faulty behavior closer to source. ● Quick to modify if spec. or behavior is changed. ● Minimal effort (few hours) for good results
  • 4. Best practices ● Errors get fixed, Warnings are ignored. ● Thinking about assertions can find bugs. ● Write assertions for module interfaces as they are written. [~1 per port] (HW) ● Write protocol checks/monitors (DV) ● Minimum #3-5 required as encouragement. (HW) ● Active comments detect bad behavior (HW)
  • 5. Best Practices cont. ● Verify old vs. new equations (HW timing opt) ● Error messages convey missing information Illegal alignment of address (25) for word size Illegal request during pending flush, See John Extra done sent. See BR block. Request (4) did not complete in 1000 cycles. ● Stop simulations on the first error.
  • 6.
  • 7. OVL vs. PSL vs. SVA ● 80% of Assertions are simple SVA assert property (@(posedge clk) disable_iff ! rst_n ( expression )); PSL assert always (expression) @(posedge clk) abort ! rst_n ; OVL assert_always A1(clk, rst_n, expression ); ● 10% of Assertions need either SVA not ( expr1 ##1 expr2) or expr1 |-> expr2 PSL ( expr1 ; expr2) or expr1 |-> expr2 OVL assert_next()
  • 8. Next steps ● Protocol verification tools – Need assertions on interface to define legal behavior (best practice) ● End to end verification – Need well defined specifications (Assertions help reduce ambiguity)
  • 9. Conclusions ● Unbug the design, don't debug the design. Assertions are the designers part. ● Assertions are concise; simplifying monitors and checking code ● Focus assertions on interfaces to trap wrong behavior early.