2. INTRODUCTION
Integrated circuits: many transistors on single chip.
Metal Oxide Semiconductor (MOS) transistor
Fast, cheap, low-power transistors
Complementary: mixture of n- and p-type leads to
less power
11. CMOS FABRICATION PROCESS
well formation
Well will be formed
here
By photolithography and etching process,
well opening are made
photolithography and etch processes are shown in next slides
12. PHOTOLITHOGRAPHY (CED)
photoresist
Si02 Photoresist coating (C)
P-substrate
UV light Masking and exposure under
mask
UV light(E)
Resist dissolved after
Opaque
area
developed (D)
P-substrate ◦ Pre-shape the well pattern at
Transparent
area resist layer
13. ETCHING
Removing the unwanted pattern
P-substrate by wet etching
Resistclean
Desired pattern formed
P-substrate
14. CMOS FABRICATION PROCESS
well formation
Phosphorus ion
Ion bombardment by ion implantation
SiO2 as mask, uncovered area will exposed
to dopant ion
15. CMOS FABRICATION PROCESS
Isolation formation
Thick oxide
IncreaseSiO2 thickness by oxidation at high
temperature
Oxide will electrically isolates nmos and
pmos devices
16. CMOS FABRICATION PROCESS
transistor making
nmos will pmos will
be formed be formed
here here
By photolithography and etching process,
pmos and nmos areas are defined
20. CMOS FABRICATION
PROCESS
transistor making
Arsenic ion
photoresist
Photo process to define the nmos active
(source and drain) area and VDD contact
Ion implantation with Arsenic ion for n+
dopant.
Photoresist and polysilicon gate act as
mask
22. CMOS FABRICATION
PROCESS
transistor making
Boron ion
photoresist
Photo process to define the GND contact
and pmos active area (source and drain)
Ion implantation with boron for p+
dopant
Photoresist and gate act as mask