1. On MPSoC Software Execution at the Transaction Level
1.Frederic Petrot
Grenoble Institute of Technology
2. Nicolas Fournel and Patrice Gerin
Kalray
3.Marius Gligor, Mian-Muhammad Hamayun,
and Hao Shen
Grenoble Institute of Technology
IEEE Design & Test of Computers Volume:28 Issue:3
@2011 IEEE
NILAMADHAB MISHRA
D0121008
Access provided by: Chang Gung University

2. Contents
• Aim
• Concept
• Transaction level modeling(TLM)
• Handling software in MPSoC simulations
• Methods used for s/w execution
• Comparison of simulation strategies
• Integration into TLM environment
• Conclusion
2

3. Aim
• The basic aim of this paper is to present a wide variety of
techniques for realizing transaction-level models of the increasingly
large-scale multiprocessor systems on chip.
• It describes how such models of hardware allow subsequent
software integration and system performance evaluation.
• To review the challenges involved in introducing software and
hardware-software simulation in MPSoCs at the transaction
level.
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4. Contents
• Aim
• Concept
• Transaction level modeling(TLM)
• Handling software in MPSoC simulations
• Methods used for s/w execution
• Comparison of simulation strategies
• Integration into TLM environment
• Conclusion
4

5. Concept
• A SoC is an integrated circuit that integrates all components of
a computer and other electronic system into a single chip.
• The co-simulated platform for a SoC aims to develop the
hardware and software in parallel.
• A typical SoC consists of:
-MPSoC-multiprocessor system on chip(having multi processors
core).
-Memory blocks(ROM/PROM/FLASH).
-Timing sources like oscillators.
-Peripherals like timers.
-External interfaces like USB, Ethernet, etc..
-Analog interfaces like ADCs and DACs.
-Voltage regulators and power management circuit.
5

6. Concept
• The current state-of-the-art:
multi processors core ,Multiple computational and data-
processing engines, memory, and peripherals, all constructed
on a single silicon chip called a MPSOC.
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7. Concept
7

8. Example of MPSoC and applications
• Emotion Engine from the Sony Play station 2
– 3 processors (general purpose CPU, 2 vector
processing units)
• CELL processor from Sony, Toshiba, IBM
– 9 processors (general purpose CPU, 8 processing
elements)
• Nomadic for Nokia mobile phone
• ST7200 for DVD or HDTV
– 5 processors (general purpose CPU, 4 digital signal
processors)
• DaVinci (Texas Instrument) for cameras
– 3 processors (general purpose CPU, 2 digital signal
processors)
• Diopsis D940 for Massive parallel processor system
(Petaflop)
– 3 processors (general purpose CPU, 1 DSP VLIW, 1
network processor) 2048

9. Contents
• Aim
• Concept
• Transaction level modeling(TLM)
• Handling software in MPSoC simulations
• Methods used for s/w execution
• Comparison of simulation strategies
• Integration into TLM environment
• Conclusion
9

10. Transaction level modeling(TLM)
• The basis for a unified system model is called as Transaction
Level Modeling (TLM).
• TLM based Unified System Models provide a means to carry
out design and verification hand in hand while promoting
hardware / software co-development platform.
• To provide simulation platforms suited to early verification of
software running on complex SoC architectures before their
availability as actual hardware platforms.
Transaction is the basic representation for exchange of information between two blocks.
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11. Transaction level modeling(TLM)
• Transaction-level hardware-software simulation of
multiprocessor SoCs (MPSoCs) requires handling software
execution in some way.
• Thus, two different strategies have been developed to
provide suitable environments for executing software code.
• 1.Row instruction interpretation of cross complied code.
• 2.Native execution of the code on the host.
Transaction is the basic representation for exchange of information between two blocks.
11

12. Contents
• Aim
• Concept
• Transaction level modeling(TLM)
• Handling software in MPSoC simulations
• Methods used for s/w execution
• Comparison of simulation strategies
• Integration into TLM environment
• Conclusion
12

13. Handling software in MPSoC simulations
Software architecture: The rôle of layer
Application
• The application layer may be a multi-tasking description or a single task
function of the application targeted to be executed on the software (processor)
subsystem.
• A task or thread is a lightweight process that runs sequentially
Multiple tasks can be executed in parallel by a single CPU or by multiple CPUs.
Operating System (OS)
• The OS manages the sharing of the resources of the architecture.
• It is responsible for the initialization and management of the application tasks
and communication between them.

14. Handling software in MPSoC simulations
Software architecture: The rôle of layer
Communication
• This layer is responsible to manage the I/O operations and more generally the
interaction with the hardware components and the other subsystems. It may
include different communication protocols, such as fifo (first-in-first-out)
implemented in software, or communication using dedicated hardware
components (DMA).
HAL (Hardware Abstraction layer)
• The HAL provides a unique programming interface to manipulate hardware
devices.
• The HAL is a thin software layer which totally depends on the type of processor
that will execute the software, but also depends on the hardware resources
interacting with the processor.

15. Handling software in MPSoC
simulations
Integrations of software within the TLM hardware architecture 15

16. Handling software in MPSoC
simulations
• To execute every single software instruction, the most straight
foreword strategy is instruction-accurate interpretation.
• The left side of the figure represents an application split in
software layer and right side represents the TLM hardware on
which the software runs.
• For the interpretation of cross complied code , all layers are
loaded into program memory, so h/w abstraction not required.
• For Native execution approach, the execution unit abstracts
either OS layer or hardware abstraction layer(HAL).
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17. Contents
• Aim
• Concept
• Transaction level modeling(TLM)
• Handling software in MPSoC simulations
• Methods used for s/w execution
• Comparison of simulation strategies
• How to integrate into TLM environment
• Conclusion
Methods used for s/w execution 17

18. Methods used for s/w execution
• Interpretive methods-
(3-techniques for interpretation )
1.Instruction accurate interpretation
2.Dynamic binary translation
3.semihosting execution
The s/w interpretations is the process of transforming instruction
from target processor into the instruction of host processor. It
always requires decoding an instruction and execute it’s
behavior.
• Native execution method-Most efficient way of executing s/w
directly on host machine.
Methods used for s/w execution 18

19. Interpretive methods
1. Instruction accurate interpretation-
• Uses decode-dispatch method
• Easy to implement and can be made accurate
• Support simulations of entire support layers
• Problems – very slow and not suited for extensive software
based validations.
• In interpretive predecoding- simulation speed is slow, but
having high simulation accuracy. For 1st time development is
complexed, but reuse is easier.
Methods used for s/w execution 19

20. Interpretive methods
2.Dynamic binary translation-
• Very efficient.
• Achieve ultimate goal and accuracy .
• Problems –conceptually complex and challenging to
implement.
3.semihosting execution-
• This approach is efficient and leads to high gains in simulation
speed.
• Does not provide any extra benefits as compared to other
methods, hence no more use.
• More time consumes in performance evaluation.
Methods used for s/w execution 20

21. Native execution method
• Most efficient way of executing s/w directly on host machine.
• Simulation is fast and well suited for well-structured software.
• It requires entire program codes in high level language ,not in
assembly language codes.
• For performance evaluation, many researchers have proposed
the ways to insert time annotation into source codes to
estimate execution time.
Methods used for s/w execution 21

22. Contents
• Aim
• Concept
• Transaction level modeling(TLM)
• Handling software in MPSoC simulations
• Methods used for s/w execution
• Comparison of simulation strategies
• Integration into TLM environment
• Conclusion
22

23. Comparison of simulation strategies
• Here the 4-software execution methods are compared in terms of speed,
simulation accuracy and development time.
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24. Contents
• Aim
• Concept
• Transaction level modeling(TLM)
• Handling software in MPSoC simulations
• Methods used for s/w execution
• Comparison of simulation strategies
• Integration into TLM environment
• Conclusion
For s/w execution , an environment is required , that is known as a TLM environment 24

25. Integration into TLM environment
• Here the author focuses on 3 software execution strategies i.e.
instruction accurate interpretation ,dynamic binary translation
and native s/w execution into TLM environment, that supports
notion of time and target multi-processor platform.
1. Instruction accurate interpretation :-
-It describes the integrations of accurate interpretation method into TLM
environment.
- Instruction accurate ISS(instruction set simulator)technology is popular in TLM
environment.
- Suffers low simulation speed and remains a bottleneck for MPSoC simulation.
- Time annotation is not difficult with this technology, but each added
architectural details is an extra burden on the already low simulation speed.
Describes the integrations of 3-strategies/methods into TLM environment 25

26. Integration into TLM environment
2.Dynamic binary translation:-
- It describes the integration of dynamic binary translation method into
TLM environment.
dynamic binary translation simulation model. pc-program counter, TB-translation block 26

27. Integration into TLM environment
3.Native s/w execution:-
-Native s/w simulation targets the direct execution of s/w code on the
host machine to an event driven simulation environment.
Annotation strategy(fig)-describes the normal use of intermediate representation is the target
object code generation , because it represents the actual control flow of the target program
after all optimizations.
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28. Integration into TLM environment
Native s/w execution(cont..):-
- Native approaches can provide application and operating
system timing information by embedding simulator wait
statements into the s/w codes.
- The annotation pass analyzes the target code and insert calls
to an annotation function. The annotated intermediate
representation (IR) then used to generate a native binary
object ,which has a control flow graph equivalent to the target
object and can be simulated on the host machine.
Native s/w execution 28

29. Contents
• Aim
• Concept
• Transaction level modeling(TLM)
• Handling software in MPSoC simulations
• Methods used for s/w execution
• Comparison of simulation strategies
• Integration into TLM environment
• Conclusion
29

30. Conclusion
• Out of three s/w execution strategy, the native
simulation strategy is well suited to the
development of software stake’s upper layer.
• This strategy can able to provide accurate
performance results at a high simulation
speed by using annotation strategies.
QUERY PLEASE?
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