SlideShare uma empresa Scribd logo

JTAG Interface (Intro)

•
•
Nitesh Bhatia
Nitesh Bhatia

Introduction to JTAG Interface for debugging embedded micro-controller and devices.

EducaçãoTecnologiaNegócios
1 de 21
JTAG Interface Nitesh Bhatia- 200501071 Embedded Systems | DA-IICT | 2009 Joint Test Action Group
Outline !! Background – need for JTAG !! JTAG and Boundary Scan !! Advantages !! Atmel ICE mk-II and gdb !! Real JTAG Applications
Bed of Nails fixture !! PCB testing was done using Bed of Nails in circuit testing.
Past to Future – Testing !! Miniaturization results in loss of test access Yesterday TomorrowToday
Circuit Complexity / Cost !! Increasing integration at chip level complicates controllability. Yesterday Today
JTAG (1149.1 Standard) !! IEEE 1149.1, a standard 5-pin serial protocol that established the details of access to any chip with JTAG port. !! Features: !! Boundary scan testing of ICs !! Debug Embedded devices !! System level debug capability
JTAG – Boundary Scan !! Boundary scan is a methodology allowing complete controllability and observablity of the boundary pins of a JTAG compatible device via software control.
Boundary Scan Principle The top level schematic of test logic defined by IEEE Std 1149.1 includes three key blocks: !! The TAP Controller !! This responds to the control sequences supplied through the test access port (TAP) and generates the clock and control signals required for correct operation of the circuit blocks !! The Instruction Register !! This shift register-based circuit is serially loaded with the instructions that selects an operation to be performed !! The Data Registers !! These are a bank of shift register based circuits.The stimuli required by an operation are serially loaded into the data registers selected by the current instruction. Following execution of the operation, results can be shifted out for examination.
What can it be used for !! The standard defines instructions that can be used to perform !! Functional Tests !! Interconnect Tests !! Built-in self test procedures
Advantages !! Need for physical test points on board is eliminated => simpler board layouts !! Cheap test fixtures !! Reduced time on in-circuit test systems !! Increased use of standard interfaces !! Faster time-to-market
Widespread uses !! A large proportion of high end embedded systems have a JTAG port. !! The PCI bus connector standard contains optional JTAG signals (pins 1-5); PCI-Express contains JTAG signals (pins 5-9).A special JTAG card can be used to re-flash a corrupt BIOS. !! Almost all FPGAs and CPLDs used today can be programmed via the JTAG port.
JTAG Software !! Open Source !! UrJTAG project supports many JTAG tools, processors, and boards. !! OpenOCD project supports various inexpensive JTAG adapters including USB ones based on FT2232 chips, and is mostly used with ARM projects. It provides GDB and telnet interfaces, both from Linux and from MS-Windows. !! Freeware !! Atmel provides AVR Studio on MS-Windows, for AVR8 microcontrollers, and a cross-platform AVR32studio product to support AVR32 systems. !! Xilinx provides lower end FPGA development tools at no cost !! HappyJTAG2 is embedded JTAG solution with FT2232 chip for AVR8 microcontrollers and Atmel AVR Studio on MS-Windows.
Working Source: http://www.corelis.com/products/ScanExpressJET.htm
JTAG ICE mkII and gdb. !! Functions - !! Run !! Stop !! Step !! Write to Registers and memory !! Read from Registers and memory !! Exchange parameters with the JTAG host !! Display CPU status Refer: http://www.youtube.com/watch?v=IwPWq9m0M6w
Real applications !! DesignVerification/Debug !! Provides control and observation of system under test without need for physical access !! Manufacturing Test !! Provides test and diagnostic capabilities of in-circuit test without need/expense of physical access !! System Configuration Maintenance
References !! http://www.inaccessnetworks.com/ian/projects/ianjtag/ jtag-intro/jtag-intro.html !! http://www.embedded.com/story/OEG20021028S0049 !! http://www.corelis.com/products/ScanExpressJET.htm !! http://www.ee.ic.ac.uk/pcheung/teaching/ee3_DSD/ ti_jtag_seminar.pdf
Thankyou !
Extra Slides
Test Access Ports !! The JTAG Test Access Port (TAP) contains four pins that drive the circuit blocks and control the operations specified.The TAP facilitates the serial loading and unloading of instructions and data. !! Four pins of TAP are: !! TMS – Test mode Select !! TCK – Test Clock !! TDI – Test Data Input !! TDO – Test Data Output
The function of each TAP pin is as follows: !! TCK- this pin is the JTAG test clock. It sequences the TAP controller as well as all of the JTAG registers !! TMS – this pin is the mode input signal to the TAP Controller.The stare of TMS at the rising if TCK determines the sequence of states for the TAP controller. !! TDI – this pin is the serial data input to all JTAG instruction and data registers.TDI is sampled into the JTAG registers on the rising edge of TCK. !! TDO - this pin is serial data output for all JTAG instruction and data registers.TDO changes state on the falling edge of TCK and only active during shifting of data through device.This pin is three-stated at all times.
SECONS JTAG TESTER Source: http://www.jtagtest.com/images/jtagtest_linux.png

Recomendados

Jtag presentation
Jtag presentationJtag presentation
Jtag presentationklinetik
 
Jtagppt
JtagpptJtagppt
JtagpptChiranjeevi Chiru
 
Basics of Functional Verification - Arrow Devices
Basics of Functional Verification - Arrow DevicesBasics of Functional Verification - Arrow Devices
Basics of Functional Verification - Arrow DevicesArrow Devices
 
Verification Challenges and Methodologies
Verification Challenges and MethodologiesVerification Challenges and Methodologies
Verification Challenges and MethodologiesDr. Shivananda Koteshwar
 
The IEEE 1149.1 Boundary-scan test standard
The IEEE 1149.1 Boundary-scan test standardThe IEEE 1149.1 Boundary-scan test standard
The IEEE 1149.1 Boundary-scan test standardJose Manuel Martins Ferreira
 
SOC Verification using SystemVerilog
SOC Verification using SystemVerilog SOC Verification using SystemVerilog
SOC Verification using SystemVerilog Ramdas Mozhikunnath
 
ASIC design verification
ASIC design verificationASIC design verification
ASIC design verificationGireesh Kallihal
 
Introduction to System verilog
Introduction to System verilog Introduction to System verilog
Introduction to System verilog Pushpa Yakkala
 

Recomendados

Jtag presentation
Jtag presentationJtag presentation
Jtag presentationklinetik
 
Jtagppt
JtagpptJtagppt
JtagpptChiranjeevi Chiru
 
Basics of Functional Verification - Arrow Devices
Basics of Functional Verification - Arrow DevicesBasics of Functional Verification - Arrow Devices
Basics of Functional Verification - Arrow DevicesArrow Devices
 
Verification Challenges and Methodologies
Verification Challenges and MethodologiesVerification Challenges and Methodologies
Verification Challenges and MethodologiesDr. Shivananda Koteshwar
 
The IEEE 1149.1 Boundary-scan test standard
The IEEE 1149.1 Boundary-scan test standardThe IEEE 1149.1 Boundary-scan test standard
The IEEE 1149.1 Boundary-scan test standardJose Manuel Martins Ferreira
 
SOC Verification using SystemVerilog
SOC Verification using SystemVerilog SOC Verification using SystemVerilog
SOC Verification using SystemVerilog Ramdas Mozhikunnath
 
ASIC design verification
ASIC design verificationASIC design verification
ASIC design verificationGireesh Kallihal
 
Introduction to System verilog
Introduction to System verilog Introduction to System verilog
Introduction to System verilog Pushpa Yakkala
 
UVM Driver sequencer handshaking
UVM Driver sequencer handshakingUVM Driver sequencer handshaking
UVM Driver sequencer handshakingHARINATH REDDY
 
UVM TUTORIAL;
UVM TUTORIAL;UVM TUTORIAL;
UVM TUTORIAL;Azad Mishra
 
SPI Protocol
SPI ProtocolSPI Protocol
SPI ProtocolAnurag Tomar
 
System verilog important
System verilog importantSystem verilog important
System verilog importantelumalai7
 
dft
dftdft
dftNejeh Ferjani
 
Challenges in Using UVM at SoC Level
Challenges in Using UVM at SoC LevelChallenges in Using UVM at SoC Level
Challenges in Using UVM at SoC LevelDVClub
 
Verification flow and_planning_vlsi_design
Verification flow and_planning_vlsi_designVerification flow and_planning_vlsi_design
Verification flow and_planning_vlsi_designUsha Mehta
 
UVM Methodology Tutorial
UVM Methodology TutorialUVM Methodology Tutorial
UVM Methodology TutorialArrow Devices
 
What is JTAG?
What is JTAG?What is JTAG?
What is JTAG?killerdolton
 
Verification Strategy for PCI-Express
Verification Strategy for PCI-ExpressVerification Strategy for PCI-Express
Verification Strategy for PCI-ExpressDVClub
 
Level sensitive scan design(LSSD) and Boundry scan(BS)
Level sensitive scan design(LSSD) and Boundry scan(BS)Level sensitive scan design(LSSD) and Boundry scan(BS)
Level sensitive scan design(LSSD) and Boundry scan(BS)Praveen Kumar
 
2019 2 testing and verification of vlsi design_verification
2019 2 testing and verification of vlsi design_verification2019 2 testing and verification of vlsi design_verification
2019 2 testing and verification of vlsi design_verificationUsha Mehta
 
UVM Update: Register Package
UVM Update: Register PackageUVM Update: Register Package
UVM Update: Register PackageDVClub
 
System verilog coverage
System verilog coverageSystem verilog coverage
System verilog coveragePushpa Yakkala
 
Pcie basic
Pcie basicPcie basic
Pcie basicSaifuddin Kaijar
 
verification_planning_systemverilog_uvm_2020
verification_planning_systemverilog_uvm_2020verification_planning_systemverilog_uvm_2020
verification_planning_systemverilog_uvm_2020Sameh El-Ashry
 
PCIe DL_layer_3.0.1 (1)
PCIe DL_layer_3.0.1 (1)PCIe DL_layer_3.0.1 (1)
PCIe DL_layer_3.0.1 (1)Rakeshkumar Sachdev
 
Verification challenges and methodologies - SoC and ASICs
Verification challenges and methodologies - SoC and ASICsVerification challenges and methodologies - SoC and ASICs
Verification challenges and methodologies - SoC and ASICsDr. Shivananda Koteshwar
 
Uvm presentation dac2011_final
Uvm presentation dac2011_finalUvm presentation dac2011_final
Uvm presentation dac2011_finalsean chen
 
Boundary Scan Basics - x1149 de Keysight
Boundary Scan Basics - x1149 de KeysightBoundary Scan Basics - x1149 de Keysight
Boundary Scan Basics - x1149 de KeysightInterlatin
 
JTAG
JTAGJTAG
JTAGzomrolion
 
Prezentare tcs2011
Prezentare tcs2011Prezentare tcs2011
Prezentare tcs2011Alexandru IOVANOVICI
 

Mais conteúdo relacionado

Mais procurados

UVM Driver sequencer handshaking
UVM Driver sequencer handshakingUVM Driver sequencer handshaking
UVM Driver sequencer handshakingHARINATH REDDY
 
System verilog important
System verilog importantSystem verilog important
System verilog importantelumalai7
 
Challenges in Using UVM at SoC Level
Challenges in Using UVM at SoC LevelChallenges in Using UVM at SoC Level
Challenges in Using UVM at SoC LevelDVClub
 
Verification flow and_planning_vlsi_design
Verification flow and_planning_vlsi_designVerification flow and_planning_vlsi_design
Verification flow and_planning_vlsi_designUsha Mehta
 
UVM Methodology Tutorial
UVM Methodology TutorialUVM Methodology Tutorial
UVM Methodology TutorialArrow Devices
 
Verification Strategy for PCI-Express
Verification Strategy for PCI-ExpressVerification Strategy for PCI-Express
Verification Strategy for PCI-ExpressDVClub
 
Level sensitive scan design(LSSD) and Boundry scan(BS)
Level sensitive scan design(LSSD) and Boundry scan(BS)Level sensitive scan design(LSSD) and Boundry scan(BS)
Level sensitive scan design(LSSD) and Boundry scan(BS)Praveen Kumar
 
2019 2 testing and verification of vlsi design_verification
2019 2 testing and verification of vlsi design_verification2019 2 testing and verification of vlsi design_verification
2019 2 testing and verification of vlsi design_verificationUsha Mehta
 
UVM Update: Register Package
UVM Update: Register PackageUVM Update: Register Package
UVM Update: Register PackageDVClub
 
System verilog coverage
System verilog coverageSystem verilog coverage
System verilog coveragePushpa Yakkala
 
verification_planning_systemverilog_uvm_2020
verification_planning_systemverilog_uvm_2020verification_planning_systemverilog_uvm_2020
verification_planning_systemverilog_uvm_2020Sameh El-Ashry
 
Verification challenges and methodologies - SoC and ASICs
Verification challenges and methodologies - SoC and ASICsVerification challenges and methodologies - SoC and ASICs
Verification challenges and methodologies - SoC and ASICsDr. Shivananda Koteshwar
 
Uvm presentation dac2011_final
Uvm presentation dac2011_finalUvm presentation dac2011_final
Uvm presentation dac2011_finalsean chen
 
Boundary Scan Basics - x1149 de Keysight
Boundary Scan Basics - x1149 de KeysightBoundary Scan Basics - x1149 de Keysight
Boundary Scan Basics - x1149 de KeysightInterlatin
 

Mais procurados (20)

UVM Driver sequencer handshaking
UVM Driver sequencer handshakingUVM Driver sequencer handshaking
UVM Driver sequencer handshaking
 
UVM TUTORIAL;
UVM TUTORIAL;UVM TUTORIAL;
UVM TUTORIAL;
 
SPI Protocol
SPI ProtocolSPI Protocol
SPI Protocol
 
System verilog important
System verilog importantSystem verilog important
System verilog important
 
dft
dftdft
dft
 
Challenges in Using UVM at SoC Level
Challenges in Using UVM at SoC LevelChallenges in Using UVM at SoC Level
Challenges in Using UVM at SoC Level
 
Verification flow and_planning_vlsi_design
Verification flow and_planning_vlsi_designVerification flow and_planning_vlsi_design
Verification flow and_planning_vlsi_design
 
UVM Methodology Tutorial
UVM Methodology TutorialUVM Methodology Tutorial
UVM Methodology Tutorial
 
What is JTAG?
What is JTAG?What is JTAG?
What is JTAG?
 
Verification Strategy for PCI-Express
Verification Strategy for PCI-ExpressVerification Strategy for PCI-Express
Verification Strategy for PCI-Express
 
Level sensitive scan design(LSSD) and Boundry scan(BS)
Level sensitive scan design(LSSD) and Boundry scan(BS)Level sensitive scan design(LSSD) and Boundry scan(BS)
Level sensitive scan design(LSSD) and Boundry scan(BS)
 
2019 2 testing and verification of vlsi design_verification
2019 2 testing and verification of vlsi design_verification2019 2 testing and verification of vlsi design_verification
2019 2 testing and verification of vlsi design_verification
 
UVM Update: Register Package
UVM Update: Register PackageUVM Update: Register Package
UVM Update: Register Package
 
System verilog coverage
System verilog coverageSystem verilog coverage
System verilog coverage
 
Pcie basic
Pcie basicPcie basic
Pcie basic
 
verification_planning_systemverilog_uvm_2020
verification_planning_systemverilog_uvm_2020verification_planning_systemverilog_uvm_2020
verification_planning_systemverilog_uvm_2020
 
PCIe DL_layer_3.0.1 (1)
PCIe DL_layer_3.0.1 (1)PCIe DL_layer_3.0.1 (1)
PCIe DL_layer_3.0.1 (1)
 
Verification challenges and methodologies - SoC and ASICs
Verification challenges and methodologies - SoC and ASICsVerification challenges and methodologies - SoC and ASICs
Verification challenges and methodologies - SoC and ASICs
 
Uvm presentation dac2011_final
Uvm presentation dac2011_finalUvm presentation dac2011_final
Uvm presentation dac2011_final
 
Boundary Scan Basics - x1149 de Keysight
Boundary Scan Basics - x1149 de KeysightBoundary Scan Basics - x1149 de Keysight
Boundary Scan Basics - x1149 de Keysight
 

Semelhante a JTAG Interface (Intro)

One integrated platform for all activities,from engineering to production
One integrated platform for all activities,from engineering to productionOne integrated platform for all activities,from engineering to production
One integrated platform for all activities,from engineering to productionS Jebaraj
 
IRJET- PCB Test, Debug & Programming Made Easy with Universal Test Jig
IRJET- PCB Test, Debug & Programming Made Easy with Universal Test JigIRJET- PCB Test, Debug & Programming Made Easy with Universal Test Jig
IRJET- PCB Test, Debug & Programming Made Easy with Universal Test JigIRJET Journal
 
GOEPEL Electronics TAP Checker
GOEPEL Electronics TAP CheckerGOEPEL Electronics TAP Checker
GOEPEL Electronics TAP CheckerGOEPEL Electronics
 
UGM 2015: X1149 workshop
UGM 2015: X1149 workshopUGM 2015: X1149 workshop
UGM 2015: X1149 workshopInterlatin
 
Bsides Puerto Rico-2017
Bsides Puerto Rico-2017Bsides Puerto Rico-2017
Bsides Puerto Rico-2017Price McDonald
 
ARM® Cortex™ M Bootup_CMSIS_Part_3_3_Debug_Architecture
ARM® Cortex™ M Bootup_CMSIS_Part_3_3_Debug_ArchitectureARM® Cortex™ M Bootup_CMSIS_Part_3_3_Debug_Architecture
ARM® Cortex™ M Bootup_CMSIS_Part_3_3_Debug_ArchitectureRaahul Raghavan
 
System Development for Verification of General Purpose Input Output
System Development for Verification of General Purpose Input OutputSystem Development for Verification of General Purpose Input Output
System Development for Verification of General Purpose Input OutputRSIS International
 
IEEE 2014 JAVA NETWORKING PROJECTS Automatic test packet generation
IEEE 2014 JAVA NETWORKING PROJECTS Automatic test packet generationIEEE 2014 JAVA NETWORKING PROJECTS Automatic test packet generation
IEEE 2014 JAVA NETWORKING PROJECTS Automatic test packet generationIEEEGLOBALSOFTSTUDENTPROJECTS
 
2014 IEEE JAVA NETWORKING PROJECT Automatic test packet generation
2014 IEEE JAVA NETWORKING PROJECT Automatic test packet generation2014 IEEE JAVA NETWORKING PROJECT Automatic test packet generation
2014 IEEE JAVA NETWORKING PROJECT Automatic test packet generationIEEEFINALSEMSTUDENTSPROJECTS
 
CNIT 140: Flashing Firmware
CNIT 140: Flashing FirmwareCNIT 140: Flashing Firmware
CNIT 140: Flashing FirmwareSam Bowne
 
IMAGE CAPTURE, PROCESSING AND TRANSFER VIA ETHERNET UNDER CONTROL OF MATLAB G...
IMAGE CAPTURE, PROCESSING AND TRANSFER VIA ETHERNET UNDER CONTROL OF MATLAB G...IMAGE CAPTURE, PROCESSING AND TRANSFER VIA ETHERNET UNDER CONTROL OF MATLAB G...
IMAGE CAPTURE, PROCESSING AND TRANSFER VIA ETHERNET UNDER CONTROL OF MATLAB G...Christopher Diamantopoulos
 
Brain wave controlled robot
Brain wave controlled robotBrain wave controlled robot
Brain wave controlled robotRahul Wagh
 

Semelhante a JTAG Interface (Intro) (20)

JTAG
JTAGJTAG
JTAG
 
Prezentare tcs2011
Prezentare tcs2011Prezentare tcs2011
Prezentare tcs2011
 
One integrated platform for all activities,from engineering to production
One integrated platform for all activities,from engineering to productionOne integrated platform for all activities,from engineering to production
One integrated platform for all activities,from engineering to production
 
IRJET- PCB Test, Debug & Programming Made Easy with Universal Test Jig
IRJET- PCB Test, Debug & Programming Made Easy with Universal Test JigIRJET- PCB Test, Debug & Programming Made Easy with Universal Test Jig
IRJET- PCB Test, Debug & Programming Made Easy with Universal Test Jig
 
What is JTAG..pdf
What is JTAG..pdfWhat is JTAG..pdf
What is JTAG..pdf
 
GOEPEL Electronics TAP Checker
GOEPEL Electronics TAP CheckerGOEPEL Electronics TAP Checker
GOEPEL Electronics TAP Checker
 
UGM 2015: X1149 workshop
UGM 2015: X1149 workshopUGM 2015: X1149 workshop
UGM 2015: X1149 workshop
 
Bsides Puerto Rico-2017
Bsides Puerto Rico-2017Bsides Puerto Rico-2017
Bsides Puerto Rico-2017
 
ARM® Cortex™ M Bootup_CMSIS_Part_3_3_Debug_Architecture
ARM® Cortex™ M Bootup_CMSIS_Part_3_3_Debug_ArchitectureARM® Cortex™ M Bootup_CMSIS_Part_3_3_Debug_Architecture
ARM® Cortex™ M Bootup_CMSIS_Part_3_3_Debug_Architecture
 
System Development for Verification of General Purpose Input Output
System Development for Verification of General Purpose Input OutputSystem Development for Verification of General Purpose Input Output
System Development for Verification of General Purpose Input Output
 
JTAG
JTAGJTAG
JTAG
 
JTAG-Technical-Primer.pdf
JTAG-Technical-Primer.pdfJTAG-Technical-Primer.pdf
JTAG-Technical-Primer.pdf
 
IEEE 2014 JAVA NETWORKING PROJECTS Automatic test packet generation
IEEE 2014 JAVA NETWORKING PROJECTS Automatic test packet generationIEEE 2014 JAVA NETWORKING PROJECTS Automatic test packet generation
IEEE 2014 JAVA NETWORKING PROJECTS Automatic test packet generation
 
2014 IEEE JAVA NETWORKING PROJECT Automatic test packet generation
2014 IEEE JAVA NETWORKING PROJECT Automatic test packet generation2014 IEEE JAVA NETWORKING PROJECT Automatic test packet generation
2014 IEEE JAVA NETWORKING PROJECT Automatic test packet generation
 
CNIT 140: Flashing Firmware
CNIT 140: Flashing FirmwareCNIT 140: Flashing Firmware
CNIT 140: Flashing Firmware
 
IMAGE CAPTURE, PROCESSING AND TRANSFER VIA ETHERNET UNDER CONTROL OF MATLAB G...
IMAGE CAPTURE, PROCESSING AND TRANSFER VIA ETHERNET UNDER CONTROL OF MATLAB G...IMAGE CAPTURE, PROCESSING AND TRANSFER VIA ETHERNET UNDER CONTROL OF MATLAB G...
IMAGE CAPTURE, PROCESSING AND TRANSFER VIA ETHERNET UNDER CONTROL OF MATLAB G...
 
Embest s3 cev40 _neomore
Embest s3 cev40 _neomoreEmbest s3 cev40 _neomore
Embest s3 cev40 _neomore
 
Soc.pptx
Soc.pptxSoc.pptx
Soc.pptx
 
Brain wave controlled robot
Brain wave controlled robotBrain wave controlled robot
Brain wave controlled robot
 
40120140504013
4012014050401340120140504013
40120140504013
 

Mais de Nitesh Bhatia

Cost Estimation in Project Management - Case of Solar Assisted Water Pump
Cost Estimation in Project Management - Case of Solar Assisted Water PumpCost Estimation in Project Management - Case of Solar Assisted Water Pump
Cost Estimation in Project Management - Case of Solar Assisted Water PumpNitesh Bhatia
 
Volume Rendering of Unstructured Tetrahedral Grids using Intel / nVidia OpenCL
Volume Rendering of Unstructured Tetrahedral Grids using Intel / nVidia OpenCLVolume Rendering of Unstructured Tetrahedral Grids using Intel / nVidia OpenCL
Volume Rendering of Unstructured Tetrahedral Grids using Intel / nVidia OpenCLNitesh Bhatia
 
Solution Neutral Problem Statement (SNPS) Generation (Example - Cooking India...
Solution Neutral Problem Statement (SNPS) Generation (Example - Cooking India...Solution Neutral Problem Statement (SNPS) Generation (Example - Cooking India...
Solution Neutral Problem Statement (SNPS) Generation (Example - Cooking India...Nitesh Bhatia
 
Mapping - Reality and Virtual Reality (Strictly No AR!!)
Mapping - Reality and Virtual Reality (Strictly No AR!!)Mapping - Reality and Virtual Reality (Strictly No AR!!)
Mapping - Reality and Virtual Reality (Strictly No AR!!)Nitesh Bhatia
 
Natural User Interface Demo based on - 3D Brick Game using Kinect
Natural User Interface Demo based on - 3D Brick Game using KinectNatural User Interface Demo based on - 3D Brick Game using Kinect
Natural User Interface Demo based on - 3D Brick Game using KinectNitesh Bhatia
 
iKeymote - Internet Keyboard cum Remote (Idea Design)
iKeymote - Internet Keyboard cum Remote (Idea Design)iKeymote - Internet Keyboard cum Remote (Idea Design)
iKeymote - Internet Keyboard cum Remote (Idea Design)Nitesh Bhatia
 
Visual space perception
Visual space perceptionVisual space perception
Visual space perceptionNitesh Bhatia
 
PPT- Chaos Prediction using Visual Surveillance and Network Computing
PPT- Chaos Prediction using Visual Surveillance and Network ComputingPPT- Chaos Prediction using Visual Surveillance and Network Computing
PPT- Chaos Prediction using Visual Surveillance and Network ComputingNitesh Bhatia
 
Lecture 1 - Web Engineering - Apple iClub at DA-IICT
Lecture 1 - Web Engineering - Apple iClub at DA-IICTLecture 1 - Web Engineering - Apple iClub at DA-IICT
Lecture 1 - Web Engineering - Apple iClub at DA-IICTNitesh Bhatia
 
Introduction to Lectures in Apple iClub at DA-IICT
Introduction to Lectures in Apple iClub at DA-IICTIntroduction to Lectures in Apple iClub at DA-IICT
Introduction to Lectures in Apple iClub at DA-IICTNitesh Bhatia
 
Apple iClub at DA-IICT Opening PPT
Apple iClub at DA-IICT Opening PPTApple iClub at DA-IICT Opening PPT
Apple iClub at DA-IICT Opening PPTNitesh Bhatia
 
Design Flaws In Products
Design Flaws In ProductsDesign Flaws In Products
Design Flaws In ProductsNitesh Bhatia
 

Mais de Nitesh Bhatia (13)

Cost Estimation in Project Management - Case of Solar Assisted Water Pump
Cost Estimation in Project Management - Case of Solar Assisted Water PumpCost Estimation in Project Management - Case of Solar Assisted Water Pump
Cost Estimation in Project Management - Case of Solar Assisted Water Pump
 
Volume Rendering of Unstructured Tetrahedral Grids using Intel / nVidia OpenCL
Volume Rendering of Unstructured Tetrahedral Grids using Intel / nVidia OpenCLVolume Rendering of Unstructured Tetrahedral Grids using Intel / nVidia OpenCL
Volume Rendering of Unstructured Tetrahedral Grids using Intel / nVidia OpenCL
 
Solution Neutral Problem Statement (SNPS) Generation (Example - Cooking India...
Solution Neutral Problem Statement (SNPS) Generation (Example - Cooking India...Solution Neutral Problem Statement (SNPS) Generation (Example - Cooking India...
Solution Neutral Problem Statement (SNPS) Generation (Example - Cooking India...
 
Mapping - Reality and Virtual Reality (Strictly No AR!!)
Mapping - Reality and Virtual Reality (Strictly No AR!!)Mapping - Reality and Virtual Reality (Strictly No AR!!)
Mapping - Reality and Virtual Reality (Strictly No AR!!)
 
Natural User Interface Demo based on - 3D Brick Game using Kinect
Natural User Interface Demo based on - 3D Brick Game using KinectNatural User Interface Demo based on - 3D Brick Game using Kinect
Natural User Interface Demo based on - 3D Brick Game using Kinect
 
iKeymote - Internet Keyboard cum Remote (Idea Design)
iKeymote - Internet Keyboard cum Remote (Idea Design)iKeymote - Internet Keyboard cum Remote (Idea Design)
iKeymote - Internet Keyboard cum Remote (Idea Design)
 
Visual space perception
Visual space perceptionVisual space perception
Visual space perception
 
PPT- Chaos Prediction using Visual Surveillance and Network Computing
PPT- Chaos Prediction using Visual Surveillance and Network ComputingPPT- Chaos Prediction using Visual Surveillance and Network Computing
PPT- Chaos Prediction using Visual Surveillance and Network Computing
 
Give up - Orkut App
Give up - Orkut AppGive up - Orkut App
Give up - Orkut App
 
Lecture 1 - Web Engineering - Apple iClub at DA-IICT
Lecture 1 - Web Engineering - Apple iClub at DA-IICTLecture 1 - Web Engineering - Apple iClub at DA-IICT
Lecture 1 - Web Engineering - Apple iClub at DA-IICT
 
Introduction to Lectures in Apple iClub at DA-IICT
Introduction to Lectures in Apple iClub at DA-IICTIntroduction to Lectures in Apple iClub at DA-IICT
Introduction to Lectures in Apple iClub at DA-IICT
 
Apple iClub at DA-IICT Opening PPT
Apple iClub at DA-IICT Opening PPTApple iClub at DA-IICT Opening PPT
Apple iClub at DA-IICT Opening PPT
 
Design Flaws In Products
Design Flaws In ProductsDesign Flaws In Products
Design Flaws In Products
 

Último

Textual Evidence in Reading and Writing of SHS
Textual Evidence in Reading and Writing of SHSTextual Evidence in Reading and Writing of SHS
Textual Evidence in Reading and Writing of SHSMae Pangan
 
ANG SEKTOR NG agrikultura.pptx QUARTER 4
ANG SEKTOR NG agrikultura.pptx QUARTER 4ANG SEKTOR NG agrikultura.pptx QUARTER 4
ANG SEKTOR NG agrikultura.pptx QUARTER 4MiaBumagat1
 
How to Add Barcode on PDF Report in Odoo 17
How to Add Barcode on PDF Report in Odoo 17How to Add Barcode on PDF Report in Odoo 17
How to Add Barcode on PDF Report in Odoo 17Celine George
 
How to do quick user assign in kanban in Odoo 17 ERP
How to do quick user assign in kanban in Odoo 17 ERPHow to do quick user assign in kanban in Odoo 17 ERP
How to do quick user assign in kanban in Odoo 17 ERPCeline George
 
Millenials and Fillennials (Ethical Challenge and Responses).pptx
Millenials and Fillennials (Ethical Challenge and Responses).pptxMillenials and Fillennials (Ethical Challenge and Responses).pptx
Millenials and Fillennials (Ethical Challenge and Responses).pptxJanEmmanBrigoli
 
Visit to a blind student's school🧑‍🦯🧑‍🦯(community medicine)
Visit to a blind student's school🧑‍🦯🧑‍🦯(community medicine)Visit to a blind student's school🧑‍🦯🧑‍🦯(community medicine)
Visit to a blind student's school🧑‍🦯🧑‍🦯(community medicine)lakshayb543
 
Oppenheimer Film Discussion for Philosophy and Film
Oppenheimer Film Discussion for Philosophy and FilmOppenheimer Film Discussion for Philosophy and Film
Oppenheimer Film Discussion for Philosophy and FilmStan Meyer
 
4.16.24 21st Century Movements for Black Lives.pptx
4.16.24 21st Century Movements for Black Lives.pptx4.16.24 21st Century Movements for Black Lives.pptx
4.16.24 21st Century Movements for Black Lives.pptxmary850239
 
Influencing policy (training slides from Fast Track Impact)
Influencing policy (training slides from Fast Track Impact)Influencing policy (training slides from Fast Track Impact)
Influencing policy (training slides from Fast Track Impact)Mark Reed
 
4.16.24 Poverty and Precarity--Desmond.pptx
4.16.24 Poverty and Precarity--Desmond.pptx4.16.24 Poverty and Precarity--Desmond.pptx
4.16.24 Poverty and Precarity--Desmond.pptxmary850239
 
ENG 5 Q4 WEEk 1 DAY 1 Restate sentences heard in one’s own words. Use appropr...
ENG 5 Q4 WEEk 1 DAY 1 Restate sentences heard in one’s own words. Use appropr...ENG 5 Q4 WEEk 1 DAY 1 Restate sentences heard in one’s own words. Use appropr...
ENG 5 Q4 WEEk 1 DAY 1 Restate sentences heard in one’s own words. Use appropr...JojoEDelaCruz
 
Inclusivity Essentials_ Creating Accessible Websites for Nonprofits .pdf
Inclusivity Essentials_ Creating Accessible Websites for Nonprofits .pdfInclusivity Essentials_ Creating Accessible Websites for Nonprofits .pdf
Inclusivity Essentials_ Creating Accessible Websites for Nonprofits .pdfTechSoup
 
Concurrency Control in Database Management system
Concurrency Control in Database Management systemConcurrency Control in Database Management system
Concurrency Control in Database Management systemChristalin Nelson
 
Activity 2-unit 2-update 2024. English translation
Activity 2-unit 2-update 2024. English translationActivity 2-unit 2-update 2024. English translation
Activity 2-unit 2-update 2024. English translationRosabel UA
 
Dust Of Snow By Robert Frost Class-X English CBSE
Dust Of Snow By Robert Frost Class-X English CBSEDust Of Snow By Robert Frost Class-X English CBSE
Dust Of Snow By Robert Frost Class-X English CBSEaurabinda banchhor
 
MULTIDISCIPLINRY NATURE OF THE ENVIRONMENTAL STUDIES.pptx
MULTIDISCIPLINRY NATURE OF THE ENVIRONMENTAL STUDIES.pptxMULTIDISCIPLINRY NATURE OF THE ENVIRONMENTAL STUDIES.pptx
MULTIDISCIPLINRY NATURE OF THE ENVIRONMENTAL STUDIES.pptxAnupkumar Sharma
 
Transaction Management in Database Management System
Transaction Management in Database Management SystemTransaction Management in Database Management System
Transaction Management in Database Management SystemChristalin Nelson
 

Último (20)

Textual Evidence in Reading and Writing of SHS
Textual Evidence in Reading and Writing of SHSTextual Evidence in Reading and Writing of SHS
Textual Evidence in Reading and Writing of SHS
 
ANG SEKTOR NG agrikultura.pptx QUARTER 4
ANG SEKTOR NG agrikultura.pptx QUARTER 4ANG SEKTOR NG agrikultura.pptx QUARTER 4
ANG SEKTOR NG agrikultura.pptx QUARTER 4
 
How to Add Barcode on PDF Report in Odoo 17
How to Add Barcode on PDF Report in Odoo 17How to Add Barcode on PDF Report in Odoo 17
How to Add Barcode on PDF Report in Odoo 17
 
FINALS_OF_LEFT_ON_C'N_EL_DORADO_2024.pptx
FINALS_OF_LEFT_ON_C'N_EL_DORADO_2024.pptxFINALS_OF_LEFT_ON_C'N_EL_DORADO_2024.pptx
FINALS_OF_LEFT_ON_C'N_EL_DORADO_2024.pptx
 
How to do quick user assign in kanban in Odoo 17 ERP
How to do quick user assign in kanban in Odoo 17 ERPHow to do quick user assign in kanban in Odoo 17 ERP
How to do quick user assign in kanban in Odoo 17 ERP
 
YOUVE_GOT_EMAIL_PRELIMS_EL_DORADO_2024.pptx
YOUVE_GOT_EMAIL_PRELIMS_EL_DORADO_2024.pptxYOUVE_GOT_EMAIL_PRELIMS_EL_DORADO_2024.pptx
YOUVE_GOT_EMAIL_PRELIMS_EL_DORADO_2024.pptx
 
Millenials and Fillennials (Ethical Challenge and Responses).pptx
Millenials and Fillennials (Ethical Challenge and Responses).pptxMillenials and Fillennials (Ethical Challenge and Responses).pptx
Millenials and Fillennials (Ethical Challenge and Responses).pptx
 
Visit to a blind student's school🧑‍🦯🧑‍🦯(community medicine)
Visit to a blind student's school🧑‍🦯🧑‍🦯(community medicine)Visit to a blind student's school🧑‍🦯🧑‍🦯(community medicine)
Visit to a blind student's school🧑‍🦯🧑‍🦯(community medicine)
 
Oppenheimer Film Discussion for Philosophy and Film
Oppenheimer Film Discussion for Philosophy and FilmOppenheimer Film Discussion for Philosophy and Film
Oppenheimer Film Discussion for Philosophy and Film
 
4.16.24 21st Century Movements for Black Lives.pptx
4.16.24 21st Century Movements for Black Lives.pptx4.16.24 21st Century Movements for Black Lives.pptx
4.16.24 21st Century Movements for Black Lives.pptx
 
Influencing policy (training slides from Fast Track Impact)
Influencing policy (training slides from Fast Track Impact)Influencing policy (training slides from Fast Track Impact)
Influencing policy (training slides from Fast Track Impact)
 
4.16.24 Poverty and Precarity--Desmond.pptx
4.16.24 Poverty and Precarity--Desmond.pptx4.16.24 Poverty and Precarity--Desmond.pptx
4.16.24 Poverty and Precarity--Desmond.pptx
 
ENG 5 Q4 WEEk 1 DAY 1 Restate sentences heard in one’s own words. Use appropr...
ENG 5 Q4 WEEk 1 DAY 1 Restate sentences heard in one’s own words. Use appropr...ENG 5 Q4 WEEk 1 DAY 1 Restate sentences heard in one’s own words. Use appropr...
ENG 5 Q4 WEEk 1 DAY 1 Restate sentences heard in one’s own words. Use appropr...
 
Inclusivity Essentials_ Creating Accessible Websites for Nonprofits .pdf
Inclusivity Essentials_ Creating Accessible Websites for Nonprofits .pdfInclusivity Essentials_ Creating Accessible Websites for Nonprofits .pdf
Inclusivity Essentials_ Creating Accessible Websites for Nonprofits .pdf
 
Concurrency Control in Database Management system
Concurrency Control in Database Management systemConcurrency Control in Database Management system
Concurrency Control in Database Management system
 
Activity 2-unit 2-update 2024. English translation
Activity 2-unit 2-update 2024. English translationActivity 2-unit 2-update 2024. English translation
Activity 2-unit 2-update 2024. English translation
 
Dust Of Snow By Robert Frost Class-X English CBSE
Dust Of Snow By Robert Frost Class-X English CBSEDust Of Snow By Robert Frost Class-X English CBSE
Dust Of Snow By Robert Frost Class-X English CBSE
 
INCLUSIVE EDUCATION PRACTICES FOR TEACHERS AND TRAINERS.pptx
INCLUSIVE EDUCATION PRACTICES FOR TEACHERS AND TRAINERS.pptxINCLUSIVE EDUCATION PRACTICES FOR TEACHERS AND TRAINERS.pptx
INCLUSIVE EDUCATION PRACTICES FOR TEACHERS AND TRAINERS.pptx
 
MULTIDISCIPLINRY NATURE OF THE ENVIRONMENTAL STUDIES.pptx
MULTIDISCIPLINRY NATURE OF THE ENVIRONMENTAL STUDIES.pptxMULTIDISCIPLINRY NATURE OF THE ENVIRONMENTAL STUDIES.pptx
MULTIDISCIPLINRY NATURE OF THE ENVIRONMENTAL STUDIES.pptx
 
Transaction Management in Database Management System
Transaction Management in Database Management SystemTransaction Management in Database Management System
Transaction Management in Database Management System
 

JTAG Interface (Intro)

  • 1. JTAG Interface Nitesh Bhatia- 200501071 Embedded Systems | DA-IICT | 2009 Joint Test Action Group
  • 2. Outline !! Background – need for JTAG !! JTAG and Boundary Scan !! Advantages !! Atmel ICE mk-II and gdb !! Real JTAG Applications
  • 3. Bed of Nails fixture !! PCB testing was done using Bed of Nails in circuit testing.
  • 4. Past to Future – Testing !! Miniaturization results in loss of test access Yesterday TomorrowToday
  • 5. Circuit Complexity / Cost !! Increasing integration at chip level complicates controllability. Yesterday Today
  • 6. JTAG (1149.1 Standard) !! IEEE 1149.1, a standard 5-pin serial protocol that established the details of access to any chip with JTAG port. !! Features: !! Boundary scan testing of ICs !! Debug Embedded devices !! System level debug capability
  • 7. JTAG – Boundary Scan !! Boundary scan is a methodology allowing complete controllability and observablity of the boundary pins of a JTAG compatible device via software control.
  • 8. Boundary Scan Principle The top level schematic of test logic defined by IEEE Std 1149.1 includes three key blocks: !! The TAP Controller !! This responds to the control sequences supplied through the test access port (TAP) and generates the clock and control signals required for correct operation of the circuit blocks !! The Instruction Register !! This shift register-based circuit is serially loaded with the instructions that selects an operation to be performed !! The Data Registers !! These are a bank of shift register based circuits.The stimuli required by an operation are serially loaded into the data registers selected by the current instruction. Following execution of the operation, results can be shifted out for examination.
  • 9. What can it be used for !! The standard defines instructions that can be used to perform !! Functional Tests !! Interconnect Tests !! Built-in self test procedures
  • 10. Advantages !! Need for physical test points on board is eliminated => simpler board layouts !! Cheap test fixtures !! Reduced time on in-circuit test systems !! Increased use of standard interfaces !! Faster time-to-market
  • 11. Widespread uses !! A large proportion of high end embedded systems have a JTAG port. !! The PCI bus connector standard contains optional JTAG signals (pins 1-5); PCI-Express contains JTAG signals (pins 5-9).A special JTAG card can be used to re-flash a corrupt BIOS. !! Almost all FPGAs and CPLDs used today can be programmed via the JTAG port.
  • 12. JTAG Software !! Open Source !! UrJTAG project supports many JTAG tools, processors, and boards. !! OpenOCD project supports various inexpensive JTAG adapters including USB ones based on FT2232 chips, and is mostly used with ARM projects. It provides GDB and telnet interfaces, both from Linux and from MS-Windows. !! Freeware !! Atmel provides AVR Studio on MS-Windows, for AVR8 microcontrollers, and a cross-platform AVR32studio product to support AVR32 systems. !! Xilinx provides lower end FPGA development tools at no cost !! HappyJTAG2 is embedded JTAG solution with FT2232 chip for AVR8 microcontrollers and Atmel AVR Studio on MS-Windows.
  • 14. JTAG ICE mkII and gdb. !! Functions - !! Run !! Stop !! Step !! Write to Registers and memory !! Read from Registers and memory !! Exchange parameters with the JTAG host !! Display CPU status Refer: http://www.youtube.com/watch?v=IwPWq9m0M6w
  • 15. Real applications !! DesignVerification/Debug !! Provides control and observation of system under test without need for physical access !! Manufacturing Test !! Provides test and diagnostic capabilities of in-circuit test without need/expense of physical access !! System Configuration Maintenance
  • 16. References !! http://www.inaccessnetworks.com/ian/projects/ianjtag/ jtag-intro/jtag-intro.html !! http://www.embedded.com/story/OEG20021028S0049 !! http://www.corelis.com/products/ScanExpressJET.htm !! http://www.ee.ic.ac.uk/pcheung/teaching/ee3_DSD/ ti_jtag_seminar.pdf
  • 19. Test Access Ports !! The JTAG Test Access Port (TAP) contains four pins that drive the circuit blocks and control the operations specified.The TAP facilitates the serial loading and unloading of instructions and data. !! Four pins of TAP are: !! TMS – Test mode Select !! TCK – Test Clock !! TDI – Test Data Input !! TDO – Test Data Output
  • 20. The function of each TAP pin is as follows: !! TCK- this pin is the JTAG test clock. It sequences the TAP controller as well as all of the JTAG registers !! TMS – this pin is the mode input signal to the TAP Controller.The stare of TMS at the rising if TCK determines the sequence of states for the TAP controller. !! TDI – this pin is the serial data input to all JTAG instruction and data registers.TDI is sampled into the JTAG registers on the rising edge of TCK. !! TDO - this pin is serial data output for all JTAG instruction and data registers.TDO changes state on the falling edge of TCK and only active during shifting of data through device.This pin is three-stated at all times.
  • 21. SECONS JTAG TESTER Source: http://www.jtagtest.com/images/jtagtest_linux.png