1. VLSI email id:vlsi@pantechmail.com
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Sl.No Topic Field
PSVLSI001 Pipelined Radix-2k
Feed forward FFT Architectures
IEEE2013
CommunicationSystems,ArchitecturalDesignsand
ProtocolDesigns
PSVLSI002 Design of High Speed Low Power Viterbi Decoder for TCM System
PSVLSI003 An Efficient SQRT Architecture of Carry Select Adder Design by Common Boolean Logic
PSVLSI004 FFT Architectures for Real-Valued Signals Based on Radix-23
& Radix-24
Algorithms
PSVLSI005 Achieving Reduced Area By Multi-Bit Flip Flop Design
PSVLSI006 High-Throughput Compact Delay-Insensitive Asynchronous NOC Router
PSVLSI007 Design of Low Energy, High Performance Synchronous and Asynchronous 64-PointFFT
PSVLSI008 An Efficient High Speed Wallace Tree Multiplier
PSVLSI009 Design and Implementation of 32 Bit Unsigned Multiplier Using CLAA and CSLA
PSVLSI010 Real Time Communication between Multiple FPGA Systems in Multitasking Environment
Using RTOS
PSVLSI011 Low-Power Digital Signal Processing Using Approximate Adders
PSVLSI012 Performance Evaluation of FFT Processor Using Conventional and VedicAlgorithm
PSVLSI013 A Novel Transistor Level Realization of Ultra Low Power High-Speed Adiabatic Vedic
Multiplier
IEEE2013
LowPowerDesign(Memories,Flip-Flops,Counters,AritmeticCoresand
AnalogandDigitalCircuitsDesign)
PSVLSI014 Low-Power Digital Signal Processing Using Approximate Adders
PSVLSI015 Asynchronous Fine-Grain Power-Gated Logic
PSVLSI016 Comparison of Static and Dynamic Printed Organic Shift Registers
PSVLSI017 A 10-T SRAM cell with Inbuilt Charge Sharing for Dynamic Power Reduction
PSVLSI018 Sub threshold Dual Mode Logic
PSVLSI019 Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating
PSVLSI020 A High Performance D-Flip Flop Design with Low Power Clocking System using MTCMOS
PSVLSI021 A Low Power Fault Tolerant Reversible Decoder Using MOS Transistor
PSVLSI022 Performance Analysis of a New CMOS Output Buffer
PSVLSI023 A Current-Starved Inverter-Based Differential Amplifier Design for Ultra-Low Power
Applications
PSVLSI024 A low power single phase clock distribution using VLSI technology
PSVLSI025 Reduction of Leakage Current and Power in Full Subtractor Using MTCMOS Technique
PSVLSI026 Design of Low Power Sequential Circuit Using Clocked Pair Shared Flip flop
PSVLSI027 Asynchronous Design of Energy Efficient Full Adder
PSVLSI028 Hardware Implementation of a Digital Watermarking System for Video Authentication
IEEE2013
DigitalImageProcessing
Applications(Steganography,
Surveillance
termarkingmentation,
Enhancement)
PSVLSI029 Reconfigurable Processor for Binary Image Processing
PSVLSI030 An Efficient Denoising Architecture for Removal of Impulse Noise in Images
PSVLSI031 Optical Flow Estimation for Flame Detection in Videos
PSVLSI032 Memory efficient high-Speed convolution-based generic structure for multilevel 2D
DWT
PSVLSI033 Selective Eigen background for Background Modeling & Subtraction in Crowded Scenes

2. VLSI email id:vlsi@pantechmail.com
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PSVLSI034 Background Subtraction Based on Threshold detection using Modified K-Means
Algorithm
IEEE2013
SoftcoreProcessorDesign
(Microblaze,XilinxPlatformStudio)
PSVLSI035 Modified Gradient Search for Level Set Based Image Segmentation
PSVLSI036 Satellite Image Enhancement Using Discrete Wavelet Transform and Threshold
Decomposition Driven Morphological Filter
PSVLSI037 An Efficient Modified Structure Of CDF9/7 Wavelet Based On Adaptive Lifting With
SPHIT For Lossy To Lossless Image Compression.
PSVLSI038 A Fast Low-Light Multi-Image Fusion with Online Image Restoration
PSVLSI039 An Analysis of SOBEL and GABOR Image Filters for Identifying Fish
PSVLSI040 Segmentation and Location of Abnormality in Brain MR Images using Distributed
Estimation
PSVLSI041 Shadow Removal for Background Subtraction Using Illumination InvariantMeasures
PSVLSI042 Least Significant Bit Matching Steganalysis Based on Feature Analysis
IEEE2013
Cryptography
Algorithm
PSVLSI043 Teaching HW/SW Co-Design With a Public Key Cryptography Application
PSVLSI044 FPGA Implementation of Pipelined Architecture For SPIHT Algorithm
PSVLSI045 Parallel AES Encryption Engines for Many-Core Processor Arrays
PSVLSI046 Reverse Circle Cipher for Personal and Network Security
PSVLSI047 Prototype of a Fingerprint Based Licensing System For Driving
IEEE2013
RealTime/EmbeddedApplications(ZIGBEE,
RF,Sensors,GSM,GPS)
PSVLSI048 A Topology-Based Model for Railway Train Control Systems
PSVLSI049 Location-Aware and Safer Cards: Enhancing RFID Security and Privacy via Location
Sensing
PSVLSI050 A Smarter Toll Gate Based on Web Of Things
PSVLSI051 An Interactive RFID-based Bracelet for Airport Luggage Tracking System
PSVLSI052 The Security Technology and Tendency of New Energy Vehicle in Future
PSVLSI053 RFID-based Tracking System Preventing Trees Extinction and Deforestation
PSVLSI054 RFID-based Location System for Forest Search and Rescue Missions
PSVLSI055 Secure Transmission in Downlink Cellular Network with a Cooperative Jammer
PSVLSI056 Pipelined Parallel FFT Architectures via Folding Transformation
IEEE2012
CommunicationSystems,ArchitecturalDesignsand
ProtocolDesigns
PSVLSI057 High Speed and Area Efficient Vedic Multiplier
PSVLSI058 Multifunction RNS modulo (2n±1) Multipliers Based on Modified Booth Encoding
PSVLSI059 BPSK System on Spartan 3E FPGA
PSVLSI060 Design of Modified Low Power Booth Multiplier
PSVLSI061 Design and Simulation of 32-Point FFT Using Radix-2 Algorithm for FPGA
Implementation
PSVLSI062 Teaching And Research In FPGA Based Digital Signal Processing Using Xilinx System
Generator
PSVLSI063 Platform-Independent Customizable UART Soft-Core
PSVLSI064 Input/ Output Peripheral Devices Control through Serial Communication using
Microblaze Processor
PSVLSI065 Real Time Smart Car Lock Security System Using Face Detection and Recognition

3. VLSI email id:vlsi@pantechmail.com
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PSVLSI066 Implementation of a Home Automation System through a Central FPGA Controller
PSVLSI067 A Novel Non-payment Vehicle Searching Method for Multilane-Free-Flow Electronic-
Toll- Collection Systems
IEEE2012
(XilinxISE,Placeand
Route)
PSVLSI068 Design of Intelligent Home Appliance Control System Based on FPGA and ZIGBEE
PSVLSI069 An improved three-factor authentication scheme using smart card with biometric
privacy protection
PSVLSI070 The Ship Monitoring and Control Network System Design
PSVLSI071 Image Segmentation via Normalized Cuts and Clustering Algorithm
IEEE2012
CoreProcessorDesign(Softcore-
Microblaze)
PSVLSI072 VLSI Architecture of Arithmetic Coder Used in SPIHT
PSVLSI073 Edge Detection of Angiogram Images Using the Classical Image Processing Techniques
PSVLSI074 Median Filter on FPGAs
PSVLSI075 Analysis of CT and MRI Image Fusion using Wavelet Transform
PSVLSI076 Background Subtraction Algorithm for Moving Object Detection in FPGA
PSVLSI077 An Auto-adaptive Edge-Detection Algorithm for Flame and Fire Image Processing
PSVLSI078 Gesture Recognition Using Field Programmable Gate Arrays
PSVLSI079 High Speed Implementation of RSA Algorithm with Modified Keys Exchange
IEEE2012
SecurityAlgorithms
PSVLSI080 A Fast Cryptography Pipelined Hardware developed in FPGA with VHDL
PSVLSI081 An efficient FPGA implementation of the Advanced Encryption Standard Algorithm
PSVLSI082 A Novel Architecture for VLSI Implementation of RSA Cryptosystem
PSVLSI083 Models Simulation based on HDL-Simulink Platform
PSVLSI084 Single Phase Clocked Quasi Static Adiabatic Tree Adder
IEEE2012
LowPowerApplications(Microwind&
DSCH)
PSVLSI085 A Novel High-Performance CMOS 1 Bit Full-Adder Cell
PSVLSI086 Design of Low Voltage Low Power Operational Amplifier
PSVLSI087 Enhancing NBTI Recovery in SRAM Arrays Through Recovery Boosting
PSVLSI088 Low-Power and Area-Efficient Carry Select Adder
PSVLSI089 Digital CMOS Parallel Counter Architecture Based on State Look-Ahead Logic
PSVLSI090 Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design
PSVLSI091 An Evaluation of CMOS Adders in Deep Submicron Processes
PSVLSI092 Design Low Power 10T Full Adder Using Process and Circuit Techniques
PSVLSI093 A Novel High Speed & Power Efficient Half Adder Design Using MTCMOS Technique in
45 Nanometre Regime
IEEE2012
LowPowerApplications(Tanner
EDA,W-Edit,S-Edit,L-Edit,T-Spice)
PSVLSI094 Enhanced Power Gating Schemes for Low Leakage Low Ground Bounce Noise in Deep
Submicron Circuits
PSVLSI095 Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement
Scheme
PSVLSI096 A High Performance D-Flip Flop Design with Low Power Clocking System using MTCMOS
Technique
PSVLSI097 Low-Swing Differential Conditional Capturing Flip-Flop for LC Resonant Clock
Distribution Networks