This slide is used for K51 student class of Advanced Program in Hanoi University of Technology 2009.

1. Nguyen Thanh Kien Department of Computer Engineering Faculty of Information Technology Hanoi University of Technology Digital Logic Design

12. 1.1.1. Number Representation 11101.11 (2) = 1x2 4 +1x2 3 +1x2 2 +0x2 1 +1x2 0 +1x2 -1 +1x2 -2 = 29.75 (10)

36. 4 bit representation of unsigned and signed (2’s complement) -1 15 1111 -2 14 1110 -3 13 1101 -4 12 1100 -5 11 1011 -6 10 1010 -7 9 1001 -8 8 1000 +7 7 0111 +6 6 0110 +5 5 0101 +4 4 0100 +3 3 0011 +2 2 0010 +1 1 0001 0 0 0000 Signed Unsigned Binary format

69. Canonical forms f(x2,x1,x0)=m 1 +m 4 +m 5 +m 6 +m 7 = Σ (1,4,5,6,7) f(x2,x1,x0)=M 0 M 2 M 3 = Π (0,2,3) Canonical sum-of-products (SOP) Canonical product-of-sums (POS) 1 1 1 1 7 1 0 1 1 6 1 1 0 1 5 1 0 0 1 4 0 1 1 0 3 0 0 1 0 2 1 1 0 0 1 0 0 0 0 0 f x0 x1 x2 Decimal

76. Venn diagram A A A+B A.B A.B A+B

85. Five-variable K-map 00 01 11 10 AB CD 00 01 11 10 00 01 11 10 AB CD 00 01 11 10 E 0 1 5 variables Karnaugh Map consists of two 4 variables Karnaugh Map connected up/down.

86. Six-variable K-map 1 1 1 1 1 1 00 01 11 10 AB CD 00 01 11 10 1 1 1 1 1 1 00 01 11 10 AB CD 00 01 11 10 E 0 1 1 1 1 1 1 1 00 01 11 10 AB CD 00 01 11 10 1 1 1 1 1 1 00 01 11 10 AB CD 00 01 11 10 F 0 1

87. Karnaugh map with don’t care don’t care ~ input conditions that not occur

117. Examples: F(a,b,c,d)=R(1,3,5,7,12,13) don’t care (0,4,10,15) - 10 - 1 1 11 1 1 - 01 1 1 - 00 10 11 01 00 CD AB

120. 2.3. Quine-Mcluskey method Karnaugh map cannot handle more than 6 variables. Quine-McCluskey method has no limitation with number of variables, and is suitable for computer algorithm. 0 1 00 01 1 11 1 1 10 1 1 AB C ABC+ABC+ABC+ABC+ABC 010 *10 11* 1*0 1*1 10* 110 111 100 101 1** find a pair of numbers of 1 bit difference

122. S1. Represent minterms in binary numbers f = ABCDEF+ABCDEF+ABCDEF+ABCDEF+ABCDEF +ABCDEF+ABCDEF +ABCDEF+ABCDEF+ABCDEF f = 000000+000010+000110+000111+001110 +001000+101001+001100+001111+001010 f(A,B,C,D,E,F)=Σ(0,2,6,7,14,8,41,12,15,10)

123. S2. Grouping f = 000000+000010+000110+000111+001110 +001000+101001+001100+001111+001010 000000 once twice three times 000010 001000 000110 001100 001010 000111 001110 101001 four times 001111 group 0 group 1 group 2 group 3 group 4 group each term by the appearance of 1 no times

124. S3 & S4. Making set (1) 000000 0 000010 2 001000 8 000110 6 001010 10 001100 12 000111 7 001110 14 101001 41 001111 15 0,2 (2) 0,8 (8) 2,6(4) 2,10(8) 8,10(2) 8,12(4) 6,7(1) 6,14(8) 10,14(4) 12,14(2) 7,15(8) 14,15(1) find a pair of 1 bit difference between neighboring group write difference within ( ) mark to the number not included in any set group 0 group 1 group 2 group 3 group 4

125. S3 & S4. Making set (2) 0,2 (2) 0,8 (8) 2,6(4) 2,10(8) 8,10(2) 8,12(4) 6,7(1) 6,14(8) 10,14(4) 12,14(2) 7,15(8) 14,15(1) 0,2,8,10(2,8) 2,6,10,14(4,8) 8,10,12,14(2,4) 6,7,14,15(1,8) mark to the set not involved in the next level set when all the set is marked finish Each pair appears in duplicate find a pair of 1 bit different sets with the same value in ( ) between neighboring group append difference within ( )

126. S6. Selecting Prime Implicants (1) 41 0,2,8,10(2,8) 2,6,10,14(4,8) 8,10,12,14(2,4) 6,7,14,15(1,8) 0 2 6 7 8 10 12 14 15 41 x x x x x x x x x x x x x x x x x If only one x in a column, then the row is inevitable implicant minterms (given at first) Prime implicant （ marked ） write x into the position where minterm is included in the prime implicant inevitable implicant

127. S6. Selecting Prime Implicants (2) 41 0,2,8,10(2,8) 2,6,10,14(4,8) 8,10,12,14(2,4) 6,7,14,15(1,8) 0 2 6 7 8 10 12 14 15 41 x x x x x x x x x x x x x x x x x mini term prime implicants mark minterms involved in the inevitable implicants inevitable implicants

128. S7. C onversion to logic variables 41 101001 0,2,8,10(2,8) 000000 000010 001000 001010 8,10,12,14(2,4) 001000 001010 001100 001110 6,7,14,15(1,8) 000110 000111 001110 001111 ABCDEF ABDF ABCF ABDE F=ABCDEF +ABDF +ABCF +ABDE

131. Quine-Mcluskey method w ith don’t care f=ABCD+BCD+ACD+ABCD+ABCD don’t care AD mini term ABCD 0000 0001 0010 0011 0101 0111 1011 1101 1111 decimal 0 1 2 3 5 7 11 13 15 first comparison second comparison 0,1(1) 0,2(2) 1,3(2) 1,5(4) 2,3(1) 3,7(4) 3,11(8) 5,7(2) 5,13(8) 7,15(8) 11,15(4) 13,15(2) 0,1,2,3(1,2) 1,3,5,7(2,4) 3,7,11,15(4,8) 5,7,13,15(2,8)

132. Quine-Mcluskey method w ith don’t care 0 2 11 13 15 0,1,2,3(1,2) 1,3,5,7(2,4) 3,7,11,15(4,8) 5,7,13,15(2,8) x x x x x x 00** 0**1 **11 *1*1 ABCD f=AB+CD+BD

138. Half Adder  =a  b r = ab Half Adder (Carry-out) a b  r 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 =1 & a b  r HA a b  r (Result)

139. Addition of two n-bit numbers  4  3  2  1  0 r 3 r 2 r 1 r 0 A = a 3 a 2 a 1 a 0 +B = b 3 b 2 b 1 b 0 r 4  3 r 3  2 r 2  1 r 1  0 Summation

140. Full Adder  i r i+1  i = a i  b i  r i r i+1 = a i b i + r i (a i  b i ) FA a i r i b i  i r i+1 a i b i r i  i r i+1 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 0 10 11 01 00 a i b i r i 1 1 1 1 1 0 10 11 01 00 a i b i r i

147. Full Adder =1 & r i a i b i =1 &  i r i+1  1

148. Full Adder =1 & r i a i b i =1 &  i r i+1  1 HA HA

151. Parallel 4-bit addition r 4 =  4  3  2  1  0 r 2 r 1 a 2 b 2 a 1 b 1 a 0 b 0 P 3 G 3 P 2 G 2 P 1 G 1 P 0 G 0 Calculate P i and G i a 3 b 3 a 2 b 2 a 1 b 1 a 0 b 0 Carry calculation Sum calculation r 0 a 3 b 3 r 3 r 4 r 0

154. Adder and Subtractor C1 C2 C3 C4 A B C S C+ FA A B C S C+ FA A B C S C+ FA A B C S C+ FA MPX MPX MPX MPX A3 A2 A1 A0 B3 B2 B1 B0 S3 S2 S1 S0 sel

158. Design 3x8 decoder En if (En=0) Disable or D0...D7=0 else if (En=1) Function as a 3x8 decoder

159. BCD-to-decimal decoder BCD to decimal Decoder A B C D Y 0 Y 1 Y i Y 9 : : N A B C D Y 0 Y 1 .. Y 9 0 0 0 0 0 1 0 .. 0 1 0 0 0 1 0 1 .. 0 2 0 0 1 0 0 0 .. 0 3 0 0 1 1 0 0 .. 0 4 0 1 0 0 0 0 .. 0 5 0 1 0 1 0 0 .. 0 6 0 1 1 0 0 0 .. 0 7 0 1 1 1 0 0 .. 0 8 1 0 0 0 0 0 .. 0 9 1 0 0 1 0 0 . 1

160. BCD-to-decimal decoder   10     11 01 1 00 10 11 01 00 CD AB

162. Decoder implementation of arbitrary functions F1(x1,x2,x3,x4)= Σ (0,1,3,8,12)

163. BCD-to-7segment decoder Each segment is a Light Emitting Diode (LED) a b c d e f g 1 1 0 1 1 1 1 1 0 0 1 9 1 1 1 1 1 1 1 0 0 0 1 8 0 0 0 0 1 1 1 1 1 1 0 7 1 1 1 1 1 0 1 0 1 1 0 6 1 1 0 1 1 0 1 1 0 1 0 5 1 1 0 0 1 1 0 0 0 1 0 4 1 0 0 1 1 1 1 1 1 0 0 3 1 0 1 1 0 1 1 0 1 0 0 2 0 0 0 0 1 1 0 1 0 0 0 1 0 1 1 1 1 1 1 0 0 0 0 0 g f e d c b a D C B A N

164. BCD-to-7segment decoder   1 1 10     11 1 1 1 0 01 1 1 0 1 00 10 11 01 00 CD AB

168. Keyboard encoder A = 1 if (N=8) or (N=9) B = 1 if (N=4) or (N=5) or (N=6) or (N=7) C = 1 if (N=2) or (N=3) or (N=6) or (N=7) D = 1 if (N=1) or (N=3) or (N=5) or (N=7) or (N=9) 1001 9 1000 8 0111 7 0110 6 0101 5 0100 4 0011 3 0010 2 0001 1 ABCD N

169. Keyboard encoder  1  1  1  1 N=9 N=8 N=7 N=6 N=5 N=4 N=3 N=2 N=1 A B C D

172. 2-to-1 Multiplexor MUX 2-1 X 0 X 1 C 0 Y C 0 Y 0 X 0 1 X 1 1 1 1 1 1 0 10 11 01 00 X 1 X 0 C 0 C 0 X 1 X 0 Y 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 0 1 1 0 1 1 1 1 1

173. 2-to-1 Multiplexor

174. 4-to-1 Multiplexor Y = s 1 ’s 0 ’I 0 + s 1 ’s 0 I 1 +s 1 s 0 ’I 2 + s 1 s 0 I 3

181. Demultiplexor 1-4 E C 1 C 0 S 0 S 1 S 2 S 3

217. Mealy state table PS: Present State NS: Next State k memory devices => 2 k rows n circuit inputs => NS portion contains 2 n columns Output portion also contains 2 n columns 1 0 c b d 0 0 a d c 0 0 c b b 0 0 a b a x=1 x=0 x=1 x=0 Output (z) NS PS c/1 b/0 d a/0 d/0 c c/0 b/0 b a/0 b/0 a x=1 x=0 NS/Output (z) PS

218. Moore state table The output portion always contains a single column. The entry at the intersection of any row with the output column indicates the output values corresponding to the PS associated with that row. 1 a f f 1 e f e 0 e d d 0 c d c 0 c b b 0 a b a z x=1 x=0 Output NS PS

226. SR Latch active-HIGH SR Latch active-LOW SR Latch S Q R Q’ S Q R Q’

229. SR Latch Circuit showing feedback Q + = R’Q + R’S SR=0 => Q + = R’Q + R’S + RS = R’Q + S for active-HIGH SR Latch Excitation table - 0 1 1 0 1 1 0 1 0 0 1 0 - 0 0 S R Q Q +

230. D Latch D Q Q’ S Q R Q’ D Graphic symbol Implementation using SR Latch Equivalent characteristic table Excitation table Q * = D 1 1 0 0 Q * D 1 1 1 0 1 0 1 0 1 0 0 0 D Q Q *

236. Implementation of SR-FF CL S Q R Q Q Q S R SR-latch Q Q CL S R Implementation of SR-FF by SR-Latch

259. Example1: A D flip-flop Moore model circuit State table State diagram q1* = d1 = q1q2’ + xq1’ q2* = d2 = xq1 0 01 00 11 1 11 10 10 0 10 00 01 1 10 00 00 z x=1 x=0 q1q2 q1*q2*

261. Example2: A JK flip-flop Moore model circuit State table State diagram A* = A’J A + AK A = A’x+AxB’ B* = B’J B + BK B = B’(x+A’) + B(x+A’)’ 1 10 11 11 1 01 10 10 1 10 00 01 0 11 01 00 z x=1 x=0 AB A*B*

262. Example2: A JK flip-flop Moore model circuit

266. Example3: A D flip-flop Mealy model circuit

270. Example1: Design sync sequential circuit using JK Use two state variables q 1 q 2 to encode states in binary State table after assignment State table Q 1 Q 2 Q 1 Q 2 C,1 B,0 D A,0 D,0 C C,0 B,0 B A,0 B,0 A 1 0 x S D B 1 C A 0 1 0 q 1 q 2 10,1 01,0 11 00,0 11,0 10 10,0 01,0 01 00,0 01,0 00 1 0 x q 1 q 2

271. Example1: Design sync sequential circuit using JK q 1 *q 2 * Excitation table Application table 00,0 11,0 10 10,1 01,0 11 10,0 01,0 01 00,0 0 1 ,0 0 0 1 0 x q 1 q 2 0 - 1 1 1 - 0 1 - 1 1 0 - 0 0 0 K J q* q q 1 q 2 x 0 1 J 1 K 1 J 2 K 2 J 1 K 1 J 2 K 2 00 0 - 1- 0 - 0 - 01 0 - - 0 1 - - 1 11 - 1 - 0 - 0 - 1 10 - 0 1 - - 1 0 -

272. Example1: Design sync sequential circuit using JK Excitation equations: J 1 = xq 2 K 2 = x Output equation: y = xq 1 q 2 Minimization for J 1 q 1 q 2 x 0 1 J 1 K 1 J 2 K 2 J 1 K 1 J 2 K 2 00 0 - 1- 0 - 0 - 01 0 - - 0 1 - - 1 11 - 1 - 0 - 0 - 1 10 - 0 1 - - 1 0 - x q 1 q 2 0 1 00 0 0 01 0 1 11 - - 10 - -

273. Ex 1: Design sync sequential circuit using JK J 2 q 2 CLK K 2 q 2 J 1 q 1 CLK K 1 q 1 1 & =1 & y x CLOCK

281. State reduction 0 1 B C D E E D D F E F B C 0 1 0 0 0 1 0 1 0 0 0 0 0 0 A B C D E F current state next state output 0 1 B C D E E D D AF E AF 0 1 0 0 0 1 0 1 0 0 0 0 AF B C D E 0 1 B C DE DE DE DE DE AF 0 1 0 0 0 1 0 1 0 0 AF B C DE 0 1 BC BC DE DE DE AF 0 1 0 0 0 1 0 0 AF BC DE current state current state current state next state next state next state output output output

288. Example of method 2 (1/5) current state next state input X 1 X 0 00 01 10 11 d e b - e - - a a - - e - b e d a b f - d c - e output input X 1 X 0 00 01 10 11 0 - 0 - - 1 - 0 1 - 0 - - 0 0 - - - - 0 1 - 1 0 a b c d e f a set of not compatible pairs (a,c) (a,f) (b,d) (c,f) (d,f) Implication table a b c d e b c d e f × × × × × 1:fill in × at incompatible pair 2: fill in conditions to be compatible de be ad be bf ae ae de ae de ○ ef ad bc

289. Example of method 2 (2/5) (a,b,e) (a,b,c,d,e,f) (a,b,d,e,f) (b,c,d,e,f) (a,c) (a,f) (a,b,d,e) (b,d,e,f) (b,d) (b,c,e,f) (c,d,e,f) (b,d) (a,d,e) (b,d) (b,e,f) (d,e,f) (c,f) (b,e,f) (b,c,e) (c,f) (c,d,e) (d,e,f) (d,f) (d,e) (e,f) Maximum compatible set is (a,b,e),(a,d,e),(b,e,f),(b,c,e),(c,d,e) Decompose state set by non compatible pairs (a,c) (a,f) (b,d) (c,f) (d,f) remove duplicated node remove pair involved to other node

290. Example of method 2 (3/5) Maximum compatible set C1:(a,b,e) C2:(a,d,e) C3:(b,e,f) C4:(b,c,e) C5:(c,d,e) Logic function to represent each set involved a: C1+C2 b: C1+C3+C4 c: C4+C5 d: C2+C5 e: C1+C2+C4+C5 f: C3 Minimum closed set is a subset of maximum compatible set that involves all the state axbxcxdxexf = 1 (C1+C2)(C1+C3+C4)(C4+C5)(C2+C5)(C1+C2+C4+C5)C3 =(C1+C2C3+C2C4)(C2C4+C5) (C1+C2+C4+C5)C3 =(C1C5+C2C3C5+C2C4) (C1+C2+C4+C5)C3 =(C1C5+C2C3C5+C2C4)C3 =C1C3C5+C2C3C5+C2C3C4 hence (C1,C3,C5),(C2,C3,C5),(C2,C3,C4) are candidates for minimum closed set

291. Example of method 2 (4/5) C1:(a,b,e) C2:(a,d,e) C3:(b,e,f) C4:(b,c,e) C5:(c,d,e) candidate for minimum closed set: (C1,C3,C5),(C2,C3,C5),(C2,C3,C4) check state transition of each candidate by using Implication table C1->(d,e)(a,d),(b,e),(b,f),(a,e) ->(a,d,e)(b,e,f) ->C1,C3 C2 ->(b,e),(a,d),(b,e),(b,f),(e,f) ->(b,e,f)(a,d) ->C3,C2 C3->(a,e),(d,e),(a,d),(b,c) ->(a,d,e)(b,c) ->C2,C4 C4->(a,e) ->(C1|C2) C5->(d,e),(e,f) ->(C2|C5),C3 C2,C3,C4 is closed Implication table a b c d e b c d e f × × × × × de be ad be bf ae ae de ae de ○ ef ad bc

292. Example of method 2 (5/5) C2:(a,d,e),C3:(b,e,f),C4:(b,c,e) are used current state next state input X 1 X 0 00 01 10 11 d e b - e - - a a - - e - b e d a b f - d c - e output inputX 1 X 0 00 01 10 11 0 - 0 - - 1 - 0 1 - 0 - - 0 0 - - - - 0 1 - 1 0 a b c d e f current state next state input X 1 X 0 00 01 10 11 C2 C3 C3 C2 C2 C4 C3 C2 C2 C4 C3 C2 output input X 1 X 0 00 01 10 11 0 0 0 0 1 1 1 0 1 1 0 0 C2 C3 C4 Reduced State Transition Table

295. State assignment q1 q2 q3 q4 q5 q6 q2 q3 q1 q5 q6 q4 q4 q6 q5 q2 q1 q3 input X current state next state 0 1 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 0 0 1 0 1 0 0 0 0 1 0 1 1 1 0 1 0 0 1 0 0 1 1 0 1 0 1 0 0 1 0 0 0 0 1 0 u u u u u u u u u current state input X next state 0 1 1 2 3 1+ 2+ 3+ 1+ 2+ 3+ block 1 (q1,q2,q3) block 2 (q4,q5,q6) This partition is SP The first bit is used to distinguish the blocks.