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Application Specific IntegratedApplication Specific Integrated
Circuits (ASIC)Circuits (ASIC)
IntroductionIntroduction
BEIT VII
KICSIT
August 28 2012
2
ASIC vs Standard ICASIC vs Standard IC
 Standard ICs – ICs sold as Standard Parts
 SSI/LSI/ MSI IC such as MUX, Encoder, Memory Chips, or
Microprocessor IC
 Application Specific Integrated Circuits (ASIC) – A
Chip for Toy Bear, Auto-Mobile Control Chip, Different
Communication Chips –These ICs are not found in Data Books
 Concept started in 1980s
 An IC customized to a particular System or Application –
Custom ICs
 Digital Designs became a matter of placing of fewer CICs or
ASICs plus Some Glue Logic
 Reduced Cost and Improved Reliability
 Application Specific Standard Parts (ASSP) – Controller
Chip for PC or a Modem
August 28 2012
3
Types of ASICsTypes of ASICs
 Full-Custom ICs/Fixed ASICs and Programmable ASICs
 Wafer : A circular piece of pure silicon (10-15 cm in dia, but
wafers of 30 cm dia are expected soon)
 Wafer Lot: 5 ~ 30 wafers, each containing hundreds of
chips(dies) depending upon size of the die
 Die: A rectangular piece of silicon that contains one IC
design
 Mask Layers: Each IC is manufactured with successive
mask layers(10 – 15 layers)
 First half-dozen or so layers define transistors
 Other half-dozen or so define Interconnect
August 28 2012
4
Types of ASICs –Types of ASICs – Cont’dCont’d
ASICs
Full-Custom ASICs
Semi-Custom
ASICs
PLDs FPGA
Stnadard-Cell
based ASICs
Gate-Array based
ASICs
Praogrammable
ASICs
Full-Custom ASICs: Possibly all logic cells and all mask layers customized
Semi-Custom ASICs: all logic cells are pre-designed and some (possibly all)
mask layers customized
August 28 2012
5
Types of ASICs –Types of ASICs – Cont’dCont’d
Full-Custom ASICs
 Include some (possibly all) customized logic cells
 Have all their mask layers customized
 Full-custom ASIC design makes sense only
 When no suitable existing libraries exist or
 Existing library cells are not fast enough or
 The available pre-designed/pre-tested cells consume too much power that a
design can allow or
 The available logic cells are not compact enough to fit
 Offer highest performance and lowest cost (smallest die size) but at the
expense of increased design time, complexity, higher design cost and higher
risk.
 Some Examples: High-Voltage Automobile Control Chips, Analog & Digital
Communication Chips, Sensors and Actuators
August 28 2012
6
Types of ASICs –Types of ASICs – Cont’dCont’d
 Semi-Custom ASICs
 Standard-Cell based ASICs
(CBIC)
 Use logic blocks from standard
cell libraries, full-custom blocks,
system-level macros(SLMs),
functional standard blocks (FSBs),
cores etc.
 Get all mask layers customized-
transistors and interconnect
 Manufacturing lead time is
around 8 weeks
 Less efficient in size and
performance but lower in design
cost
August 28 2012
7
Types of ASICs –Types of ASICs – Cont’dCont’d
 Semi-Custom ASICs – Cont’d
 Standard-Cell based ASICs
(CBIC) – Cont’d
August 28 2012
8
Types of ASICs –Types of ASICs – Cont’dCont’d
 Semi-Custom ASICs – Cont’d
 Gate Array based ASICs
diffused layers, i.e. transistors and other active devices, are predefined
and wafers containing such devices are held in stock prior to metallization
i.e unconnected
August 28 2012
9
Types of ASICs –Types of ASICs – Cont’dCont’d
 Semi-Custom ASICs – Cont’d
 Gate Array based ASICs - Cont’d
August 28 2012
10
Types of ASICs –Types of ASICs – Cont’dCont’d
The key difference between a channel-less
gate array and channeled gate array
there are no pre-defined areas set aside
for routing between cells on a channel-
less gate array.
channel-less gate arrays have higher logic
density than channeled gate arrays.
 Semi-Custom ASICs – Cont’d
August 28 2012
11
Types of ASICs –Types of ASICs – Cont’dCont’d
 Semi-Custom ASICs – Cont’d
 Programmable ASICs
 PLDs - PLDs are low-density devices
which contain 1k – 10 k gates and are
available both in bipolar and CMOS
technologies [PLA, PAL or GAL]
 CPLDs or FPLDs or FPGAs -
FPGAs combine architecture of gate arrays
with programmability of PLDs.
User Configurable
 Contain Regular Structures - circuit
elements such as AND, OR,
NAND/NOR gates, FFs, Mux, RAMs,
Allow Different Programming
Technologies
 Allow both Matrix and Row-based
Architectures
August 28 2012
12
Types of ASICs –Types of ASICs – Cont’dCont’d
 Semi-Custom ASICs – Cont’d
 Programmable ASICs
 PLDs - PLDs are low-density devices
which contain 1k – 10 k gates and are
available both in bipolar and CMOS
technologies [PLA, PAL or GAL]
 CPLDs or FPLDs or FPGAs -
FPGAs combine architecture of gate arrays
with programmability of PLDs.
User Configurable
 Contain Regular Structures - circuit
elements such as AND, OR,
NAND/NOR gates, FFs, Mux, RAMs,
Allow Different Programming
Technologies
 Allow both Matrix and Row-based
Architectures
August 28 2012
13
Types of ASICs –Types of ASICs – Cont’dCont’d
August 28 2012
14
Types of ASICs –Types of ASICs – Cont’dCont’d
August 28 2012
15
Types of ASICs –Types of ASICs – Cont’dCont’d
August 28 2012
16
Types of ASICs –Types of ASICs – Cont’dCont’d
 Semi-Custom ASICs – Cont’d
 Programmable ASICs - Cont’d
 Structure of a CPLD / FPGA
August 28 2012
17
Why FPGA-based ASIC Design?Why FPGA-based ASIC Design?
 Choice is based on Many Factors ;
 Speed
 Gate Density
 Development Time
 Prototyping and Simulation
Time
 Manufacturing Lead Time
 Future Modifications
 Inventory Risk
 Cost
Very Effective Adequate Poor
Requirement FPGA/FPLD Discrete Logic Custom Logic
Speed
Gate Density
Cost
Development Time
Prototyping and Sim.
Manufacturing
Future Modification
Inventory
Development Tools
August 28 2012
18
Different Categorizations of FPGAsDifferent Categorizations of FPGAs
 Based on Functional
Unit/Logic Cell Structure
 Transistor Pairs
 Basic Logic Gates:
NAND/NOR
 MUX
 Look –up Tables (LUT)
 Wide-Fan-In AND-OR Gates
 Programming Technology
 Anti-Fuse Technology
 SRAM Technology
 EPROM Technology
 Gate Density
 Chip Architecture (Routing Style)
August 28 2012
19
Different Types of Logic CellsDifferent Types of Logic Cells
August 28 2012
20
Different Types of Logic CellsDifferent Types of Logic Cells – Cont’d– Cont’d
 Xilinx XC4000 CLB Structure
August 28 2012
21
Different Types of Logic CellsDifferent Types of Logic Cells – Cont’d– Cont’d
 Actel Act Logic Module Structure
The Actel ACT 2 and ACT 3 Logic Modules. (a) The C-
Module for combinational logic. (b) The ACT 2 S-Module.
(c) The ACT 3 S-Module. (d) The equivalent circuit
(without buffering) of the SE (sequential element). (e) The
sequential element configured as a positive-edge–triggered
D flip-flop. (Source: Actel.)
 Use Antifuse Programming Tech.
 Based on Channeled GA Architecture
 Logic Cell is MUX which can be configured as multi-input logic gates
August 28 2012
22
Different Types of Logic CellsDifferent Types of Logic Cells – Cont’d– Cont’d
 Altera Flex / Max Logic Element
Structure
Flex 8k/10k Devices – SRAM Based LUTs,
Logic Elements (LEs) are similar to those used
in XC5200 FPGA
The Altera MAX architecture. (a) Organization of logic
and interconnect. (b) A MAX family LAB (Logic Array
Block). (c) A MAX family macrocell. The macrocell
details vary between the MAX families—the functions
shown here are closest to those of the MAX 9000
family
August 28 2012
23
Different Types of Logic CellsDifferent Types of Logic Cells – Cont’d– Cont’d
Vendor/ Product Architechture Capacity Basic Cell Programming Technology
Actel Gate Array 2-8 k MUX Antifuse
QuickLogic Matrix 1.2-1.8 k MUX Antifuse
Xilinx Matrix 2-10 k RAM Block SRAM
Altera Extended PLA 1- 5 k PLA EPROM
Concurrent Matrix 3-5 k XOR, AND SRAM
Plessy SOG 2-40 k NAND SRAM
To SUMMARIZE, FPGAs from various
vendors differ in their
 Architecture (Row Based or Matrix
Based Routing Mechanism)
 Gate Density (Cap. In Equiv. 2-
Input NAND Gates)
 Basic Cell Structure
 Programming Technology
August 28 2012
24
Programming TechnologiesProgramming Technologies
 Three Programming Technologies
The Antifuse Technology
Static RAM Technology
EPROM and EEPROM Technology
August 28 2012
25
Programming TechnologiesProgramming Technologies – Cont’d– Cont’d
 The Antifuse Technology
Invented at Stanford and developed by Actel
Opposite to regular fuse Technology
Normally an open circuit until a programming current
(about 5 mA) is forced through it
Disadvantages:
Unwanted Long Delay
OTP Technology
August 28 2012
26
Programming TechnologiesProgramming Technologies – Cont’d– Cont’d
 The Antifuse Technology
August 28 2012
27
Programming TechnologiesProgramming Technologies – Cont’d– Cont’d
 Static RAM Technology
 SRAM cells are used for
As Look-Up Tables (LUT) to
implement logic (as Truth Tables)
As embedded RAM blocks (for
buffer storage etc.)
As control to routing and
configuration switches
 Advantages
Allows In-System Programming
(ISP)
Suitable for Reconfigurable HW
 Disadvantages
Volatile – needs power all the
time / use PROM to download
configuration data
August 28 2012
28
Programming TechnologiesProgramming Technologies – Cont’d– Cont’d
 EPROM and EEPROM Technology-
.
 EPROM Cell is almost as small as Antifuse
 Floating-Gate Avalanche MOS (FAMOS) Tech.
Under normal voltage, transistor is on
With Programming Voltage applied, we can turn it off (configuration) to
implement our logic
Exposure to UV lamp (one hour) we can erase the programming
Use EEPROM for quick reconfiguration, also, ISP possible
August 28 2012
29
Programming TechnologiesProgramming Technologies – Cont’d– Cont’d
 Summary Sheet
August 28 2012

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ASIC vs Standard IC

  • 1. 1 Application Specific IntegratedApplication Specific Integrated Circuits (ASIC)Circuits (ASIC) IntroductionIntroduction BEIT VII KICSIT August 28 2012
  • 2. 2 ASIC vs Standard ICASIC vs Standard IC  Standard ICs – ICs sold as Standard Parts  SSI/LSI/ MSI IC such as MUX, Encoder, Memory Chips, or Microprocessor IC  Application Specific Integrated Circuits (ASIC) – A Chip for Toy Bear, Auto-Mobile Control Chip, Different Communication Chips –These ICs are not found in Data Books  Concept started in 1980s  An IC customized to a particular System or Application – Custom ICs  Digital Designs became a matter of placing of fewer CICs or ASICs plus Some Glue Logic  Reduced Cost and Improved Reliability  Application Specific Standard Parts (ASSP) – Controller Chip for PC or a Modem August 28 2012
  • 3. 3 Types of ASICsTypes of ASICs  Full-Custom ICs/Fixed ASICs and Programmable ASICs  Wafer : A circular piece of pure silicon (10-15 cm in dia, but wafers of 30 cm dia are expected soon)  Wafer Lot: 5 ~ 30 wafers, each containing hundreds of chips(dies) depending upon size of the die  Die: A rectangular piece of silicon that contains one IC design  Mask Layers: Each IC is manufactured with successive mask layers(10 – 15 layers)  First half-dozen or so layers define transistors  Other half-dozen or so define Interconnect August 28 2012
  • 4. 4 Types of ASICs –Types of ASICs – Cont’dCont’d ASICs Full-Custom ASICs Semi-Custom ASICs PLDs FPGA Stnadard-Cell based ASICs Gate-Array based ASICs Praogrammable ASICs Full-Custom ASICs: Possibly all logic cells and all mask layers customized Semi-Custom ASICs: all logic cells are pre-designed and some (possibly all) mask layers customized August 28 2012
  • 5. 5 Types of ASICs –Types of ASICs – Cont’dCont’d Full-Custom ASICs  Include some (possibly all) customized logic cells  Have all their mask layers customized  Full-custom ASIC design makes sense only  When no suitable existing libraries exist or  Existing library cells are not fast enough or  The available pre-designed/pre-tested cells consume too much power that a design can allow or  The available logic cells are not compact enough to fit  Offer highest performance and lowest cost (smallest die size) but at the expense of increased design time, complexity, higher design cost and higher risk.  Some Examples: High-Voltage Automobile Control Chips, Analog & Digital Communication Chips, Sensors and Actuators August 28 2012
  • 6. 6 Types of ASICs –Types of ASICs – Cont’dCont’d  Semi-Custom ASICs  Standard-Cell based ASICs (CBIC)  Use logic blocks from standard cell libraries, full-custom blocks, system-level macros(SLMs), functional standard blocks (FSBs), cores etc.  Get all mask layers customized- transistors and interconnect  Manufacturing lead time is around 8 weeks  Less efficient in size and performance but lower in design cost August 28 2012
  • 7. 7 Types of ASICs –Types of ASICs – Cont’dCont’d  Semi-Custom ASICs – Cont’d  Standard-Cell based ASICs (CBIC) – Cont’d August 28 2012
  • 8. 8 Types of ASICs –Types of ASICs – Cont’dCont’d  Semi-Custom ASICs – Cont’d  Gate Array based ASICs diffused layers, i.e. transistors and other active devices, are predefined and wafers containing such devices are held in stock prior to metallization i.e unconnected August 28 2012
  • 9. 9 Types of ASICs –Types of ASICs – Cont’dCont’d  Semi-Custom ASICs – Cont’d  Gate Array based ASICs - Cont’d August 28 2012
  • 10. 10 Types of ASICs –Types of ASICs – Cont’dCont’d The key difference between a channel-less gate array and channeled gate array there are no pre-defined areas set aside for routing between cells on a channel- less gate array. channel-less gate arrays have higher logic density than channeled gate arrays.  Semi-Custom ASICs – Cont’d August 28 2012
  • 11. 11 Types of ASICs –Types of ASICs – Cont’dCont’d  Semi-Custom ASICs – Cont’d  Programmable ASICs  PLDs - PLDs are low-density devices which contain 1k – 10 k gates and are available both in bipolar and CMOS technologies [PLA, PAL or GAL]  CPLDs or FPLDs or FPGAs - FPGAs combine architecture of gate arrays with programmability of PLDs. User Configurable  Contain Regular Structures - circuit elements such as AND, OR, NAND/NOR gates, FFs, Mux, RAMs, Allow Different Programming Technologies  Allow both Matrix and Row-based Architectures August 28 2012
  • 12. 12 Types of ASICs –Types of ASICs – Cont’dCont’d  Semi-Custom ASICs – Cont’d  Programmable ASICs  PLDs - PLDs are low-density devices which contain 1k – 10 k gates and are available both in bipolar and CMOS technologies [PLA, PAL or GAL]  CPLDs or FPLDs or FPGAs - FPGAs combine architecture of gate arrays with programmability of PLDs. User Configurable  Contain Regular Structures - circuit elements such as AND, OR, NAND/NOR gates, FFs, Mux, RAMs, Allow Different Programming Technologies  Allow both Matrix and Row-based Architectures August 28 2012
  • 13. 13 Types of ASICs –Types of ASICs – Cont’dCont’d August 28 2012
  • 14. 14 Types of ASICs –Types of ASICs – Cont’dCont’d August 28 2012
  • 15. 15 Types of ASICs –Types of ASICs – Cont’dCont’d August 28 2012
  • 16. 16 Types of ASICs –Types of ASICs – Cont’dCont’d  Semi-Custom ASICs – Cont’d  Programmable ASICs - Cont’d  Structure of a CPLD / FPGA August 28 2012
  • 17. 17 Why FPGA-based ASIC Design?Why FPGA-based ASIC Design?  Choice is based on Many Factors ;  Speed  Gate Density  Development Time  Prototyping and Simulation Time  Manufacturing Lead Time  Future Modifications  Inventory Risk  Cost Very Effective Adequate Poor Requirement FPGA/FPLD Discrete Logic Custom Logic Speed Gate Density Cost Development Time Prototyping and Sim. Manufacturing Future Modification Inventory Development Tools August 28 2012
  • 18. 18 Different Categorizations of FPGAsDifferent Categorizations of FPGAs  Based on Functional Unit/Logic Cell Structure  Transistor Pairs  Basic Logic Gates: NAND/NOR  MUX  Look –up Tables (LUT)  Wide-Fan-In AND-OR Gates  Programming Technology  Anti-Fuse Technology  SRAM Technology  EPROM Technology  Gate Density  Chip Architecture (Routing Style) August 28 2012
  • 19. 19 Different Types of Logic CellsDifferent Types of Logic Cells August 28 2012
  • 20. 20 Different Types of Logic CellsDifferent Types of Logic Cells – Cont’d– Cont’d  Xilinx XC4000 CLB Structure August 28 2012
  • 21. 21 Different Types of Logic CellsDifferent Types of Logic Cells – Cont’d– Cont’d  Actel Act Logic Module Structure The Actel ACT 2 and ACT 3 Logic Modules. (a) The C- Module for combinational logic. (b) The ACT 2 S-Module. (c) The ACT 3 S-Module. (d) The equivalent circuit (without buffering) of the SE (sequential element). (e) The sequential element configured as a positive-edge–triggered D flip-flop. (Source: Actel.)  Use Antifuse Programming Tech.  Based on Channeled GA Architecture  Logic Cell is MUX which can be configured as multi-input logic gates August 28 2012
  • 22. 22 Different Types of Logic CellsDifferent Types of Logic Cells – Cont’d– Cont’d  Altera Flex / Max Logic Element Structure Flex 8k/10k Devices – SRAM Based LUTs, Logic Elements (LEs) are similar to those used in XC5200 FPGA The Altera MAX architecture. (a) Organization of logic and interconnect. (b) A MAX family LAB (Logic Array Block). (c) A MAX family macrocell. The macrocell details vary between the MAX families—the functions shown here are closest to those of the MAX 9000 family August 28 2012
  • 23. 23 Different Types of Logic CellsDifferent Types of Logic Cells – Cont’d– Cont’d Vendor/ Product Architechture Capacity Basic Cell Programming Technology Actel Gate Array 2-8 k MUX Antifuse QuickLogic Matrix 1.2-1.8 k MUX Antifuse Xilinx Matrix 2-10 k RAM Block SRAM Altera Extended PLA 1- 5 k PLA EPROM Concurrent Matrix 3-5 k XOR, AND SRAM Plessy SOG 2-40 k NAND SRAM To SUMMARIZE, FPGAs from various vendors differ in their  Architecture (Row Based or Matrix Based Routing Mechanism)  Gate Density (Cap. In Equiv. 2- Input NAND Gates)  Basic Cell Structure  Programming Technology August 28 2012
  • 24. 24 Programming TechnologiesProgramming Technologies  Three Programming Technologies The Antifuse Technology Static RAM Technology EPROM and EEPROM Technology August 28 2012
  • 25. 25 Programming TechnologiesProgramming Technologies – Cont’d– Cont’d  The Antifuse Technology Invented at Stanford and developed by Actel Opposite to regular fuse Technology Normally an open circuit until a programming current (about 5 mA) is forced through it Disadvantages: Unwanted Long Delay OTP Technology August 28 2012
  • 26. 26 Programming TechnologiesProgramming Technologies – Cont’d– Cont’d  The Antifuse Technology August 28 2012
  • 27. 27 Programming TechnologiesProgramming Technologies – Cont’d– Cont’d  Static RAM Technology  SRAM cells are used for As Look-Up Tables (LUT) to implement logic (as Truth Tables) As embedded RAM blocks (for buffer storage etc.) As control to routing and configuration switches  Advantages Allows In-System Programming (ISP) Suitable for Reconfigurable HW  Disadvantages Volatile – needs power all the time / use PROM to download configuration data August 28 2012
  • 28. 28 Programming TechnologiesProgramming Technologies – Cont’d– Cont’d  EPROM and EEPROM Technology- .  EPROM Cell is almost as small as Antifuse  Floating-Gate Avalanche MOS (FAMOS) Tech. Under normal voltage, transistor is on With Programming Voltage applied, we can turn it off (configuration) to implement our logic Exposure to UV lamp (one hour) we can erase the programming Use EEPROM for quick reconfiguration, also, ISP possible August 28 2012
  • 29. 29 Programming TechnologiesProgramming Technologies – Cont’d– Cont’d  Summary Sheet August 28 2012