1. DESIGN AND ANALYSIS OF VOLTAGE CONTROLLED OSCILLATOR
A Mid Term Report for major project submitted in for approval
MASTER OF TECHNOLOGY
IN
INFORMATION AND COMMUNICATION TECHNOLOGY
(for Engineering Graduates)
Specilization
(VLSI DESIGN)
Submitted by:
Mr. Sharad Sharma Enrollment No: 12/PIT/054
Mr. Vaibhav Jindal Enrollment No: 12/PIT/055
Mr. Saurabh Kumar Enrollment No: 12/PIT/068
Supervised by:
Mr. Navaid Zafar Rizvi
-
SCHOOL OF INFORMATION AND COMMUNICATION TECHNOLOGY
GAUTAM BUDDHA UNIVERSITY
GAUTAM BUDH NAGAR, GREATER NOIDA
MARCH, 2013

2. ABSTRACT
Our Project is to design of complementary oxide semiconductor voltage controlled oscillator
(CMOS VCO) with improved phase noise and lower power consumption. Design is supposed to be area
efficient and power efficient. We have completed the study and analysis part of VCO, and have started
the designing of VCO in cadence and schematic editor using 180 nm technology. We successfully
completed the circuit diagram, symbol creation part. Then we moved on to test circuit verification and
analysis. In this report we have also included the results which we got till test circuit simulation. The
layout part is still remaining, which is very important and main part in governing the power analysis.
Thus we can say that we have completed about one third part of Simulation and overall performance
results are yet to be reported.

3. LIST OF ABBRIVATIONS
1. VCO : Voltage controlled oscillator
2. C-MOS : Complementary Metal Oxide Semiconductor
3. I.C. : Integrated Chip
4. LC : Inductor and Capacitor
5. RF : Radio Frequency
6. CIW : Command Interface Window
7. TRANS : Transient
8. DC : Direct Current
9. AC : Alternating Current
10. ADE : Analog Design Environment
11. PAW : Parameter Analyses Window
12. µm : Micro Meter

4. LIST OF FIGURES
1. Fig 3.1 : Design Process Flowchart………………………………………………………9
2. Fig 3.2 : The cadence virtuoso command interface window(CIW)……………………..10
3. Fig 3.3 : Cadence New library Create …………………………………………………..11
4. Fig 3.4 : Schematic Cellview ……………………………………………………………12
5. Fig 3.5 : VCO Schematic Design………………………………………………………...14
6. Fig 3.6 : VCO Test Schematic…………………………………………………………...15
7. Fig 3.7 : ADE window…………………………………………………………………..16
8. Fig 3.8 : Recordings Of Trans analysis…………………………………………………..18
9. Fig 3.9 : Simulation Results of VCO…………………………………………………….18
10. Fig 3.10 : Parameter Analysis Window(Calculator)……………………………………….19
11. Fig 4.1 : Simulation Response of output response………………………………………..21
12. Fig 4.2 : Simulation Result on Phase noise @ 1MHz…………………………………….21

5. List of Tables
SNo. Table No. Title Page No.
1 1 Results of VCO Design 20

6. TABLE OF CONTENT
1. CHAPTER I…………………………………………………………………………………...2
INTRODUCTION………………………………………………………………………..…...2
1.1 Motivation……………………………………………………………………………..2
1.2 Report Structure…………………………………………………………………….…2
2. CHAPTER II………………………………………………………………………………….3
THEORETICAL BACKGROUND AND LITERATURE REVIEW……………………..…3
2.1 Introduction to VCO…………………………………………………………………..3
2.2 VCO Metrics…………………………………………………………………………..3
2.3 VCO for Frequency Translation……………………………………………………….4
2.4 VCO Basic…………………………………………………………………………….4
2.5 Design of VCO………………………………………………………………………..6
2.5.1 VCO Circuit Design
2.5.2 Advantages of LC tank VCO Circuit
3. CHAPTER III……………………………………………………………..………………….8
INTRODUCTION TO DESIGN TOOL………………………………………………..……8
3.1 CADENCE Virtuoso…………………………………………………………………8
3.1.1 Features/Benefits Of CADENCE Virtuoso
3.1.2 IC Design Flow
3.2 Getting started with CADENCE Virtuoso…………………………………………..10
3.2.1 Library creation and selection of technology
3.3 Designing of VCO in Virtuoso………………………………………………………12
4. Base Paper……………………………………………………………………………………20
5. Software Specification………………………………………………………………...……..22
6. Scope of Major Project………………………………………………………………..……..23
References……………………………………………………………………..……...…………24

7. CHAPTER I
INTRODUCTION
1.1 Motivation
A lot of research work has been done on Wireless Communication in the past few years and
many applications have been developed. Today is increasing demand for wireless and
multimedia applications keeps pushing the CMOS integrated wire-less systems to support much
communication standards (WLAN, GSM, UWB and DVB etc). As gigahertz-band
communication is becoming more mature, the realization of a single chip transceiver becomes
more demanding, with the need for lower cost, reduced size and less power consumption. For the
local oscillator signal generated from the integrated frequency synthesizer, the transceivers
matched these standards need excellent phase noise performance and wide tuning range solving
the frequency offset due to the variations of process, temperature and voltage. As per demand for
multi-band and multi-standard radios requires VCO’s operating over a wider frequency range.
Wireless standards specify the minimum level of the received signal, the maximum level of
noise, the channel bandwidth, and the spacing between adjacent channels. Therefore, the
maximum amount of acceptable phase noise on the oscillator can be calculated using the re-
quired signal to noise ratio after down conversion. We took this project so that we can achieve
low phase noise, low power consumption and enlarged tuning range.
1.2 Report Structure
This report is organized as follows. Chapter II discusses theoretical background and
literature review which was taken into consideration during our research. In chapter III we
have first introduced the Design tool which we are using to complete our project topic, then
we have discussed how to start with the tool and finally we have shown that how we are
designing our topic in this tool and the results achieved up till now. In chapter IV we have
discussed our base paper and its results. Then we have discussed the software specifications
and finally the scope of the Major Project.

8. CHAPTER II
THEORETICAL BACKGROUND AND LITERATURE REVIEW
2.1 INTRODUCTION
Oscillators are a fundamental part in many electronic systems. Applications utilize
oscillators from clock generation in microprocessors to frequency translation in mobile phones.
Different application also requires different set of oscillator performance parameters. As today’s
integrated circuits are converging towards CMOS, the design of robust and high-performance
CMOS oscillators, more specifically, voltage-controlled oscillators (VCOs), has become
extremely important. A Voltage controlled oscillator is a circuit that provides a varying output
signal (typically a square wave or triangular wave forms) whose frequency can be adjusted over
a range controlled by a dc voltage. An example of a VCO is the IC 566 IC unit which contain the
circuitry to generate both square and triangular wave signals we are designing the same IC using
C-MOS having low power dissipation and low phase noise.
2.2 VCO Metrics
The key metrics of a VCO consist of: oscillation frequency, tuning range, phase noise, and
power consumption. The frequency of oscillation is determined by the application in which the
VCO is used in, such as microprocessor or cellular phone. The tuning range is determined by the
necessity of the application and the variation on oscillation frequency due to process and
temperature variation. The center frequency of some CMOS oscillators may vary by a factor of
two at the extremes of process and temperature, thus a wide tuning range is very desirable. The
design of low phase noise VCOs has become another major direction of research. The recent
huge growth in wireless communication has demanded more available channels. As a result the
phase noise requirement in the local oscillator becomes more stringent. In digital
microprocessors, the phase noise of the oscillator will directly affect the jitter of the clock signal
and the timing margin, thus limits system performance. Lastly, power consumption is extremely
important for mobile applications such as cellular phones and laptops where a battery supply the

9. power. A low power design will increase the battery life and low power designs are seen in many
of the recent publications.
2.3 VCOs for Frequency Translation
Another common application for VCOs is frequency translation. In this type of application, such
as radio and cellular phone, base band data needs to be up converted to the carrier frequency for
transmission, or received data down converted to base band for processing. Typically, frequency
translation requires the VCO to have very high oscillation frequency, on the order of gigahertz, and
more recently, tens of gigahertz, due to the fact that carrier frequencies are becoming higher and
higher. As a result, VCOs used for frequency translation typically uses inductor and capacitor (LC)
tank VCO topology for its relatively high oscillation frequency and low phase noise.
2.4 Voltage Controlled Oscillator Basic
Noise is injected into an oscillator by the devices that constitute the oscillator itself including
the active transistors and passive elements. This noise will disturb both the amplitude and
frequency of oscillation. Amplitude noise is usually unimportant because non-linearties that limit
the amplitude of oscillation also stabilize the amplitude noise. Phase noise, on the other hand, is
essentially a random deviation in frequency which can also be viewed as a random variation in
the zero crossing points of the time-dependent oscillator waveform.
CMOS voltage controlled oscillator (VCO) will be challenging RF block. Especially, the
higher close in phase noise due to higher 1/f noise in CMOS continues to be a challenge. As per
demand for multi-band and multi-standard radios requires VCO’s operating over a wider
frequency range. Wireless standards specify the minimum level of the received signal, the
maximum level of noise, the channel bandwidth, and the spacing between adjacent channels.
Therefore, the maximum amount of acceptable phase noise on the oscillator can be calculated
using the required signal to noise ratio after down conversion or VCO architecture should have
low phase noise, low power consumption and enlarged tuning range. The low phase noise and
enlarged tuning range are accomplished by adding capacitors which is forming frequency tuning
network. The phase noise is mainly deter-mined by the quality value of tank higher the Q factor

10. of the inductor, the closer it approaches the behavior of an ideal, lossless, inductor. The Q factor
of an inductor can be found through the following formula
R
WoL
Q (1)
The oscillation frequency of oscillator is given by:
LC
Fosc
2
1
( 2 )
where L is the inductance of LC-tank and C is the capacitance.
Phase Noise is calculated by following formula Equation 3
m
c
t f
f
Qf
fo
fm
fo
Pavs
FKT
fmL 1
2
1
2
log10
2
0
2
( 3)
Where
L(fm) : phase noise in dBc/Hz.
Q : loaded Q of the circuit,
fm : frequency from the carrier,
fc : flicker noise corner frequency,
fo : carrier (oscillator) frequency,
T : temperature in Kelvin,
Pavs : power through the resonator,
F : noise factor of the active device,
K : Boltzmann constant.
An important concern in the design of VCOs’ is the variation of the output phase and frequency
as a result of noise on the control line. For a given noise in the output frequency is proportional
to Kvco as
Wout=Wo+Kvco.Vcont
where, Wo is the intercept at Vcont = 0,
Kvco is the gain or sensitivity of the circuit,
Wout is output.
Maximum d.c power dissipation = Vsupply × Ibias

11. 2.5 Design of VCO
2.5.1 VCO Circuit Design
There are two types of VCO that one may choose to design
a. Wave Form Oscillator
b. Resonant Oscillator
Wave Form Oscillator
These type of oscillator are designed as Ring Oscillator and Relaxation Oscillator. There is
low power consumption but on the other hand it gives poor phase noise performance
Resonant Oscillator
These type of oscillator are designed as LC tank oscillator topology and using crystal
oscillator. The main disadvantage in this topology is that it neither integrated nor tunable.
Ideal VCO has following specification
a. Low noise
b. Low power
c. Integrated
d. Wide tuning range
e. Small dice area occupancy
f. High frequency
It is not easy to design VCO with above specification as it is for ideal VCO specification.
We have to reduce power consumption and make low phase noise. We will make it by using LC
tank Oscillator Design Topology.
2.5.2 Advantages of LC tank VCO Circuit
It gives outstanding performance at high frequency of Phase noise as we can tune frequency by
using LC tank circuit. We designed our circuit on virtuoso tool by ―CADENCE‖ as on this tool
we can check our circuit by simulate it and can do power and other analysis.
Certain design specifications must be given for designing VCO
a. max D.C. power dissipation = Vsupply×Ibias
b. min output voltage swing (single-ended) = Vtank

12. c. tuning range in percentage = max− min/ o× 100%
d. αmin > 1
e. chip area
f. Frequency of operation ( o)
The goal of the design is then to develop a VCO that meets the above constraints with
minimum phase noise. An alternative strategy may be to design a VCO with a pre-specified
phase noise but where the d.c. power dissipation is minimized.
Design Procedure Steps
1. Set Ibias = Pd.c. max/Vsupply
2. Determine max of inductors for a given process at required frequency o. This can be
determined in many ways including
i. Already known from previous design experience in that particular process.
ii. Read from model elements in design kit.
iii. Determined through exhaustive design and optimization of inductor using electromagnetic
simulation packages.
iv. Measured data taken from test inductors already fabricated in the same process.
3. Using = L, set L so that is at the minimum required voltage
swing for the design. , o and area already known.
Where values of L must be chosen such that it is in a practical value range to be fabricated as
well as being at a value that results in a practical value of capacitance, C, for the varactor.
4. Using Where = effective series resistance of inductor, calculate
the required value of C for the LC tank with o being the center frequency of the VCO.
5. Given the minimum closed loop gain min α > 1 calculate the minimum transconductance
of each NMOS transistor gm such that gm = αmin RC/L.

13. CHAPTER III
INTRODUCTION TO DESIGN TOOL
3.1 CADENCE Virtuoso
Cadence Virtuoso Spectre Circuit Simulator provides fast, accurate SPICE-level
simulation for tough analog, radio frequency (RF) and mixed-signal circuits. It is tightly
integrated with the Virtuoso custom design platform and provides detailed transistor-level
analysis in multiple domains. Its superior architecture allows for low memory consumption and
high capacity analysis.
3.1.1 Features/Benefits Of CADENCE Virtuoso
It provides high-performance, high-capacity SPICE-level analog and RF simulation with out-
of-the-box tuning for accuracy and convergence.
Facilitates the tradeoff between accuracy and performance through user-friendly simulation
setup applicable to the most complex analog and custom-digital ICs Enables accurate and
efficient post-layout simulation with RLC parasitic, S-Parameter models (n-port), and lossy
coupled transmission lines.
Performs application-specific analysis of RF performance parameters (spectral response, gain
compression, inter-modulation distortion, impedance matching, stability, isolation).
Includes advanced statistical analysis (Smart, MonteCarlo, DCmatch) to help design
companies improve the manufacturability and yield of ICs at advanced process nodes
without sacrificing time to market.
Delivers fast interactive simulation set-up, cross-probing, visualization, and post-processing
of simulation results through tight integration with Virtuoso Analog Design Environment.
Ensures higher design quality using silicon-accurate, foundry-certified device models shared
within Virtuoso Multi-Mode Simulation

14. 3.1.2 IC Design Flow
Cadence Design Systems provides tools for different design styles. Here we will learn to use
three Cadence products: Composer Symbol, Composer Schematic and the Virtuoso Layout
Editor. We will also learn how to get started with Cadence and successfully create symbol,
schematic and layout views. The final check will be seeing whether our layout matches your
schematic.
Fig 3.1: Design Process Flowchart

15. 3.2 Getting started with CADENCE Virtuoso
First of all login as a root user in a linux system(RED HAT).
Open the TERMINAL write the following commands :
 mount -t nfs cadenceserver:/root/cadence /mnt/cadence
(To mount the cadence database from the server)
 cd cadence (to access the cadence directory)
 csh (to work in c shell as cadence is compatible to c shell)
 source cshrc (to activate the changes in c shell)
 cd cadencedb (to access the cadence database directory)
 cd cadence_ms_labs_613 (to access the version installed)
 virtuoso (to open cadence virtuoso)
This will open a window like this:
Fig 3.2: The cadence virtuoso command interface window(CIW)

16. From the CIW menus, all Cadence main tools, online help and options can be accessed. In the
window area, all kind of messages (info, errors, warnings, etc) generated by the different
Cadence tools appear.
3.2.1 Library creation and selection of technology
It is recommended that we use a library to store related cell views; e.g., use a library to hold all
the cellviews for a single project (that can involve a complete chip design). In our example, we
are going to create a new library for our design. From the CIW or from the Library Manager
window,
a) Select File -> New -> Library. A new window appears following screen.
b) Enter a library name, e.g., project
c) Enter the absolute path name if we want the library created somewhere else than the working
directory.
d) Choose the Attach to an existing technology file option.
e) Choose your technology.
This will be the technology chosen for your design (that we will employ eventually for
fabrication). Now all the designs made in this library are technology-dependent (e.g., the
schematic MOS symbol save by default the model for this technology, the available layout layers
correspond to this technology, etc.).
Fig 3.3: Cadence New library Create

17. 3.3 Designing of VCO in Virtuoso
Creation of Schematic Cellview
We are going to create a schematic. From the CIW or from the Library Manager window,
a) Select the library name that we just created, e.g., mydesignlib
b) Select File -> New -> Cellview
c) Enter a cell name, for instance, VCO
d) Choose Composer - Schematic as the Tool. View name should be schematic.
e) Click OK.
An empty blank Composer - schematic window should open. In this window we will create your
schematic.
Fig 3.4: Schematic Cellview

18. Adding Components to schematic
1. In the schematic window, click the Instance menu icon to display the Add Instance form.
Tip: You can also execute Create — Instance or press i.
2. Click on the Browse button. This opens up a Library browser from which you can select
components and the symbol view. You will update the Library Name, Cell Name, and the
property values given in the table on the next page as you place each component.
3. After you complete the Add Instance form, move your cursor to the schematic window and
click left to place a component. If you place a component with the wrong parameter values, use
the Edit—Properties— Objects command to change the parameters. Use the Edit— Move
command if you place components in the wrong location. You can rotate components at the time
you place them, or use the Edit— Rotate command after they are placed.
4. After entering components, click Cancel in the Add Instance form or press Esc with your
cursor in the schematic window.
Adding pins to Schematic
1. Click the Pin fixed menu icon in the schematic window. We can also execute Create — Pin or
press p. The Add pin form appears.
2. Type the following in the Add pin form in the exact order leaving space between the pin
names. Make sure that the direction field is set to input/output/input-output when placing the
input/output/in-out pins respectively and the Usage field is set to schematic.
3. Select Cancel from the Add – pin form after placing the pins. In the schematic window,
execute Window— Fit or press the f bind key.
Adding Wires to a Schematic
Add wires to connect components and pins in the design.
1. Click the Wire (narrow) icon in the schematic window. We can also press the w key, or
execute Create — Wire (narrow).
2. In the schematic window, click on a pin of one of your components as the first point for your
wiring. A diamond shape appears over the starting point of this wire.

19. 3. Follow the prompts at the bottom of the design window and click left on the destination point
for your wire. A wire is routed between the source and destination points.
4. Complete the wiring as shown in figure and when done wiring press ESC key in the schematic
window to cancel wiring.
Saving the Design
1. Click the Check and Save icon in the schematic editor window.
2. Observe the CIW output area for any errors.
Fig 3.5: VCO Schematic Design
Symbol Creation
1. In the schematic window, execute Create — Cellview— From Cellview.
The Cellview From Cellview form appears. With the Edit Options function active, you can
control the appearance of the symbol to generate.

20. 2. Verify that the From View Name field is set to schematic, and the To View Name field is set
to symbol, with the Tool/Data Type set as Schematic Symbol.
3. Click OK in the Cellview from Cellview form. The Symbol Generation Form appears.
4. Modify the Pin Specifications if any.
5. Click OK in the Symbol Generation Options form.
6. A new window displays an automatically created symbol of schematic cellview.
7. The symbol can be modified to a desired symbol using geometrical tools available in the
design window.
Building the Test Design
We will create Test cellview that will contain an instance of our cellview for which we will run
Simulation.
1. In the CIW or Library Manager, execute File— New— Cellview.
2. Set up the new cellview, name it and select the type Schematic.
3. Click OK when done. A blank schematic window for the Test design appears.
4. Build the test circuit according to needs by which simulation can be done.
Fig 3.6: VCO Test Schematic

21. Simulation
We will run the simulation for VCO and plot the transient, DC characteristics and we will do
Parametric Analysis after the initial simulation. For this we can launch various Analog Design
Environments such as ADE L-The analog design environment window display the design
information on the title bar and the design variables, Analyses, and outputs in different panes.
ADE XL- is the new design environment in IC 6.1 for mixed signal design.ADE XL is provides
is support to run multiple tests in parallel and storing all results in a central location. ADE GXL-
you can perform optimization, characterization and modeling tasks, and multi technology
simulation on your designs in the ADE GXL environment.
Starting the Simulation Environment
1. In the Test schematic window, execute: Launch – ADE L
The Virtuoso Analog Design Environment (ADE) simulation window appears.
Fig 3.7: ADE window
Choosing a Simulator (optional, default is spectre)
Set the environment to use the Spectre® tool, a high speed, highly accurate analog simulator.
Use this simulator with the Test design, which is made-up of analog components.
1. In the simulation window (ADE), execute Setup— Simulator/Directory/Host.
2. In the Choosing Simulator form, set the Simulator field to spectre (NotspectreS) and click OK.

22. Setting the Model Libraries (optional default lib set)
The Model Library file contains the model files that describe the NMOS and PMOS devices
during Simulation.
1. In the simulation window (ADE),: Execute Setup - Model Libraries. The Model Library Setup
form appears. Click the browse button to add gpdk.scs if not added by default
as shown in the Model Library Setup form. Remember to select the section type as stat in front
of the gpdk.scs file. To view the model file, highlight the expression in the Model Library File
field and Click Edit File.
2. To complete the Model Library Setup, move the cursor and click OK. The Model Library
Setup allows you to include multiple model files. It also allows you to use the Edit button to
view the model file.
Choosing Analyses
1. In the Simulation window (ADE), click the Choose - Analyses icon.
The Choosing Analysis form appears. This is a dynamic form, the bottom of the form changes
based on the selection above.
2. To setup for transient analysis
a. In the Analysis section select ―tran‖.
b. Set the stop time for example 2n
c. Click at the moderate or enabled button at the bottom, and then click Apply.
3. Click OK in the Choosing Analyses Form.
Selecting Outputs for Plotting
1. Execute Outputs – To be plotted – Select on Schematic in the simulation window.
2. Follow the prompt at the bottom of the schematic window, Click on output net Vout1 & Vout2
, input net Vcont & Iin of the VCO. Press ESC with the cursor in the schematic after selecting it.
Running the Simulation
1. Execute Simulation – Netlist and Run in the simulation window to start the Simulation or the
Icon, this will create the netlist as well as run the simulation.
2. When simulation finishes, the Transient plots automatically will be popped up along with
log file.

23. Fig 3.8: Recordings of Trans Analysis
Fig 3.9: Simulation Results of VCO
I input
V out2
Vout1
Vcont
Spectral Power

24. Calculating Spectral Power
1. For calculating spectral power click on Tools-Calculator on ADE-L window, A new window
is opened.
2. Choose All parameters and in that choose spectral power.
3. Select input voltage and current wave forms from plotted waves.
4. Click on calculated button.
5. Choose All parameters and in that choose average.
6. Select spectral power wave forms from plotted waves.
7. Click on calculated button.
By the above steps power is calculated and that is Watts
Fig 3.10: Parameter Analysis Window(Calculator)

25. BASE PAPER
“Layout Design of LC VCO with Current Mirror Using 0.18 μm Technology” By Namrata
Prasad and Radheshyam Gamad
Presented At: Conference of Wireless Engineering and Technology, 2011
This paper presents a new design of complementary oxide semiconductor voltage
controlled oscillator (CMOS VCO) for improve tuning range and phase noise with low power
consumption. Design is area efficient and easy to implement. Design is carried out in cadence
and schematic editor using 180 nm technology.
In base paper work is carried out under the environment of cadence software and
schematic editor is used for design entry, by using UMC 0.18 μm technology. In that design they
have applied 2V as a supply at the center frequency of 3.3 GHz. Simulation have been done and
obtained values are: the band width of 1.625 GHz, phase noise of –155.78 dBc/Hz @ 1MHz and
–156.89 dBc/Hz @ 100 MHz and phase margin of 180° given in Table 1. Simulated output
voltage responses of this design are presented in Figure 4.1. Phase noise is given in Figure 4.2
with the power consumption of 7.40 mW at supply volt-age of 2V and FOM is 367 dBF.
Table 1 Results of VCO Design
Parameters Namrata Prasad et al
General VCO
(Without current mirror)
Propose VCO
(With current mirror)
Operating Voltage 2V 2V
Technology(CMOS) 0.18um 0.18um
Power Consumption 12.72mW 7.40mW
Operating Frequency 3.3GHz 3.3GHz
Tuning Range 29.8% 4.20%
Phase Noise (dBc/Hz) 63.7 at 1MHz -155.78 at 1MHz
Bandwidth(GHz) 1.611 1.625
FOM(dBF) 141 367
Phase Margin 180 180

26. Fig 4.1: Simulation Response of output response
Fig 4.2:Simulation Result on Phase noise @ 1MHz
We are trying to minimized the power consumption of general VCO (with current
mirrors) by varying the channel length of MOS.

27. SOFTWARE SPECIFICATION
Specifications of CADENCE virtuoso
INTERACTIVE SIMULATION ENVIRONMENT
• Easy to learn and enter data
• Simulation set-ups can be reused
• Quick analysis of multiple simulation data
• Cross probing support for both schematics and layouts
• Multiple measurement syntaxes supported
• Batch scripting waveform display
• Supports multiple Y-axes, strip plots, and Smith Charts
• Built-in waveform calculator
• Independent sub window displays
• Horizontal and vertical measurement markers
• Independent pan and zoom capability
• Signal browser distributed processing
• Parallel analysis option
• Job monitoring and controlling functions
DESIGN INPUTS
• Open Access data objects
• Cadence CDBA data objects
• SPICE
DESIGN OUTPUTS
• SPICE
• PSF Waveform format
• Perl language
• HTML
PLATFORM/OS
• Sun/Solaris
• HP-UX
• Linux

28. SCOPE OF MAJOR PROJECT
This project has a huge future scope. Now a day’s VCO’s are being widely used in
various applications like VCOs for Phase Locked Loops., VCOs for Frequency Translation for
wireless communication, as a result of which the demand of VCO will go on ever increasing in
engineering domain.
This project also aims at developing a VCO that has a lower phase noise comparable to
other present VCO’s. VCO’s with lower phase noise found great applications in wireless
communication. As the domain of communication has broad opportunities of research and
development, VCO’s will always be required and taken into account for research and
development. Another aim of this project is to develop a Low Power VCO. Nowadays electronic
market is growing with huge pace. A huge number of electronic devices like mobile phones,
function generator etc deploy VCO in there circuitry. But in the future scarcity of power is going
to be a great problem. A famous proverb says that ―The Electricity saved is Electricity created‖.
So to save our electricity and to increase the life of batteries we need to minimize the power
losses in the electronic and electrical equipments. A power efficient VCO will prove to be a great
step in this direction of power saving as it will help in minimizing the power losses.

29. REFERENCES
[1.] Namrata Prasad and Radheshyam Gamad, ―Layout Design of LC VCO with Current
Mirror Using 0.18 μm Technology‖, Scientific Research Journal on Wireless Engineering
and Technology, 2011.
[2.] H. Y. Wang, N. J. Wu and G. L. Shou, ―A Novel CMOS Low Phase Noise VCO with
Enlarged Tuning Range,‖ International Conference on Microwave and Millimeter Wave
Technology, Nanjing, 2008.
[3.] N. Prasad, R. S. Gamad and C. B. Kushwah, ―Design of a 2.2 - 4.0 GHz Low Phase Noise
and Low Power LC VCO,‖ International Journal of Computer and Network
Security, 2009.
[4.] P. Dudulwar, K. Shah, H. Le and J. Singh, ―Design and Analysis of Low Power Low
Phase Noise VCO,‖ 13th IEEE International Conference on Mixed Design of Integrated
Circuits and Systems,2006.
[5.] B. Razavi, ―Deign of Analog Complementary MOS Integrated Circuits, Edition 3‖ Tata
McGraw-Hill, Delhi, 2002.
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