design is done using virtuoso tool by cadence in 180 and 45 nm

1. DESIGN OF VOLTAGE
CONTROLLED OSCILLATOR
(LOW POWER CONSUMPTION AND LOW PHASE NOISE)
1
Group No.28 Supervised By-
Saurabh Kumar Mr.Navaid Zafar Rizvi
Vaibhav Jindal
Sharad Sharma

2. CONTENT
• Motivation.
• Introduction.
• Design of VCO.
• Basic parameters of VCO.
• Base Paper.
• Objective.
• Tool Used.
• Design Implemented.
• Results Achieved.
• Future Work & Time Plan.
• References. 2

3. 3
MOTIVATION
• Now a days communication is most necessary thing in
the world.
• Our aim is to make communication device of low
cost, less power consuming and Noise free.
• As Voltage Controlled Oscillator is used on both ends
of Communication.
• Or, we are trying to design a Voltage controlled
Oscillator which Consumed less power and having a
low phase noise

4. 4
INTRODUCTION
• A voltage controlled oscillator is a device that
provides a varying output signal whose frequency
can be adjusted over the range controlled by D.C.
voltage
Voltage Controlled
Oscillator
Vcont ωout

5. Specifications of Ideal Voltage Controlled Oscillator
1. VCO is of Low Noise.
2. Low Power Consumption.
3. High Packing Density.
4. High Frequency.
5. Wide tuning range.
5
VOLTAGE CONTROLLED OSCILLATOR

6. • Noise is injected into an oscillator will disturb both
the amplitude and frequency of oscillation.
• Amplitude noise is usually unimportant but Phase
noise, on the other hand, is essentially a random
deviation in frequency which can also be viewed as a
random variation in the zero crossing points of the
time-dependent oscillator waveform.
.
6
OSCILLATOR PHASE NOISE

7. 7
• Ring Oscillator Topology
• Relaxation Oscillator Topology
• Advantages-
Easy to fabricate
Low power
Small dice area occupancy
Wide tuning range.
• Disadvantage-
As frequency increases phase
noise performance degrades.
• LC Tank Oscillator Topology
• Crystal Oscillator Topology
• Advantages-
Low phase noise performance at
high frequency.
• Disadvantage-
Not suitable in fabrication
High power consumption
Small tuning range
Wave form Oscillators Resonant Oscillators
DIFFERENT OSCILLATORS DESIGN

8. • In this Topology oscillation frequency is decided by
L and C used in tank circuit of oscillator.
• Oscillation Frequency fosc =
• Only Inductor and Capacitor value has to vary
oscillation frequency.
• It is not easy to vary the value of L in monolithic
inductor, but we can change C by using Voltage
dependent capacitor (varactors).
8
LC OSCILLATOR TANK TOPOLOGY

9. • “Layout Design of LC VCO with Current Mirror Using 0.18
μm Technology”
• Namrata Prasad and Radheshyam Gamad
• Department of Electronics & Instrumentation Engineering, Shri
G. S. Institute of Technology and Science, Indore, India.
• Presented in Scientific Research Journal on Wireless
Engineering and Technology, in 2011.
• This paper presents a new design of complementary metal oxide
semiconductor voltage controlled oscillator (CMOS VCO) for
improve tuning range and phase noise with low power
consumption. 9
BASE PAPER

10. Our objective is to implement our Base paper
first in 180nm technology and then in 45nm
technology, and to achieve results better than our
base paper i.e. lower phase noise. We will
accomplish this task by designing an efficient
layout which requires less metal contacts.
10
OBJECTIVE

11. • Cadence Virtuoso.
• It is a Circuit simulator tool which provides capabilities of
designing the circuit, testing of circuit, designing of
layout and its verification.
• It has a feature named Analog Design Environment
(ADE).
• It also support tools like ASSURA, CALIBAR, ICE and
with the help of these tools we can have different checks
on our schematic like DRC, LVS.
11
TOOL USED

12. 12
VCO DESIGN STEPS IN TOOL
• According to designing parameters add a predefine
library(gpdk180& gpdk45) to project
• Design a schematic
Made a symbol for schematic.
• Testing and Verification
Draw a test circuit schematic.
Simulation
Analysis of Phase noise
• Layout Design
Testing and verification

13. • Easy to learn and enter data.
• Simulation set-ups can be reused.
• Quick analysis of multiple simulation data.
• Cross probing support for both schematics and layouts.
• Multiple measurement syntaxes supported.
• Batch scripting waveform display.
• Supports multiple Y-axes, strip plots, and Smith Charts.
• Built-in waveform calculator.
13
FEATURES OF VIRTUOSO

14. • Design aims at minimizing the phase noise of oscillator
circuit.
• Circuit is a combination of both cross coupled VCO and
balanced VCO.
• Due to the combination of two configuration and a LC tank
circuit it produces lower phase noise.
• This configuration also helps in reducing the chip size.
• Power consumption is minimized by using two different
current mirrors.
14
VOLTAGE CONTROLLED OSCILLATOR DESIGN

15. 15
VOLTAGE CONTROLLED OSCILLATOR DESIGN
• In first VCO Schematic-
Using Current Source
Tail has large Capacitance
• In Second VCO Schematic-
Using NMOS
Tail Current Source has a
noise at 2ω0
• In Third VCO Schematic-
Using Current Mirror
No large Capacitance

16. 16
180 nm VCO Schematic
4 N-MOS
4 P-MOS
3 1pF Capacitors
1 1nH Inductor

17. 17
VCO TEST CIRCUIT

18. 18
SIMULATION RESULTS

19. 19
SIMULATION RESULTS(POWER CONSUMPTION)
Calculated Power Is
4.708*10-3

20. 20
SIMULATION RESULTS(PHASE NOISE)

21. 21
SIMULATION RESULTS COMPARE WITH BASE PAPER
Parameters Namrata Prasad et al Proposed VCO
Results
General VCO
(Without current
mirror)
Propose VCO
(With current
mirror)
(VCO with
Current
Mirror)
Operating Voltage 2V 2V 2V
Technology(CMOS) 0.18um 0.18um 0.18um
Power Consumption 12.72mW 7.40mW 4.7mW
Operating Frequency 3.3GHz 3.3GHz 3.3GHz
Phase Noise (dBc/Hz) 63.7 at 100MHz -155.78 at 100MHz -128 at 1MHz
Phase Margin 180 180 180

22. 22
LAYOUT

23. • Layout implementation of present 180nm circuit using
minimum possible metal contacts, which will help in
reducing power loss.
• Designing of schematic and test circuit of present
circuitry in 45nm technology and performing test
analyses.
• Layout implementation in 45nm technology.
• Performing Power and Noise analyses of the circuits.
23
FUTURE WORK

24. • Completion of 180nm design---> 1st week of April
• Completion of 45nm design ---> 3rd week of April
• Completion of final Analyses ---> 4th week of April
24
TIME PLAN

25. • Namrata Prasad and Radheshyam Gamad, “Layout
Design of LC VCO with Current Mirror Using 0.18 μm
Technology”, Scientific Research Journal on Wireless
Engineering and Technology, 2011.
• N. Prasad, R. S. Gamad and C. B. Kushwah, “Design of a
2.2 - 4.0 GHz Low Phase Noise and Low Power LC
VCO,” International Journal of Computer and
Network Security, 2009.
• B. Razavi, “Deign of Analog Complementary MOS
Integrated Circuits, Edition 3” Tata McGraw-
Hill, Delhi, 2002.
• P. Dudulwar, K. Shah, H. Le and J. Singh, “Design and
Analysis of Low Power Low Phase Noise VCO,” 13th
IEEE International Conference on Mixed Design of
Integrated Circuits and Systems,2006.
25
REFRENCES

26. Thank You
? ? ?
26