1. A Top-Level View of
Computer Function
and Interconnection

2. • This chapter focuses on the basic
structures used for computer component
interconnection. As background, the
chapter begins with a brief examination of
the basic components and their interface
requirements. Then a functional overview is
provided. And also examined the use of

3. Computer Components
• The Control Unit and the Arithmetic and
Logic Unit constitute the Central
Processing Unit
• Data and instructions need to get into the
system and results out
– Input/output
• Temporary storage of code and results is
needed
– Main memory

4. Von Neumann Architecture
• Data and Instructions are stored in a
single read-write memory.
• The contents of this memory are
addressable by location, without regard to
the type of data contained there.
• Execution occurs in a sequential fashion
(unless explicitly modified) from one
instruction to the next.

5. Hardware and Software
Approaches

6. More Components
• I/O Components: a module that accepts
data, and instructions and converts them
into instruction signals usable by the
system. It can also report results in the
form of an output module.
• Memory: A place to store instructions and
data temporarily. (Von Neumann pointed
out that the same memory could be used
to store both instructions and data).

7. Computer Components:
Top Level View

8. Computer Function
The basic function performed by a computer
is execution of a program, which consists of set of
instructions stored in memory. The processor does
the actual work by executing instructions specified
in the program. This section provides an overview
of the key elements of the program execution. In
its simplest form, instruction processing consists of
two steps: The processor reads (fetches)
instructions from the memory one at a time and
execute each instruction.

9. Fetch Cycle
• Program Counter (PC) holds address of
next instruction to fetch
• Processor fetches instruction from
memory location pointed to by PC
• Increment PC
– Unless told otherwise
• Instruction loaded into Instruction Register
(IR)
• Processor interprets instruction and
performs required actions

10. Execute Cycle
• Processor-memory
– data transfer between CPU and main memory
• Processor I/O
– Data transfer between CPU and I/O module
• Data processing
– Some arithmetic or logical operation on data
• Control
– Alteration of sequence of operations
– e.g. jump to other location

11. Basic Instruction Cycle

12. Instruction Cycle State Diagram

13. Interrupts
A mechanism by which other modules
may interrupt the normal processing of the
processor.
Classes of Interrupts
Program: Generated by some condition
that occurs as a result of an instruction
execution, such as arithmetic overflow,
division by zero, attempt to execute an
illegal machine instruction, or reference
outside a user’s allowed memory space..

14. Interrupts (cont.)
• Timer: Generated by a timer within the
processor. This allows the operating
system to perform certain functions on a
regular basis.
• I/O: Generated by an I/O controller, to
signal normal completion of an operation
or to signal a variety of error conditions.
• Hardware Failure: Generated by failure
such as power failure or memory parity
error.

15. Interrupts.. Why bother?
• Without the use of interrupts, once this
command is issued, the program must
wait for the I/O device to perform the
requested function. The program might
wait by simply repeatedly performing a
test operation to determine if the I/O
operation is done.

16. Interrupt Cycle
• Added to instruction cycle
• Processor checks for interrupt
– Indicated by an interrupt signal
• If no interrupt, fetch next instruction
• If interrupt pending:
– Suspend execution of current program
– Save context
– Set PC to start address of interrupt handler
routine
– Process interrupt
– Restore context and continue interrupted
program

17. PROGRAM FLOW OF CONTROL
WITHOUT AND WITH INTERRUPTS

18. Instruction Cycle with Interrupts

19. Multiple Interrupts
• Disable interrupts
– Processor will ignore further interrupts whilst
processing one interrupt
– Interrupts remain pending and are checked after first
interrupt has been processed
– Interrupts handled in sequence as they occur
• Define priorities
– Low priority interrupts can be interrupted by higher
priority interrupts
– When higher priority interrupt has been processed,
processor returns to previous interrupt

20. Instruction Cycle (with Interrupts) -
State Diagram

21. Transfer of Controls with
Multiple Interrupts

22. Interconnection Structure
– The collection of paths connecting the various
modules. The design of this structure will
depend on the exchanges that must be made
between modules.
The computer consists of a set of
components or modules of three basic types
(processor, memory, I/O) that communicate
with each other. In effect, computer is a
network of basic modules. Thus, there must
be paths for connecting the modules.

23. Interconnection Structure (cont.)
•Memory: Typically, a memory module will
consists of N words of equal length. Each word is
assigned a unique numerical address
(0,1………..N-1)
•I/O module: From an internal (to the computer
system) point of view, I/O is functionally similar to
memory. Two operations: read and write.
•Processor: reads in instructions and data, writes
out data after processing, and uses control signals
to control overall operation of the system. It also
receives interrupt signals.

24. Interconnection Structure (cont.)

25. Buses
• There are a number of possible
interconnection systems
• Single and multiple BUS structures are
most common
• e.g. Control/Address/Data bus (PC)
• e.g. Unibus (DEC-PDP)

26. What is a Bus?
• A communication pathway connecting two
or more devices
• Usually broadcast
• Often grouped
– A number of channels in one bus
– e.g. 32 bit data bus is 32 separate single bit
channels
• Power lines may not be shown

27. Bus Structure
•Consists from about to 50 to hundreds of
separate lines.
•Each line is assigned a particular meaning
or function.
•3 functional groups:
– Data lines
– Address lines
– Control lines

28. Data Bus
• Carries data
– Remember that there is no difference
between “data” and “instruction” at this level
• Path for moving data between system
modules.

29. Address bus
• Identify the source or destination of data
on the data bus
• e.g. CPU needs to read an instruction
(data) from a given location in memory

30. Control Bus
• Control and timing information
– Memory read/write signal
– Interrupt request
– Clock signals

31. Physical Realization of Bus
Architecture

32. Traditional Bus

33. High Performance Bus

34. Elements of Bus Design
Type: Dedicated, Multiplexed
Method of Arbitration: Distributed, Centralized
Timing: Synchronous, Asynchronous
Bus Width : Address, Data
Data Transfer Type
 Read
 Write
 Read-modify-write
 Read-after-write
 Block

35. Bus Types
• Dedicated
– Separate data & address lines
– Permanently assigned either to one function
or to physical subset of computer components
• Multiplexed
– Shared lines
– Address valid or data valid control line
– Advantage - fewer lines
– Disadvantages
• More complex control
• Ultimate performance

36. Method of Arbitration
•Centralized
– Bus controller or arbiter is
responsible for allocating time on the
bus.
•Distributed
– There is no central controller.

37. Timing
•Synchronous
-The occurrence of events on the bus is
determined by a clock.
•Asynchronous
-The occurrence of one event on a bus
follows and depends on the occurrence of
previous event.

38. Bus Width
– The width of the data bus has an impact on
system performance. The wider the data bus,
the greater the number of bits transferred at
one time. The width of the address bus has
an impact on system capacity. The wider the
address bus, the greater the range of
locations that can be referenced.

39. Data Transfer Types

41. PCI(Peripheral Component
Interconnect) Bus
• is a computer bus for attaching hardware
devices in a computer. The PCI bus
supports the functions found on a
processor bus, but in a standardized
format that is independent of any
particular processor. Devices connected
to the bus appear to the processor to be
connected directly to the processor bus,
and are assigned addresses in the
processor's address space.

42. PCI Bus Lines (required)
• Systems lines
– Including clock and reset
• Address & Data
– 32 time mux lines for address/data
– Interrupt & validate lines
• Interface Control
• Arbitration
– Not shared
– Direct connection to PCI bus arbiter
• Error lines

43. PCI Bus Lines (Optional)
• Interrupt lines
– Not shared
• Cache support
• 64-bit Bus Extension
– Additional 32 lines
– Time multiplexed
– 2 lines to enable devices to agree to use 64-
bit transfer
• JTAG/Boundary Scan
– For testing procedures