SlideShare uma empresa Scribd logo

Csla 130319073823-phpapp01-140821210430-phpapp02

•Transferir como PPTX, PDF•
•
Jayaprakash Nagaruru
Jayaprakash Nagaruru

Efficient design implementation of any ASIC requires an appropriate style which meet the design goals Area Power Speed Multi-dimensional Trade off

Educação
1 de 20
A SEMINAR ON LOW POWER AND AREA EFFICIENT CARRY SELECT ADDER BY Jayaprakash Nagaruru
Objective To design a Carry Select Adder(CSLA) with a optimum utilization of area and power Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 2
Agenda • Introduction • Carry Select Adder • Delay and Area Evaluation • Principle Behind Modification • Modified CSLA • Delay and Area Evaluation • Implementation Results • Conclusion Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 3
Introduction • Efficient design implementation of any ASIC requires an appropriate style which meet the design goals  Area  Power  Speed • Multi-dimensional Trade off Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 4
Carry Select Adder • Ripple carry adder & MUX Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 5
Regular CSLA Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 6
Delay and Power Evaluation Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 7
Contd… Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 8
Regular CSLA Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 9
Principle Behind Modification • Binary to Excess-1 Convertor Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 10
CSLA with BEC Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 11
Modified CSLA Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 12
Delay and Power Evaluation of modified CSLA Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 13
Comparison Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 14
Implementation Results • Typical ASIC flow Using 0.18u Technology for regular and modified CSLA Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 15
Graphical Analysis Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 16
Conclusion No. of Bits Area Reduction (%) 8 9.7 16 15 32 16.7 64 17.4 Power Reduction (%) 7.6 10.56 13.63 15.46 Delay Overhead (%) 14 9.8 6.7 3.76 Power Delay Product(%) 5.2 1.76 8.18 12.28 Area Delay Product(%) 2.9 6.7 11 14.4 • Despite with a little delay overhead a optimized carry select adder has been designed Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 17
Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 18
References Bibliography • IEEE 2012 paper on Low Power & Area Efficient CSLA by B Ram Kumar & H M Kittur • J M Rabaey Digital Integrated Circuits • IJCE 2012 paper on VLSI Realization Of Fast Carry Adder in Binary Excess by Santhosh Kannan and Bhanumathi Webography • http://en.wikipedia.org/wiki/Ca rry-select_adder • http://ieeexplore.ieee.org/xpl /login.jsp?tp=&arnumber=540 7919&url=http%3A%2F%2Fiee explore.ieee.org%2Fxpls%2Fab s_all.jsp%3Farnumber%3D540 7919 Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 19
Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 20

Recomendados

Design and development of carry select adder
Design and development of carry select adderDesign and development of carry select adder
Design and development of carry select adderABIN THOMAS
 
Area Delay Power Efficient and Implementation of Modified Square-Root Carry S...
Area Delay Power Efficient and Implementation of Modified Square-Root Carry S...Area Delay Power Efficient and Implementation of Modified Square-Root Carry S...
Area Delay Power Efficient and Implementation of Modified Square-Root Carry S...IJTET Journal
 
Area–delay–power efficient carry select adder
Area–delay–power efficient carry select adderArea–delay–power efficient carry select adder
Area–delay–power efficient carry select adderLogicMindtech Nologies
 
Hybrid Adder
Hybrid AdderHybrid Adder
Hybrid AdderGuru Prasanth
 
Design and Verification of Area Efficient Carry Select Adder
Design and Verification of Area Efficient Carry Select AdderDesign and Verification of Area Efficient Carry Select Adder
Design and Verification of Area Efficient Carry Select Adderijsrd.com
 
High Speed Carryselect Adder
High Speed Carryselect AdderHigh Speed Carryselect Adder
High Speed Carryselect Adderijsrd.com
 
Low power & area efficient carry select adder
Low power & area efficient carry select adderLow power & area efficient carry select adder
Low power & area efficient carry select adderSai Vara Prasad P
 
Project report on design & implementation of high speed carry select adder
Project report on design & implementation of high speed carry select adderProject report on design & implementation of high speed carry select adder
Project report on design & implementation of high speed carry select adderssingh7603
 

Recomendados

Design and development of carry select adder
Design and development of carry select adderDesign and development of carry select adder
Design and development of carry select adderABIN THOMAS
 
Area Delay Power Efficient and Implementation of Modified Square-Root Carry S...
Area Delay Power Efficient and Implementation of Modified Square-Root Carry S...Area Delay Power Efficient and Implementation of Modified Square-Root Carry S...
Area Delay Power Efficient and Implementation of Modified Square-Root Carry S...IJTET Journal
 
Area–delay–power efficient carry select adder
Area–delay–power efficient carry select adderArea–delay–power efficient carry select adder
Area–delay–power efficient carry select adderLogicMindtech Nologies
 
Hybrid Adder
Hybrid AdderHybrid Adder
Hybrid AdderGuru Prasanth
 
Design and Verification of Area Efficient Carry Select Adder
Design and Verification of Area Efficient Carry Select AdderDesign and Verification of Area Efficient Carry Select Adder
Design and Verification of Area Efficient Carry Select Adderijsrd.com
 
High Speed Carryselect Adder
High Speed Carryselect AdderHigh Speed Carryselect Adder
High Speed Carryselect Adderijsrd.com
 
Low power & area efficient carry select adder
Low power & area efficient carry select adderLow power & area efficient carry select adder
Low power & area efficient carry select adderSai Vara Prasad P
 
Project report on design & implementation of high speed carry select adder
Project report on design & implementation of high speed carry select adderProject report on design & implementation of high speed carry select adder
Project report on design & implementation of high speed carry select adderssingh7603
 
carry select adder
carry select addercarry select adder
carry select adderfaisal_hussain2008
 
Implementation of Area Effective Carry Select Adders
Implementation of Area Effective Carry Select AddersImplementation of Area Effective Carry Select Adders
Implementation of Area Effective Carry Select AddersKumar Goud
 
Implementation of Low Power and Area Efficient Carry Select Adder
Implementation of Low Power and Area Efficient Carry Select AdderImplementation of Low Power and Area Efficient Carry Select Adder
Implementation of Low Power and Area Efficient Carry Select Adderinventionjournals
 
DESIGN AND IMPLEMENTATION OF LOW POWER ALU USING CLOCK GATING AND CARRY SELEC...
DESIGN AND IMPLEMENTATION OF LOW POWER ALU USING CLOCK GATING AND CARRY SELEC...DESIGN AND IMPLEMENTATION OF LOW POWER ALU USING CLOCK GATING AND CARRY SELEC...
DESIGN AND IMPLEMENTATION OF LOW POWER ALU USING CLOCK GATING AND CARRY SELEC...IAEME Publication
 
Design and Implementation of Low-Power and Area-Efficient 64 bit CSLA using VHDL
Design and Implementation of Low-Power and Area-Efficient 64 bit CSLA using VHDLDesign and Implementation of Low-Power and Area-Efficient 64 bit CSLA using VHDL
Design and Implementation of Low-Power and Area-Efficient 64 bit CSLA using VHDLIJSRD
 
Design of Low Power Energy Efficient Carry Select Adder Using CMOS Technology
Design of Low Power Energy Efficient Carry Select Adder Using CMOS TechnologyDesign of Low Power Energy Efficient Carry Select Adder Using CMOS Technology
Design of Low Power Energy Efficient Carry Select Adder Using CMOS TechnologyAssociate Professor in VSB Coimbatore
 
Final ppt
Final pptFinal ppt
Final pptBhamidipati Gayatri
 
DESIGN AND PERFORMANCE ANALYSIS OF BINARY ADDERS_edited
DESIGN AND PERFORMANCE ANALYSIS OF BINARY ADDERS_editedDESIGN AND PERFORMANCE ANALYSIS OF BINARY ADDERS_edited
DESIGN AND PERFORMANCE ANALYSIS OF BINARY ADDERS_editedShital Badaik
 
High speed and energy-efficient carry skip adder operating under a wide range...
High speed and energy-efficient carry skip adder operating under a wide range...High speed and energy-efficient carry skip adder operating under a wide range...
High speed and energy-efficient carry skip adder operating under a wide range...LogicMindtech Nologies
 
A Novel Efficient VLSI Architecture Modified 16-B SQRT Carry Select Adder
A Novel Efficient VLSI Architecture Modified 16-B SQRT Carry Select AdderA Novel Efficient VLSI Architecture Modified 16-B SQRT Carry Select Adder
A Novel Efficient VLSI Architecture Modified 16-B SQRT Carry Select AdderIJERD Editor
 
Efficient Design of Ripple Carry Adder and Carry Skip Adder with Low Quantum ...
Efficient Design of Ripple Carry Adder and Carry Skip Adder with Low Quantum ...Efficient Design of Ripple Carry Adder and Carry Skip Adder with Low Quantum ...
Efficient Design of Ripple Carry Adder and Carry Skip Adder with Low Quantum ...IJERA Editor
 
FPGA Implementation of High Speed Architecture of CSLA using D-Latches
FPGA Implementation of High Speed Architecture of CSLA using D-LatchesFPGA Implementation of High Speed Architecture of CSLA using D-Latches
FPGA Implementation of High Speed Architecture of CSLA using D-LatchesEditor IJMTER
 
Cmos Arithmetic Circuits
Cmos Arithmetic CircuitsCmos Arithmetic Circuits
Cmos Arithmetic Circuitsankitgoel
 
32-bit unsigned multiplier by using CSLA & CLAA
32-bit unsigned multiplier by using CSLA & CLAA32-bit unsigned multiplier by using CSLA & CLAA
32-bit unsigned multiplier by using CSLA & CLAAGanesh Sambasivarao
 
implementation and comparision of effective area efficient architecture for CSLA
implementation and comparision of effective area efficient architecture for CSLAimplementation and comparision of effective area efficient architecture for CSLA
implementation and comparision of effective area efficient architecture for CSLAvenkatesh nayakoti
 
Design of Low-Power High-Speed Truncation-Error-Tolerant Adder
Design of Low-Power High-Speed Truncation-Error-Tolerant Adder Design of Low-Power High-Speed Truncation-Error-Tolerant Adder
Design of Low-Power High-Speed Truncation-Error-Tolerant Adder Sravankumar Samboju
 
Array multiplier
Array multiplierArray multiplier
Array multiplierMathew George
 
Design Of 64-Bit Parallel Prefix VLSI Adder For High Speed Arithmetic Circuits
Design Of 64-Bit Parallel Prefix VLSI Adder For High Speed Arithmetic CircuitsDesign Of 64-Bit Parallel Prefix VLSI Adder For High Speed Arithmetic Circuits
Design Of 64-Bit Parallel Prefix VLSI Adder For High Speed Arithmetic CircuitsIJRES Journal
 
design of high speed performance 64bit mac unit
design of high speed performance 64bit mac unitdesign of high speed performance 64bit mac unit
design of high speed performance 64bit mac unitShiva Narayan Reddy
 
Designing and Characterization of koggestone, Sparse Kogge stone, Spanning tr...
Designing and Characterization of koggestone, Sparse Kogge stone, Spanning tr...Designing and Characterization of koggestone, Sparse Kogge stone, Spanning tr...
Designing and Characterization of koggestone, Sparse Kogge stone, Spanning tr...IJMER
 
Design & implementation of high speed carry select adder
Design & implementation of high speed carry select adderDesign & implementation of high speed carry select adder
Design & implementation of high speed carry select adderssingh7603
 
CSLA and WTM using GDI Technique
CSLA and WTM using GDI TechniqueCSLA and WTM using GDI Technique
CSLA and WTM using GDI TechniqueNishant Yaduvanshi
 

Mais conteúdo relacionado

Mais procurados

Implementation of Area Effective Carry Select Adders
Implementation of Area Effective Carry Select AddersImplementation of Area Effective Carry Select Adders
Implementation of Area Effective Carry Select AddersKumar Goud
 
Implementation of Low Power and Area Efficient Carry Select Adder
Implementation of Low Power and Area Efficient Carry Select AdderImplementation of Low Power and Area Efficient Carry Select Adder
Implementation of Low Power and Area Efficient Carry Select Adderinventionjournals
 
DESIGN AND IMPLEMENTATION OF LOW POWER ALU USING CLOCK GATING AND CARRY SELEC...
DESIGN AND IMPLEMENTATION OF LOW POWER ALU USING CLOCK GATING AND CARRY SELEC...DESIGN AND IMPLEMENTATION OF LOW POWER ALU USING CLOCK GATING AND CARRY SELEC...
DESIGN AND IMPLEMENTATION OF LOW POWER ALU USING CLOCK GATING AND CARRY SELEC...IAEME Publication
 
Design and Implementation of Low-Power and Area-Efficient 64 bit CSLA using VHDL
Design and Implementation of Low-Power and Area-Efficient 64 bit CSLA using VHDLDesign and Implementation of Low-Power and Area-Efficient 64 bit CSLA using VHDL
Design and Implementation of Low-Power and Area-Efficient 64 bit CSLA using VHDLIJSRD
 
Design of Low Power Energy Efficient Carry Select Adder Using CMOS Technology
Design of Low Power Energy Efficient Carry Select Adder Using CMOS TechnologyDesign of Low Power Energy Efficient Carry Select Adder Using CMOS Technology
Design of Low Power Energy Efficient Carry Select Adder Using CMOS TechnologyAssociate Professor in VSB Coimbatore
 
DESIGN AND PERFORMANCE ANALYSIS OF BINARY ADDERS_edited
DESIGN AND PERFORMANCE ANALYSIS OF BINARY ADDERS_editedDESIGN AND PERFORMANCE ANALYSIS OF BINARY ADDERS_edited
DESIGN AND PERFORMANCE ANALYSIS OF BINARY ADDERS_editedShital Badaik
 
High speed and energy-efficient carry skip adder operating under a wide range...
High speed and energy-efficient carry skip adder operating under a wide range...High speed and energy-efficient carry skip adder operating under a wide range...
High speed and energy-efficient carry skip adder operating under a wide range...LogicMindtech Nologies
 
A Novel Efficient VLSI Architecture Modified 16-B SQRT Carry Select Adder
A Novel Efficient VLSI Architecture Modified 16-B SQRT Carry Select AdderA Novel Efficient VLSI Architecture Modified 16-B SQRT Carry Select Adder
A Novel Efficient VLSI Architecture Modified 16-B SQRT Carry Select AdderIJERD Editor
 
Efficient Design of Ripple Carry Adder and Carry Skip Adder with Low Quantum ...
Efficient Design of Ripple Carry Adder and Carry Skip Adder with Low Quantum ...Efficient Design of Ripple Carry Adder and Carry Skip Adder with Low Quantum ...
Efficient Design of Ripple Carry Adder and Carry Skip Adder with Low Quantum ...IJERA Editor
 
FPGA Implementation of High Speed Architecture of CSLA using D-Latches
FPGA Implementation of High Speed Architecture of CSLA using D-LatchesFPGA Implementation of High Speed Architecture of CSLA using D-Latches
FPGA Implementation of High Speed Architecture of CSLA using D-LatchesEditor IJMTER
 
Cmos Arithmetic Circuits
Cmos Arithmetic CircuitsCmos Arithmetic Circuits
Cmos Arithmetic Circuitsankitgoel
 
32-bit unsigned multiplier by using CSLA & CLAA
32-bit unsigned multiplier by using CSLA & CLAA32-bit unsigned multiplier by using CSLA & CLAA
32-bit unsigned multiplier by using CSLA & CLAAGanesh Sambasivarao
 
implementation and comparision of effective area efficient architecture for CSLA
implementation and comparision of effective area efficient architecture for CSLAimplementation and comparision of effective area efficient architecture for CSLA
implementation and comparision of effective area efficient architecture for CSLAvenkatesh nayakoti
 
Design of Low-Power High-Speed Truncation-Error-Tolerant Adder
Design of Low-Power High-Speed Truncation-Error-Tolerant Adder Design of Low-Power High-Speed Truncation-Error-Tolerant Adder
Design of Low-Power High-Speed Truncation-Error-Tolerant Adder Sravankumar Samboju
 
Design Of 64-Bit Parallel Prefix VLSI Adder For High Speed Arithmetic Circuits
Design Of 64-Bit Parallel Prefix VLSI Adder For High Speed Arithmetic CircuitsDesign Of 64-Bit Parallel Prefix VLSI Adder For High Speed Arithmetic Circuits
Design Of 64-Bit Parallel Prefix VLSI Adder For High Speed Arithmetic CircuitsIJRES Journal
 
design of high speed performance 64bit mac unit
design of high speed performance 64bit mac unitdesign of high speed performance 64bit mac unit
design of high speed performance 64bit mac unitShiva Narayan Reddy
 
Designing and Characterization of koggestone, Sparse Kogge stone, Spanning tr...
Designing and Characterization of koggestone, Sparse Kogge stone, Spanning tr...Designing and Characterization of koggestone, Sparse Kogge stone, Spanning tr...
Designing and Characterization of koggestone, Sparse Kogge stone, Spanning tr...IJMER
 

Mais procurados (20)

carry select adder
carry select addercarry select adder
carry select adder
 
Implementation of Area Effective Carry Select Adders
Implementation of Area Effective Carry Select AddersImplementation of Area Effective Carry Select Adders
Implementation of Area Effective Carry Select Adders
 
Implementation of Low Power and Area Efficient Carry Select Adder
Implementation of Low Power and Area Efficient Carry Select AdderImplementation of Low Power and Area Efficient Carry Select Adder
Implementation of Low Power and Area Efficient Carry Select Adder
 
DESIGN AND IMPLEMENTATION OF LOW POWER ALU USING CLOCK GATING AND CARRY SELEC...
DESIGN AND IMPLEMENTATION OF LOW POWER ALU USING CLOCK GATING AND CARRY SELEC...DESIGN AND IMPLEMENTATION OF LOW POWER ALU USING CLOCK GATING AND CARRY SELEC...
DESIGN AND IMPLEMENTATION OF LOW POWER ALU USING CLOCK GATING AND CARRY SELEC...
 
Design and Implementation of Low-Power and Area-Efficient 64 bit CSLA using VHDL
Design and Implementation of Low-Power and Area-Efficient 64 bit CSLA using VHDLDesign and Implementation of Low-Power and Area-Efficient 64 bit CSLA using VHDL
Design and Implementation of Low-Power and Area-Efficient 64 bit CSLA using VHDL
 
Design of Low Power Energy Efficient Carry Select Adder Using CMOS Technology
Design of Low Power Energy Efficient Carry Select Adder Using CMOS TechnologyDesign of Low Power Energy Efficient Carry Select Adder Using CMOS Technology
Design of Low Power Energy Efficient Carry Select Adder Using CMOS Technology
 
Final ppt
Final pptFinal ppt
Final ppt
 
DESIGN AND PERFORMANCE ANALYSIS OF BINARY ADDERS_edited
DESIGN AND PERFORMANCE ANALYSIS OF BINARY ADDERS_editedDESIGN AND PERFORMANCE ANALYSIS OF BINARY ADDERS_edited
DESIGN AND PERFORMANCE ANALYSIS OF BINARY ADDERS_edited
 
High speed and energy-efficient carry skip adder operating under a wide range...
High speed and energy-efficient carry skip adder operating under a wide range...High speed and energy-efficient carry skip adder operating under a wide range...
High speed and energy-efficient carry skip adder operating under a wide range...
 
A Novel Efficient VLSI Architecture Modified 16-B SQRT Carry Select Adder
A Novel Efficient VLSI Architecture Modified 16-B SQRT Carry Select AdderA Novel Efficient VLSI Architecture Modified 16-B SQRT Carry Select Adder
A Novel Efficient VLSI Architecture Modified 16-B SQRT Carry Select Adder
 
Efficient Design of Ripple Carry Adder and Carry Skip Adder with Low Quantum ...
Efficient Design of Ripple Carry Adder and Carry Skip Adder with Low Quantum ...Efficient Design of Ripple Carry Adder and Carry Skip Adder with Low Quantum ...
Efficient Design of Ripple Carry Adder and Carry Skip Adder with Low Quantum ...
 
FPGA Implementation of High Speed Architecture of CSLA using D-Latches
FPGA Implementation of High Speed Architecture of CSLA using D-LatchesFPGA Implementation of High Speed Architecture of CSLA using D-Latches
FPGA Implementation of High Speed Architecture of CSLA using D-Latches
 
Cmos Arithmetic Circuits
Cmos Arithmetic CircuitsCmos Arithmetic Circuits
Cmos Arithmetic Circuits
 
32-bit unsigned multiplier by using CSLA & CLAA
32-bit unsigned multiplier by using CSLA & CLAA32-bit unsigned multiplier by using CSLA & CLAA
32-bit unsigned multiplier by using CSLA & CLAA
 
implementation and comparision of effective area efficient architecture for CSLA
implementation and comparision of effective area efficient architecture for CSLAimplementation and comparision of effective area efficient architecture for CSLA
implementation and comparision of effective area efficient architecture for CSLA
 
Design of Low-Power High-Speed Truncation-Error-Tolerant Adder
Design of Low-Power High-Speed Truncation-Error-Tolerant Adder Design of Low-Power High-Speed Truncation-Error-Tolerant Adder
Design of Low-Power High-Speed Truncation-Error-Tolerant Adder
 
Array multiplier
Array multiplierArray multiplier
Array multiplier
 
Design Of 64-Bit Parallel Prefix VLSI Adder For High Speed Arithmetic Circuits
Design Of 64-Bit Parallel Prefix VLSI Adder For High Speed Arithmetic CircuitsDesign Of 64-Bit Parallel Prefix VLSI Adder For High Speed Arithmetic Circuits
Design Of 64-Bit Parallel Prefix VLSI Adder For High Speed Arithmetic Circuits
 
design of high speed performance 64bit mac unit
design of high speed performance 64bit mac unitdesign of high speed performance 64bit mac unit
design of high speed performance 64bit mac unit
 
Designing and Characterization of koggestone, Sparse Kogge stone, Spanning tr...
Designing and Characterization of koggestone, Sparse Kogge stone, Spanning tr...Designing and Characterization of koggestone, Sparse Kogge stone, Spanning tr...
Designing and Characterization of koggestone, Sparse Kogge stone, Spanning tr...
 

Destaque

Design & implementation of high speed carry select adder
Design & implementation of high speed carry select adderDesign & implementation of high speed carry select adder
Design & implementation of high speed carry select adderssingh7603
 
CSLA and WTM using GDI Technique
CSLA and WTM using GDI TechniqueCSLA and WTM using GDI Technique
CSLA and WTM using GDI TechniqueNishant Yaduvanshi
 
Enhanced low power, fast and area efficient carry select adder
Enhanced low power, fast and area efficient carry select adderEnhanced low power, fast and area efficient carry select adder
Enhanced low power, fast and area efficient carry select addereSAT Publishing House
 
128 bit low power and area efficient carry select adder amit bakshi academia
128 bit low power and area efficient carry select adder amit bakshi academia128 bit low power and area efficient carry select adder amit bakshi academia
128 bit low power and area efficient carry select adder amit bakshi academiagopi448
 
Design of a high speed low power Brent Kung Adder in 45nM CMOS
Design of a high speed low power Brent Kung Adder in 45nM CMOSDesign of a high speed low power Brent Kung Adder in 45nM CMOS
Design of a high speed low power Brent Kung Adder in 45nM CMOSNirav Desai
 
Gate Diffusion Input Technology (Very Large Scale Integration)
Gate Diffusion Input Technology (Very Large Scale Integration)Gate Diffusion Input Technology (Very Large Scale Integration)
Gate Diffusion Input Technology (Very Large Scale Integration)Ashwin Shroff
 
VHDL Packages, Coding Styles for Arithmetic Operations and VHDL-200x Additions
VHDL Packages, Coding Styles for Arithmetic Operations and VHDL-200x AdditionsVHDL Packages, Coding Styles for Arithmetic Operations and VHDL-200x Additions
VHDL Packages, Coding Styles for Arithmetic Operations and VHDL-200x AdditionsAmal Khailtash
 
VLSI Implementation of Vedic Multiplier Using Urdhva– Tiryakbhyam Sutra in VH...
VLSI Implementation of Vedic Multiplier Using Urdhva– Tiryakbhyam Sutra in VH...VLSI Implementation of Vedic Multiplier Using Urdhva– Tiryakbhyam Sutra in VH...
VLSI Implementation of Vedic Multiplier Using Urdhva– Tiryakbhyam Sutra in VH...iosrjce
 
1.area efficient carry select adder
1.area efficient carry select adder1.area efficient carry select adder
1.area efficient carry select adderKUMARASWAMY JINNE
 
Slideshare Powerpoint presentation
Slideshare Powerpoint presentationSlideshare Powerpoint presentation
Slideshare Powerpoint presentationelliehood
 

Destaque (12)

Design & implementation of high speed carry select adder
Design & implementation of high speed carry select adderDesign & implementation of high speed carry select adder
Design & implementation of high speed carry select adder
 
CSLA and WTM using GDI Technique
CSLA and WTM using GDI TechniqueCSLA and WTM using GDI Technique
CSLA and WTM using GDI Technique
 
Enhanced low power, fast and area efficient carry select adder
Enhanced low power, fast and area efficient carry select adderEnhanced low power, fast and area efficient carry select adder
Enhanced low power, fast and area efficient carry select adder
 
128 bit low power and area efficient carry select adder amit bakshi academia
128 bit low power and area efficient carry select adder amit bakshi academia128 bit low power and area efficient carry select adder amit bakshi academia
128 bit low power and area efficient carry select adder amit bakshi academia
 
Design of a high speed low power Brent Kung Adder in 45nM CMOS
Design of a high speed low power Brent Kung Adder in 45nM CMOSDesign of a high speed low power Brent Kung Adder in 45nM CMOS
Design of a high speed low power Brent Kung Adder in 45nM CMOS
 
Gate Diffusion Input Technology (Very Large Scale Integration)
Gate Diffusion Input Technology (Very Large Scale Integration)Gate Diffusion Input Technology (Very Large Scale Integration)
Gate Diffusion Input Technology (Very Large Scale Integration)
 
Vhdl programming
Vhdl programmingVhdl programming
Vhdl programming
 
VHDL Packages, Coding Styles for Arithmetic Operations and VHDL-200x Additions
VHDL Packages, Coding Styles for Arithmetic Operations and VHDL-200x AdditionsVHDL Packages, Coding Styles for Arithmetic Operations and VHDL-200x Additions
VHDL Packages, Coding Styles for Arithmetic Operations and VHDL-200x Additions
 
VLSI Implementation of Vedic Multiplier Using Urdhva– Tiryakbhyam Sutra in VH...
VLSI Implementation of Vedic Multiplier Using Urdhva– Tiryakbhyam Sutra in VH...VLSI Implementation of Vedic Multiplier Using Urdhva– Tiryakbhyam Sutra in VH...
VLSI Implementation of Vedic Multiplier Using Urdhva– Tiryakbhyam Sutra in VH...
 
1.area efficient carry select adder
1.area efficient carry select adder1.area efficient carry select adder
1.area efficient carry select adder
 
Slideshare Powerpoint presentation
Slideshare Powerpoint presentationSlideshare Powerpoint presentation
Slideshare Powerpoint presentation
 
Slideshare ppt
Slideshare pptSlideshare ppt
Slideshare ppt
 

Semelhante a Csla 130319073823-phpapp01-140821210430-phpapp02

Fast block motion estimation with 8 bit partial sums using SIMD architecture
Fast block motion estimation with 8 bit partial sums using SIMD architectureFast block motion estimation with 8 bit partial sums using SIMD architecture
Fast block motion estimation with 8 bit partial sums using SIMD architectureahmad abdelhafeez
 
Kaizen_ABB_IT_18Nov13
Kaizen_ABB_IT_18Nov13Kaizen_ABB_IT_18Nov13
Kaizen_ABB_IT_18Nov13Munj Bhatt
 
Data Science Projects @ Runnr
Data Science Projects @ RunnrData Science Projects @ Runnr
Data Science Projects @ RunnrAnkit Jain
 
Review on optimized area,delay and power efficient carry select adder using n...
Review on optimized area,delay and power efficient carry select adder using n...Review on optimized area,delay and power efficient carry select adder using n...
Review on optimized area,delay and power efficient carry select adder using n...IRJET Journal
 
Statistical power consumption analysis and modeling
Statistical power consumption analysis and modelingStatistical power consumption analysis and modeling
Statistical power consumption analysis and modelingnadikari123
 
Three phase BLDC motor
Three phase BLDC motorThree phase BLDC motor
Three phase BLDC motorAnoop S
 
Samsung SDI Plant Project
Samsung SDI Plant ProjectSamsung SDI Plant Project
Samsung SDI Plant ProjectEdmond Kwok
 
Design and Implementation of AMBA ASB APB Bridge
Design and Implementation of AMBA ASB APB BridgeDesign and Implementation of AMBA ASB APB Bridge
Design and Implementation of AMBA ASB APB BridgeManu BN
 
Design and analysis of knuckle and hub of FSAE race car
Design and analysis of knuckle and hub of FSAE race carDesign and analysis of knuckle and hub of FSAE race car
Design and analysis of knuckle and hub of FSAE race carSangram Pisat
 
street light intensity control using micro-controller
street light intensity control using micro-controller street light intensity control using micro-controller
street light intensity control using micro-controller krunal103
 

Semelhante a Csla 130319073823-phpapp01-140821210430-phpapp02 (12)

Fast block motion estimation with 8 bit partial sums using SIMD architecture
Fast block motion estimation with 8 bit partial sums using SIMD architectureFast block motion estimation with 8 bit partial sums using SIMD architecture
Fast block motion estimation with 8 bit partial sums using SIMD architecture
 
Kaizen_ABB_IT_18Nov13
Kaizen_ABB_IT_18Nov13Kaizen_ABB_IT_18Nov13
Kaizen_ABB_IT_18Nov13
 
Data Science Projects @ Runnr
Data Science Projects @ RunnrData Science Projects @ Runnr
Data Science Projects @ Runnr
 
Review on optimized area,delay and power efficient carry select adder using n...
Review on optimized area,delay and power efficient carry select adder using n...Review on optimized area,delay and power efficient carry select adder using n...
Review on optimized area,delay and power efficient carry select adder using n...
 
Statistical power consumption analysis and modeling
Statistical power consumption analysis and modelingStatistical power consumption analysis and modeling
Statistical power consumption analysis and modeling
 
Three phase BLDC motor
Three phase BLDC motorThree phase BLDC motor
Three phase BLDC motor
 
Samsung SDI Plant Project
Samsung SDI Plant ProjectSamsung SDI Plant Project
Samsung SDI Plant Project
 
Design and Implementation of AMBA ASB APB Bridge
Design and Implementation of AMBA ASB APB BridgeDesign and Implementation of AMBA ASB APB Bridge
Design and Implementation of AMBA ASB APB Bridge
 
Design and analysis of knuckle and hub of FSAE race car
Design and analysis of knuckle and hub of FSAE race carDesign and analysis of knuckle and hub of FSAE race car
Design and analysis of knuckle and hub of FSAE race car
 
Optimized ACH W
Optimized ACH WOptimized ACH W
Optimized ACH W
 
QRM Project
QRM ProjectQRM Project
QRM Project
 
street light intensity control using micro-controller
street light intensity control using micro-controller street light intensity control using micro-controller
street light intensity control using micro-controller
 

Mais de Jayaprakash Nagaruru

3-D Mouse controlling with wrist watch
3-D Mouse controlling with wrist watch 3-D Mouse controlling with wrist watch
3-D Mouse controlling with wrist watch Jayaprakash Nagaruru
 
eZ430-Chronos Development Tool (watch)
eZ430-Chronos Development Tool (watch)eZ430-Chronos Development Tool (watch)
eZ430-Chronos Development Tool (watch)Jayaprakash Nagaruru
 
Getting started with open cv in raspberry pi
Getting started with open cv in raspberry piGetting started with open cv in raspberry pi
Getting started with open cv in raspberry piJayaprakash Nagaruru
 
Ultra Broadband for personal area networks using fiber commnications
Ultra Broadband for personal area networks using fiber commnicationsUltra Broadband for personal area networks using fiber commnications
Ultra Broadband for personal area networks using fiber commnicationsJayaprakash Nagaruru
 

Mais de Jayaprakash Nagaruru (9)

3-D Mouse controlling with wrist watch
3-D Mouse controlling with wrist watch 3-D Mouse controlling with wrist watch
3-D Mouse controlling with wrist watch
 
eZ430-Chronos Development Tool (watch)
eZ430-Chronos Development Tool (watch)eZ430-Chronos Development Tool (watch)
eZ430-Chronos Development Tool (watch)
 
Virtual Keyboard Technology
Virtual Keyboard TechnologyVirtual Keyboard Technology
Virtual Keyboard Technology
 
Real-Time Streaming Protocol -QOS
Real-Time Streaming Protocol -QOSReal-Time Streaming Protocol -QOS
Real-Time Streaming Protocol -QOS
 
Getting started with open cv in raspberry pi
Getting started with open cv in raspberry piGetting started with open cv in raspberry pi
Getting started with open cv in raspberry pi
 
Computer Networking
Computer NetworkingComputer Networking
Computer Networking
 
Real-Time Streaming Protocol
Real-Time Streaming Protocol Real-Time Streaming Protocol
Real-Time Streaming Protocol
 
Ultra Broadband for personal area networks using fiber commnications
Ultra Broadband for personal area networks using fiber commnicationsUltra Broadband for personal area networks using fiber commnications
Ultra Broadband for personal area networks using fiber commnications
 
Tcp over 4 g
Tcp over 4 gTcp over 4 g
Tcp over 4 g
 

Último

ACC 2024 Chronicles. Cardiology. Exam.pdf
ACC 2024 Chronicles. Cardiology. Exam.pdfACC 2024 Chronicles. Cardiology. Exam.pdf
ACC 2024 Chronicles. Cardiology. Exam.pdfSpandanaRallapalli
 
Procuring digital preservation CAN be quick and painless with our new dynamic...
Procuring digital preservation CAN be quick and painless with our new dynamic...Procuring digital preservation CAN be quick and painless with our new dynamic...
Procuring digital preservation CAN be quick and painless with our new dynamic...Jisc
 
ECONOMIC CONTEXT - LONG FORM TV DRAMA - PPT
ECONOMIC CONTEXT - LONG FORM TV DRAMA - PPTECONOMIC CONTEXT - LONG FORM TV DRAMA - PPT
ECONOMIC CONTEXT - LONG FORM TV DRAMA - PPTiammrhaywood
 
Gas measurement O2,Co2,& ph) 04/2024.pptx
Gas measurement O2,Co2,& ph) 04/2024.pptxGas measurement O2,Co2,& ph) 04/2024.pptx
Gas measurement O2,Co2,& ph) 04/2024.pptxDr.Ibrahim Hassaan
 
ANG SEKTOR NG agrikultura.pptx QUARTER 4
ANG SEKTOR NG agrikultura.pptx QUARTER 4ANG SEKTOR NG agrikultura.pptx QUARTER 4
ANG SEKTOR NG agrikultura.pptx QUARTER 4MiaBumagat1
 
ENGLISH 7_Q4_LESSON 2_ Employing a Variety of Strategies for Effective Interp...
ENGLISH 7_Q4_LESSON 2_ Employing a Variety of Strategies for Effective Interp...ENGLISH 7_Q4_LESSON 2_ Employing a Variety of Strategies for Effective Interp...
ENGLISH 7_Q4_LESSON 2_ Employing a Variety of Strategies for Effective Interp...JhezDiaz1
 
HỌC TỐT TIẾNG ANH 11 THEO CHƯƠNG TRÌNH GLOBAL SUCCESS ĐÁP ÁN CHI TIẾT - CẢ NĂ...
HỌC TỐT TIẾNG ANH 11 THEO CHƯƠNG TRÌNH GLOBAL SUCCESS ĐÁP ÁN CHI TIẾT - CẢ NĂ...HỌC TỐT TIẾNG ANH 11 THEO CHƯƠNG TRÌNH GLOBAL SUCCESS ĐÁP ÁN CHI TIẾT - CẢ NĂ...
HỌC TỐT TIẾNG ANH 11 THEO CHƯƠNG TRÌNH GLOBAL SUCCESS ĐÁP ÁN CHI TIẾT - CẢ NĂ...Nguyen Thanh Tu Collection
 
Keynote by Prof. Wurzer at Nordex about IP-design
Keynote by Prof. Wurzer at Nordex about IP-designKeynote by Prof. Wurzer at Nordex about IP-design
Keynote by Prof. Wurzer at Nordex about IP-designMIPLM
 
Earth Day Presentation wow hello nice great
Earth Day Presentation wow hello nice greatEarth Day Presentation wow hello nice great
Earth Day Presentation wow hello nice greatYousafMalik24
 
DATA STRUCTURE AND ALGORITHM for beginners
DATA STRUCTURE AND ALGORITHM for beginnersDATA STRUCTURE AND ALGORITHM for beginners
DATA STRUCTURE AND ALGORITHM for beginnersSabitha Banu
 
ISYU TUNGKOL SA SEKSWLADIDA (ISSUE ABOUT SEXUALITY
ISYU TUNGKOL SA SEKSWLADIDA (ISSUE ABOUT SEXUALITYISYU TUNGKOL SA SEKSWLADIDA (ISSUE ABOUT SEXUALITY
ISYU TUNGKOL SA SEKSWLADIDA (ISSUE ABOUT SEXUALITYKayeClaireEstoconing
 
Inclusivity Essentials_ Creating Accessible Websites for Nonprofits .pdf
Inclusivity Essentials_ Creating Accessible Websites for Nonprofits .pdfInclusivity Essentials_ Creating Accessible Websites for Nonprofits .pdf
Inclusivity Essentials_ Creating Accessible Websites for Nonprofits .pdfTechSoup
 
INTRODUCTION TO CATHOLIC CHRISTOLOGY.pptx
INTRODUCTION TO CATHOLIC CHRISTOLOGY.pptxINTRODUCTION TO CATHOLIC CHRISTOLOGY.pptx
INTRODUCTION TO CATHOLIC CHRISTOLOGY.pptxHumphrey A Beña
 
ECONOMIC CONTEXT - PAPER 1 Q3: NEWSPAPERS.pptx
ECONOMIC CONTEXT - PAPER 1 Q3: NEWSPAPERS.pptxECONOMIC CONTEXT - PAPER 1 Q3: NEWSPAPERS.pptx
ECONOMIC CONTEXT - PAPER 1 Q3: NEWSPAPERS.pptxiammrhaywood
 
GRADE 4 - SUMMATIVE TEST QUARTER 4 ALL SUBJECTS
GRADE 4 - SUMMATIVE TEST QUARTER 4 ALL SUBJECTSGRADE 4 - SUMMATIVE TEST QUARTER 4 ALL SUBJECTS
GRADE 4 - SUMMATIVE TEST QUARTER 4 ALL SUBJECTSJoshuaGantuangco2
 
4.18.24 Movement Legacies, Reflection, and Review.pptx
4.18.24 Movement Legacies, Reflection, and Review.pptx4.18.24 Movement Legacies, Reflection, and Review.pptx
4.18.24 Movement Legacies, Reflection, and Review.pptxmary850239
 

Último (20)

YOUVE_GOT_EMAIL_PRELIMS_EL_DORADO_2024.pptx
YOUVE_GOT_EMAIL_PRELIMS_EL_DORADO_2024.pptxYOUVE_GOT_EMAIL_PRELIMS_EL_DORADO_2024.pptx
YOUVE_GOT_EMAIL_PRELIMS_EL_DORADO_2024.pptx
 
Raw materials used in Herbal Cosmetics.pptx
Raw materials used in Herbal Cosmetics.pptxRaw materials used in Herbal Cosmetics.pptx
Raw materials used in Herbal Cosmetics.pptx
 
ACC 2024 Chronicles. Cardiology. Exam.pdf
ACC 2024 Chronicles. Cardiology. Exam.pdfACC 2024 Chronicles. Cardiology. Exam.pdf
ACC 2024 Chronicles. Cardiology. Exam.pdf
 
Procuring digital preservation CAN be quick and painless with our new dynamic...
Procuring digital preservation CAN be quick and painless with our new dynamic...Procuring digital preservation CAN be quick and painless with our new dynamic...
Procuring digital preservation CAN be quick and painless with our new dynamic...
 
ECONOMIC CONTEXT - LONG FORM TV DRAMA - PPT
ECONOMIC CONTEXT - LONG FORM TV DRAMA - PPTECONOMIC CONTEXT - LONG FORM TV DRAMA - PPT
ECONOMIC CONTEXT - LONG FORM TV DRAMA - PPT
 
Gas measurement O2,Co2,& ph) 04/2024.pptx
Gas measurement O2,Co2,& ph) 04/2024.pptxGas measurement O2,Co2,& ph) 04/2024.pptx
Gas measurement O2,Co2,& ph) 04/2024.pptx
 
ANG SEKTOR NG agrikultura.pptx QUARTER 4
ANG SEKTOR NG agrikultura.pptx QUARTER 4ANG SEKTOR NG agrikultura.pptx QUARTER 4
ANG SEKTOR NG agrikultura.pptx QUARTER 4
 
ENGLISH 7_Q4_LESSON 2_ Employing a Variety of Strategies for Effective Interp...
ENGLISH 7_Q4_LESSON 2_ Employing a Variety of Strategies for Effective Interp...ENGLISH 7_Q4_LESSON 2_ Employing a Variety of Strategies for Effective Interp...
ENGLISH 7_Q4_LESSON 2_ Employing a Variety of Strategies for Effective Interp...
 
FINALS_OF_LEFT_ON_C'N_EL_DORADO_2024.pptx
FINALS_OF_LEFT_ON_C'N_EL_DORADO_2024.pptxFINALS_OF_LEFT_ON_C'N_EL_DORADO_2024.pptx
FINALS_OF_LEFT_ON_C'N_EL_DORADO_2024.pptx
 
HỌC TỐT TIẾNG ANH 11 THEO CHƯƠNG TRÌNH GLOBAL SUCCESS ĐÁP ÁN CHI TIẾT - CẢ NĂ...
HỌC TỐT TIẾNG ANH 11 THEO CHƯƠNG TRÌNH GLOBAL SUCCESS ĐÁP ÁN CHI TIẾT - CẢ NĂ...HỌC TỐT TIẾNG ANH 11 THEO CHƯƠNG TRÌNH GLOBAL SUCCESS ĐÁP ÁN CHI TIẾT - CẢ NĂ...
HỌC TỐT TIẾNG ANH 11 THEO CHƯƠNG TRÌNH GLOBAL SUCCESS ĐÁP ÁN CHI TIẾT - CẢ NĂ...
 
Keynote by Prof. Wurzer at Nordex about IP-design
Keynote by Prof. Wurzer at Nordex about IP-designKeynote by Prof. Wurzer at Nordex about IP-design
Keynote by Prof. Wurzer at Nordex about IP-design
 
Earth Day Presentation wow hello nice great
Earth Day Presentation wow hello nice greatEarth Day Presentation wow hello nice great
Earth Day Presentation wow hello nice great
 
YOUVE GOT EMAIL_FINALS_EL_DORADO_2024.pptx
YOUVE GOT EMAIL_FINALS_EL_DORADO_2024.pptxYOUVE GOT EMAIL_FINALS_EL_DORADO_2024.pptx
YOUVE GOT EMAIL_FINALS_EL_DORADO_2024.pptx
 
DATA STRUCTURE AND ALGORITHM for beginners
DATA STRUCTURE AND ALGORITHM for beginnersDATA STRUCTURE AND ALGORITHM for beginners
DATA STRUCTURE AND ALGORITHM for beginners
 
ISYU TUNGKOL SA SEKSWLADIDA (ISSUE ABOUT SEXUALITY
ISYU TUNGKOL SA SEKSWLADIDA (ISSUE ABOUT SEXUALITYISYU TUNGKOL SA SEKSWLADIDA (ISSUE ABOUT SEXUALITY
ISYU TUNGKOL SA SEKSWLADIDA (ISSUE ABOUT SEXUALITY
 
Inclusivity Essentials_ Creating Accessible Websites for Nonprofits .pdf
Inclusivity Essentials_ Creating Accessible Websites for Nonprofits .pdfInclusivity Essentials_ Creating Accessible Websites for Nonprofits .pdf
Inclusivity Essentials_ Creating Accessible Websites for Nonprofits .pdf
 
INTRODUCTION TO CATHOLIC CHRISTOLOGY.pptx
INTRODUCTION TO CATHOLIC CHRISTOLOGY.pptxINTRODUCTION TO CATHOLIC CHRISTOLOGY.pptx
INTRODUCTION TO CATHOLIC CHRISTOLOGY.pptx
 
ECONOMIC CONTEXT - PAPER 1 Q3: NEWSPAPERS.pptx
ECONOMIC CONTEXT - PAPER 1 Q3: NEWSPAPERS.pptxECONOMIC CONTEXT - PAPER 1 Q3: NEWSPAPERS.pptx
ECONOMIC CONTEXT - PAPER 1 Q3: NEWSPAPERS.pptx
 
GRADE 4 - SUMMATIVE TEST QUARTER 4 ALL SUBJECTS
GRADE 4 - SUMMATIVE TEST QUARTER 4 ALL SUBJECTSGRADE 4 - SUMMATIVE TEST QUARTER 4 ALL SUBJECTS
GRADE 4 - SUMMATIVE TEST QUARTER 4 ALL SUBJECTS
 
4.18.24 Movement Legacies, Reflection, and Review.pptx
4.18.24 Movement Legacies, Reflection, and Review.pptx4.18.24 Movement Legacies, Reflection, and Review.pptx
4.18.24 Movement Legacies, Reflection, and Review.pptx
 

Csla 130319073823-phpapp01-140821210430-phpapp02

  • 1. A SEMINAR ON LOW POWER AND AREA EFFICIENT CARRY SELECT ADDER BY Jayaprakash Nagaruru
  • 2. Objective To design a Carry Select Adder(CSLA) with a optimum utilization of area and power Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 2
  • 3. Agenda • Introduction • Carry Select Adder • Delay and Area Evaluation • Principle Behind Modification • Modified CSLA • Delay and Area Evaluation • Implementation Results • Conclusion Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 3
  • 4. Introduction • Efficient design implementation of any ASIC requires an appropriate style which meet the design goals  Area  Power  Speed • Multi-dimensional Trade off Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 4
  • 5. Carry Select Adder • Ripple carry adder & MUX Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 5
  • 6. Regular CSLA Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 6
  • 7. Delay and Power Evaluation Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 7
  • 8. Contd… Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 8
  • 9. Regular CSLA Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 9
  • 10. Principle Behind Modification • Binary to Excess-1 Convertor Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 10
  • 11. CSLA with BEC Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 11
  • 12. Modified CSLA Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 12
  • 13. Delay and Power Evaluation of modified CSLA Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 13
  • 14. Comparison Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 14
  • 15. Implementation Results • Typical ASIC flow Using 0.18u Technology for regular and modified CSLA Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 15
  • 16. Graphical Analysis Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 16
  • 17. Conclusion No. of Bits Area Reduction (%) 8 9.7 16 15 32 16.7 64 17.4 Power Reduction (%) 7.6 10.56 13.63 15.46 Delay Overhead (%) 14 9.8 6.7 3.76 Power Delay Product(%) 5.2 1.76 8.18 12.28 Area Delay Product(%) 2.9 6.7 11 14.4 • Despite with a little delay overhead a optimized carry select adder has been designed Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 17
  • 18. Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 18
  • 19. References Bibliography • IEEE 2012 paper on Low Power & Area Efficient CSLA by B Ram Kumar & H M Kittur • J M Rabaey Digital Integrated Circuits • IJCE 2012 paper on VLSI Realization Of Fast Carry Adder in Binary Excess by Santhosh Kannan and Bhanumathi Webography • http://en.wikipedia.org/wiki/Ca rry-select_adder • http://ieeexplore.ieee.org/xpl /login.jsp?tp=&arnumber=540 7919&url=http%3A%2F%2Fiee explore.ieee.org%2Fxpls%2Fab s_all.jsp%3Farnumber%3D540 7919 Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 19
  • 20. Tuesday, March 19, 2013 Low Power & Area Efficient CSLA 20