The document describes a proposed LP-HS logic style and its application in designing an ultra low power high speed multiplier accumulator (MAC) unit for digital signal processing applications. The LP-HS logic is derived from an existing constant delay logic style to reduce power and delay. A MAC unit is designed using both the constant delay logic and proposed LP-HS logic. Simulation results in 45nm, 32nm, 22nm, and 16nm CMOS technologies show the LP-HS logic MAC unit achieves up to 94% reduction in power delay product compared to the constant delay logic MAC unit. Therefore, the proposed LP-HS logic is concluded to be better suited for high performance, low power MAC unit design.