1. International Journal JOURNAL OF ADVANCED RESEARCH Technology (IJARET),
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ISSN 0976 – 6480(Print), ISSN 0976 – 6499(Online) Volume 5, Issue 1, January (2014), © IAEME
AND TECHNOLOGY (IJARET)
ISSN 0976 - 6480 (Print)
ISSN 0976 - 6499 (Online)
Volume 5, Issue 1, January (2014), pp. 138-144
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IJARET
©IAEME
MULTI-INPUT QUASI-FLOATING GATE MOSFETS WITH ANALOG
INVERTER USED IN CIRCUITS
S.K Bisoi,
G. Devi
ABSTRACT
The multiple-input floating gate transistors were used to simplify the design of multiple
valued logic. The Quasi-floating gate node have a well defined DC operating point. The multi-input
quasi-floating gate is used for low voltage applications because its effective threshold voltage will be
controllered to a low value.
Keywords: Quasi-floating gate, multi-input quasi-floating gate, analog inverter.
1.
INTRODUCTION
The floating gate MOS transistor is generated by forming an additional conductive layer
between control terminal and channel DS isolated from environment called floating gate [10].
Multiple-input floating gate MOS transistor is a floating gate transistor with multiple control gate.
The input control gates are capacitively coupled to the floating gate [8,9].
Floating gate is contacting with the channel through the capacity of oxide layer and with
source, drain and bulk. The values of these capacities depend on the area of input gate, floating gate
and chennel as well as on thickness of oxide layer [5,6]. The whole MIFGMOS transistor made on
semiconductor. The main goals are to release the traditional semi-floating designs from recharge
mode and to implement in continuous mode. Quasi floating gate can compute multiple valued signals
and obtain higher frequencies [1,2,3,4]. The analog inverter is a key element in multiple valued logic.
The transfer characteristic of the analog inverter is determined by capacitor division factor
Ki =
Ci
C Total
and Vout = Vdd − Vin
where Vin and Vout are the voltages on the input and output terminal and Vdd is supply voltage.
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2. International Journal of Advanced Research in Engineering and Technology (IJARET),
ISSN 0976 – 6480(Print), ISSN 0976 – 6499(Online) Volume 5, Issue 1, January (2014), © IAEME
II.
MULTI INPUT QUASI FLOATING GATE
Since Quasi floating gate node have a well defined DC operating point and this technique is
used for low voltage applications, so that multi input QFG can compute multiple valued signals and
obtain higher frequencies. To operate the function of CMOS transistors at the output of inverter, the
gate terminals of inverter must be biased through the DC supply voltage and that will be provided
through the coupling capacitors C gb and C gb' and hence, Quasi floating MOS gates are proposed to
provide a DC shift to the combined AC signal.
The quasi floating MOS gates are operating at +5v or -5v depending on n-type and p-type
MOS gates. This supply voltage or some portion of supply voltage may pass through the channel
from source to drain or drain to source depending on n-type and p-type MOS gate. The leakage
resistors and the parallel capacitors are operate in such a manner that the combined AC signals can
pass through the capacitors and DC signals can block through the capacitors in the Quasi floating
MOS gates so that the DC shifting on positive side or negative side of the combined AC signal can
be done depending on types of MOS gates.
The shifting of AC signals are required to only provide the debiasing to the gate terminals of
CMOS inverter and that is not directly provided at gate terminal, but through the coupling capacitors
which can store the DC voltage due to high impedance and pass the AC signal without shift due to
low impedance.
The coupling capacitors are DC block capacitors i.e. in DC signals, f=0Hz.
Xc =
1
ωc
=
1
= ∞ Ω (Open circuit path)
2πfc
and in AC signal, f = very high = ∞ Hz
Xc =
1
1
=
= 0Ω (Short circuit path)
ω c 2πfc
that is the coupling capacitors are short circuit paths.
At input side terminals the capacitors are provided to pass the high frequency signals only
and if any DC signal or low frequency signals accommodate with the original signals that can be
nullify and pure form of high frequency signals can easily pass through the capacitors.
The combinations of signals are generated at the node point which then passes through the
quasi floating MOS gates and then MOS inverter operation obtain.
139

3. International Journal of Advanced Research in Engineering and Technology (IJARET),
ISSN 0976 – 6480(Print), ISSN 0976 – 6499(Online) Volume 5, Issue 1, January (2014), © IAEME
C i = C1 ,C 2 ,C3 ,C ds ( with Rleak n − mos ),C gb ( at the inverter )
C 4 ,C5 ,C 6 ,C'ds ( with Rleak p − mos ),C' gb ( at the inverter )
C sd ( at the output )
Vi = V1 ,V2 ,V3 Vqfg1
V4 ,V5 ,V6 Vqfg 2 RL → Load Re sis tan ce at Output
III.
SIMULATION AND MODEL
VQFG = Vin
s Rleak CTotal
1 + s Rleak CTotal
n
where C total = ∑ C i + CGS + CGD + CGB + C'GD
i =1
and
Vin =
C total
n
( ∑ C iVi + CGSVS + CGDVD + CGBVB )
i =1

 s Rleak CTotal 
 ∑ C iVi + CGSVS + CGDVD + CGBVB 



 1 + s R C
C total  i =1
leak Total 

 s R' leak C'Total
1  n
 ∑ C i ' Vi ' + CGSVS + CGDVD + CGBVB 
=

 1 + s R'
C' total  i =1
leak C'Total

1
VQFG1 =
VQFG 2
1
n




n
where, C total = ∑ C i ' + CGS + CGD + CGB + C"GD
i =1
and
Vin =
1
C'total
n
( ∑ C i ' Vi ' + CGSVS + CGDVD + CGBVB )
i =1
It is in Ohmic mode or triod region that is VGS > Vth and VDS < (VQFGS − Vth )
I DS = µ nCox
ω


(VQFGS − Vth )VDS − VDS 
L
2 
2


1st base band signal
2nd base band signal
0.5
0.4
0.4
0.3
0.3
0.2
am plitude in volt
am plitude in volt
0.2
0.1
0
-0.1
0.1
0
-0.1
-0.2
-0.2
-0.3
-0.3
-0.4
-0.5
0
0.01
0.02
0.03
0.04
time in sec.
0.05
0.06
-0.4
0.07
Fig.1
0
0.01
0.02
0.03
0.04
time in sec.
Fig. 2
140
0.05
0.06
0.07

4. International Journal of Advanced Research in Engineering and Technology (IJARET),
ISSN 0976 – 6480(Print), ISSN 0976 – 6499(Online) Volume 5, Issue 1, January (2014), © IAEME
-7
3rd base band signal
0.3
2
0.2
Composed base band signals with capacitors,"Vin1"
1.5
1
am plitude in v olt
0.1
am plitude in v olt
x 10
0
-0.1
-0.2
0
-0.5
-1
-0.3
-0.4
0.5
-1.5
0
0.01
0.02
0.03
0.04
time in sec.
0.05
0.06
-2
0.07
0
0.01
0.02
Fig. 3
0.05
0.06
0.07
0.05
0.06
0.07
0.05
0.06
0.07
Fig. 4
Net output due to V1,V2,V3,"Vin"
Vqfg1 sigal
-4.014
0.986
-4.016
0.984
-4.018
am plitude in volts
0.988
am plitude in volts
0.03
0.04
time in sec.
0.982
0.98
0.978
-4.02
-4.022
-4.024
0.976
-4.026
0.974
-4.028
0.972
0
0.01
0.02
0.03
0.04
time in sec.
0.05
0.06
-4.03
0.07
0
0.01
0.02
Fig. 5
0.03
0.04
time in sec.
Fig. 6
4th base band signal
5th base band signal
0.1
0.2
0.08
0.15
0.06
0.1
am plitude in v olt
am plitude in v olt
0.04
0.02
0
-0.02
0.05
0
-0.05
-0.04
-0.1
-0.06
-0.15
-0.08
-0.1
0
0.01
0.02
0.03
0.04
time in sec.
0.05
0.06
-0.2
0.07
Fig. 7
0
0.01
0.02
0.03
0.04
time in sec.
Fig. 8
141

5. International Journal of Advanced Research in Engineering and Technology (IJARET),
ISSN 0976 – 6480(Print), ISSN 0976 – 6499(Online) Volume 5, Issue 1, January (2014), © IAEME
-7
6th base band signal
0.3
0.2
Composed base band signals with capacitors,"Vin3"
3
2
a m plitud e in v o lt
0.1
a m p lit u d e in v o lt
x 10
4
0
-0.1
-0.2
0
-1
-2
-0.3
-0.4
1
-3
0
0.01
0.02
0.03
0.04
time in sec.
0.05
0.06
-4
0.07
0
0.01
0.02
Fig. 9
0.03
0.04
time in sec.
0.05
0.06
0.07
0.05
0.06
0.07
0.06
0.07
Fig. 10
Vi2
Vqfg2 sigal
1
6
0.995
5.995
0.99
5.99
0.985
5.985
0.98
5.98
0.975
5.975
0.97
5.97
0.965
0
0.01
0.02
0.03
0.04
0.05
0.06
5.965
0.07
0
0.01
0.02
Fig. 11
-3
8.06
0.04
Fig. 12
Drain to source saturation current,Ids2"
Drain to source saturation current,Ids1"
x 10
0.03
-0.0108
-0.0108
8.055
-0.0108
8.05
Current in m A
Current in m A
-0.0108
8.045
8.04
-0.0108
-0.0108
-0.0109
8.035
-0.0109
8.03
8.025
-0.0109
0
0.01
0.02
0.03
0.04
0.05
Voltage in x- axis,Vqfg1
0.06
-0.0109
0.07
Fig. 13
0
0.01
0.02
0.03
0.04
0.05
Voltage in x- axis,Vqfg2
Fig. 14
142

6. International Journal of Advanced Research in Engineering and Technology (IJARET),
ISSN 0976 – 6480(Print), ISSN 0976 – 6499(Online) Volume 5, Issue 1, January (2014), © IAEME
Voltage across load,Vout1
Voltage across load,Vout2
0.806
-1.082
-1.0825
0.8055
-1.083
0.805
C urrent in m A
Current in m A
-1.0835
0.8045
0.804
-1.084
-1.0845
-1.085
0.8035
-1.0855
0.803
0.8025
-1.086
0
0.01
0.02
0.03
0.04
0.05
Voltage in x- axis,Vqfg2
0.06
-1.0865
0.07
Fig. 15
IV.
0
0.01
0.02
0.03
0.04
0.05
Voltage in x- axis,Vqfg2
0.06
0.07
Fig. 16
CONCLUSION
In this paper we have presented a new multi-input Quasi floating gate with analog inverter
used in circuit. It offers better frequency response with larger band width and large leakage
resistance needs less chip area as compared to its multiple input floating gate technique.
REFERENCE
[1]
J. Ramirez – Angulo, C.A. Urquidi, R.G. Carvajal and F.M. Chavero, “Very low-voltage
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[2] I. Seo and R.M. Fox, “Comparison of quasi/pseudo floating gate techniques and low voltage
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[8] L. Topor – Kaminski, P. Holajn, “Multiple – input floating gate MOS transistor in Analogue
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[9] S.K. Bisoi, G. Devi, “Multi-input Multi Pseudo Floating Gates used in circuits”, IJEAT,
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7. International Journal of Advanced Research in Engineering and Technology (IJARET),
ISSN 0976 – 6480(Print), ISSN 0976 – 6499(Online) Volume 5, Issue 1, January (2014), © IAEME
AUTHOR’S INFORMATION
Sunil Bisoi is studying for his Ph.D in the field of Neural networks in Utkal
University, His research activities and interest include VLSI realization of
Neural networks and analogue integrated circuits and systems. Bisoi received the
Engineering degree from Utkal University. He is an Associate Professor of
ENTC department in Orissa Engineering College, Odisha.
Dr. Gayatri Devi heads the PG department of computer science and
engineering at Ajay Binay Institute of Technology of Odisha. Her current field of
interest in MOS integrated circuits and systems and application of Neural
Networks.
Devi received PG degree in Math from Utkal University and engineering
degree (B.Tech in ETC and M.Tech in CSC) from Raisthan Deemed University
and Ph.d & D.Sc degree from Utkal University of Odisha. She is a member of
IEEE, Odisha Information technology of society and Odisha Mathematical
Society.
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