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BioEvo technical seminars GNU/Make and bioinformatics G.M. Dall'Olio Barcelona, 06/02/2009
Original problem statement ,[object Object]
g++ -c main.cpp; g++ -c func.cpp; g++ main.o func.o
rm *.o ,[object Object]
Shell commands in bioinformatics ,[object Object]
perl/python/R/other scripts
Many suites of binary programs (emboss, phylip, blast, t-coffee, plink, genepop, gromacs, rosetta...)
etc...
Common problem ,[object Object]
Execute these commands only when necessary (don't calculate again some results, if they have already been calculated)
GNU/make ,[object Object]
It is a declarative programming language
It belongs to a class of softwares called 'automated build tools'
Simplest Makefile example ,[object Object],[object Object]
Simplest Makefile example Makefile rule Target of the rule Commands associated with the rule This is a tabulation (not 8 spaces)
Simplest Makefile example ,[object Object]
Write these instructions in it: print_hello : echo 'Hello, world!!'
Then, open a terminal and type: This is a tabulation (<Tab> key) ,[object Object]
Simplest Makefile example
Simplest Makefile example –  explanation ,[object Object]
When we type 'make print_hello', it executes any procedure (target) called 'print_hello' in the makefile
It then shows the commands executed and their output
Tip1: the 'Makefile' file ,[object Object]
If you omit this option, make will look for any file called 'Makefile' in the current directory
make -f Makefile all is equivalent to: make all
A sligthly longer example ,[object Object]
For example, this ' print_hello ' rule contains 5 commands
Note: ignore the '@' thing, it is only to disable verbose mode (explained later)
A more complex example
Make - advantages ,[object Object]
It allows you to use command-line tools which are more flexible;
Combined with a revision control software, it makes possible to reproduce all the operations made to your data;
Second part A closer look at make syntax (target and commands)
The target syntax ,[object Object]
The target syntax ,[object Object]
Everytime you call a make rule (example: 'make all'), the program looks for a file called like the target name (e.g. 'all', 'clean', 'inputdata.txt', 'results.txt')
The rule is executed only if that file doesn't exists.
Filename as target names ,[object Object]
Filename as target names ,[object Object]
When we call ' make testfile.txt ', make checks if a file called 'testfile.txt' already exists.
Filename as target names The commands associated with the rule ' testfile.txt ' are executed only if that file doesn't exists already
Multiple target definition ,[object Object]
You can retrieve the matched target with the special variable $@
Special characters ,[object Object]
For example, a rule with the target: %.txt : .... would be activated by any file ending with '.txt' ,[object Object],[object Object]
Special character % / creating more than a file at a time
Makefile – cluster support ,[object Object]
If we use the '-j' option when invoking make, the three processess will be launched in parallel
[object Object],The commands syntax
Inactivating verbose mode ,[object Object],Differences here
Skipping errors ,[object Object]
Example:  ,[object Object]
'-mkdir /var' will cause an error anyway, but gnu/make will ignore it
Moving throught directories ,[object Object]
So, this: lsvar : cd /var ls
Won't work (it will list only the files in the current directory, not /var)
The solution is to put everything in a single process:
lsvar : (cd /var; ls)
Third part Prerequisites and conditional execution
[object Object],The commands syntax
Real Makefile-rule syntax ,[object Object]

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